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GET /api/patches/132339/?format=api
{ "id": 132339, "url": "http://patchwork.dpdk.org/api/patches/132339/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231005194907.557517-8-nicolas.chautru@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231005194907.557517-8-nicolas.chautru@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231005194907.557517-8-nicolas.chautru@intel.com", "date": "2023-10-05T19:49:02", "name": "[v5,07/12] baseband/acc: adding VRB2 device variant", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "bb6478bfae1a5ea9c832eb80cff2ef55d33536d6", "submitter": { "id": 1314, "url": "http://patchwork.dpdk.org/api/people/1314/?format=api", "name": "Chautru, Nicolas", "email": "nicolas.chautru@intel.com" }, "delegate": { "id": 2642, "url": "http://patchwork.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231005194907.557517-8-nicolas.chautru@intel.com/mbox/", "series": [ { "id": 29744, "url": "http://patchwork.dpdk.org/api/series/29744/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29744", "date": "2023-10-05T19:48:55", "name": "VRB2 bbdev PMD introduction", "version": 5, "mbox": "http://patchwork.dpdk.org/series/29744/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132339/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132339/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id B663C426C5;\n\tThu, 5 Oct 2023 21:57:00 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BBA4640A72;\n\tThu, 5 Oct 2023 21:56:16 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id D4B83402CF\n for <dev@dpdk.org>; Thu, 5 Oct 2023 21:56:07 +0200 (CEST)", "from fmsmga007.fm.intel.com ([10.253.24.52])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 Oct 2023 12:56:06 -0700", "from spr-npg-bds1-eec2.sn.intel.com (HELO spr-npg-bds1-eec2..)\n ([10.233.181.123])\n by fmsmga007.fm.intel.com with ESMTP; 05 Oct 2023 12:56:06 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1696535768; x=1728071768;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=RP+ushiuk6O/R9o35upBM1k5MMJ27qP4q12rAFuhPXI=;\n b=h38QYPTKn9h/2cc3OykZzFIRJS3WAFqyjBvBrfe8/crbnE71CEOGuBU7\n a3WRFF6fsjGUCQYDEd5FbDay84if44lm1EiExxnwqW85f8R+Viqs39fB2\n OTcFtPQuxhFb3OEOqRDk2M7lytxmDF0f0Otrq7cTy2BO1TaLxKBjbAPy1\n el17RmJA+qJX3rOtkRuIWyYZo1BM2IOdA24xoh5epsv2uZiaE5DlOmycg\n QIaf6uJ5WuClGqrHrhIjPqKMVbguASfleIhdsdB2tAcA/yu7IbwIiAO0M\n yF3d2dOBcnpOLvCN81u7r2/z0c/pFgYpuACLXMFJs7mFNzioSLZT2CK6C Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10854\"; a=\"386432662\"", "E=Sophos;i=\"6.03,203,1694761200\"; d=\"scan'208\";a=\"386432662\"", "E=McAfee;i=\"6600,9927,10854\"; a=\"755600308\"", "E=Sophos;i=\"6.03,203,1694761200\"; d=\"scan'208\";a=\"755600308\"" ], "X-ExtLoop1": "1", "From": "Nicolas Chautru <nicolas.chautru@intel.com>", "To": "dev@dpdk.org,\n\tmaxime.coquelin@redhat.com", "Cc": "hemant.agrawal@nxp.com, david.marchand@redhat.com,\n hernan.vargas@intel.com,\n Nicolas Chautru <nicolas.chautru@intel.com>", "Subject": "[PATCH v5 07/12] baseband/acc: adding VRB2 device variant", "Date": "Thu, 5 Oct 2023 19:49:02 +0000", "Message-Id": "<20231005194907.557517-8-nicolas.chautru@intel.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20231005194907.557517-1-nicolas.chautru@intel.com>", "References": "<20231005194907.557517-1-nicolas.chautru@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "No functionality exposed only device enumeration and\nconfiguration.\n\nSigned-off-by: Nicolas Chautru <nicolas.chautru@intel.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n doc/guides/bbdevs/features/vrb2.ini | 14 ++\n doc/guides/bbdevs/index.rst | 1 +\n doc/guides/bbdevs/vrb2.rst | 206 +++++++++++++++++++++++++\n doc/guides/rel_notes/release_23_11.rst | 3 +\n drivers/baseband/acc/rte_vrb_pmd.c | 156 +++++++++++++++----\n drivers/baseband/acc/vrb2_pf_enum.h | 124 +++++++++++++++\n drivers/baseband/acc/vrb2_vf_enum.h | 121 +++++++++++++++\n drivers/baseband/acc/vrb_pmd.h | 161 ++++++++++++++++++-\n 8 files changed, 751 insertions(+), 35 deletions(-)\n create mode 100644 doc/guides/bbdevs/features/vrb2.ini\n create mode 100644 doc/guides/bbdevs/vrb2.rst\n create mode 100644 drivers/baseband/acc/vrb2_pf_enum.h\n create mode 100644 drivers/baseband/acc/vrb2_vf_enum.h", "diff": "diff --git a/doc/guides/bbdevs/features/vrb2.ini b/doc/guides/bbdevs/features/vrb2.ini\nnew file mode 100644\nindex 0000000000..23ca6990b7\n--- /dev/null\n+++ b/doc/guides/bbdevs/features/vrb2.ini\n@@ -0,0 +1,14 @@\n+;\n+; Supported features of the 'Intel vRAN Boost v2' baseband driver.\n+;\n+; Refer to default.ini for the full list of available PMD features.\n+;\n+[Features]\n+Turbo Decoder (4G) = Y\n+Turbo Encoder (4G) = Y\n+LDPC Decoder (5G) = Y\n+LDPC Encoder (5G) = Y\n+LLR/HARQ Compression = Y\n+FFT/SRS = Y\n+External DDR Access = N\n+HW Accelerated = Y\ndiff --git a/doc/guides/bbdevs/index.rst b/doc/guides/bbdevs/index.rst\nindex 77d4c54664..269157d77f 100644\n--- a/doc/guides/bbdevs/index.rst\n+++ b/doc/guides/bbdevs/index.rst\n@@ -15,4 +15,5 @@ Baseband Device Drivers\n fpga_5gnr_fec\n acc100\n vrb1\n+ vrb2\n la12xx\ndiff --git a/doc/guides/bbdevs/vrb2.rst b/doc/guides/bbdevs/vrb2.rst\nnew file mode 100644\nindex 0000000000..2a30002e05\n--- /dev/null\n+++ b/doc/guides/bbdevs/vrb2.rst\n@@ -0,0 +1,206 @@\n+.. SPDX-License-Identifier: BSD-3-Clause\n+ Copyright(c) 2023 Intel Corporation\n+\n+.. include:: <isonum.txt>\n+\n+Intel\\ |reg| vRAN Boost v2 Poll Mode Driver (PMD)\n+=================================================\n+\n+The Intel\\ |reg| vRAN Boost integrated accelerator enables\n+cost-effective 4G and 5G next-generation virtualized Radio Access Network (vRAN)\n+solutions.\n+The Intel vRAN Boost v2.0 (VRB2 in the code) is specifically integrated on the\n+Intel\\ |reg| Xeon\\ |reg| Granite Rapids-D Process (GNR-D).\n+\n+Features\n+--------\n+\n+Intel vRAN Boost v2.0 includes a 5G Low Density Parity Check (LDPC) encoder/decoder,\n+rate match/dematch, Hybrid Automatic Repeat Request (HARQ) with access to DDR\n+memory for buffer management, a 4G Turbo encoder/decoder,\n+a Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload\n+for the 5G Sounding Reference Signal (SRS), a MLD-TS accelerator, a Queue Manager (QMGR),\n+and a DMA subsystem.\n+There is no dedicated on-card memory for HARQ, the coherent memory on the CPU side is being used.\n+\n+These hardware blocks provide the following features exposed by the PMD:\n+\n+- LDPC Encode in the Downlink (5GNR)\n+- LDPC Decode in the Uplink (5GNR)\n+- Turbo Encode in the Downlink (4G)\n+- Turbo Decode in the Uplink (4G)\n+- FFT processing\n+- MLD-TS processing\n+- Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF)\n+- Maximum of 2048 queues per VF\n+- Message Signaled Interrupts (MSIs)\n+\n+The Intel vRAN Boost v2.0 PMD supports the following bbdev capabilities:\n+\n+* For the LDPC encode operation:\n+ - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH``: set to attach CRC24B to CB(s).\n+ - ``RTE_BBDEV_LDPC_RATE_MATCH``: if set then do not do Rate Match bypass.\n+ - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS``: if set then bypass interleaver.\n+ - ``RTE_BBDEV_LDPC_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data.\n+ - ``RTE_BBDEV_LDPC_ENC_CONCATENATION``: concatenate code blocks with bit granularity.\n+\n+* For the LDPC decode operation:\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK``: check CRC24B from CB(s).\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP``: drops CRC24B bits appended while decoding.\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK``: check CRC24A from CB(s).\n+ - ``RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK``: check CRC16 from CB(s).\n+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE``: provides an input for HARQ combining.\n+ - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE``: provides an input for HARQ combining.\n+ - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE``: disable early termination.\n+ - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data.\n+ - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION``: supports compression of the HARQ input/output.\n+ - ``RTE_BBDEV_LDPC_LLR_COMPRESSION``: supports LLR input compression.\n+ - ``RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION``: supports compression of the HARQ input/output.\n+ - ``RTE_BBDEV_LDPC_SOFT_OUT_ENABLE``: set the APP LLR soft output.\n+ - ``RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS``: set the APP LLR soft output after rate-matching.\n+ - ``RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS``: disables the de-interleaver.\n+\n+* For the turbo encode operation:\n+ - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH``: set to attach CRC24B to CB(s).\n+ - ``RTE_BBDEV_TURBO_RATE_MATCH``: if set then do not do Rate Match bypass.\n+ - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS``: set for encoder dequeue interrupts.\n+ - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS``: set to bypass RV index.\n+ - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data.\n+\n+* For the turbo decode operation:\n+ - ``RTE_BBDEV_TURBO_CRC_TYPE_24B``: check CRC24B from CB(s).\n+ - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE``: perform subblock de-interleave.\n+ - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS``: set for decoder dequeue interrupts.\n+ - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN``: set if negative LLR input is supported.\n+ - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP``: keep CRC24B bits appended while decoding.\n+ - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP``: option to drop the code block CRC after decoding.\n+ - ``RTE_BBDEV_TURBO_EARLY_TERMINATION``: set early termination feature.\n+ - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data.\n+ - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN``: set half iteration granularity.\n+ - ``RTE_BBDEV_TURBO_SOFT_OUTPUT``: set the APP LLR soft output.\n+ - ``RTE_BBDEV_TURBO_EQUALIZER``: set the turbo equalizer feature.\n+ - ``RTE_BBDEV_TURBO_SOFT_OUT_SATURATE``: set the soft output saturation.\n+ - ``RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH``: set to run an extra odd iteration after CRC match.\n+ - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT``: set if negative APP LLR output supported.\n+ - ``RTE_BBDEV_TURBO_MAP_DEC``: supports flexible parallel MAP engine decoding.\n+\n+* For the FFT operation:\n+ - ``RTE_BBDEV_FFT_WINDOWING``: flexible windowing capability.\n+ - ``RTE_BBDEV_FFT_CS_ADJUSTMENT``: flexible adjustment of Cyclic Shift time offset.\n+ - ``RTE_BBDEV_FFT_DFT_BYPASS``: set for bypass the DFT and get directly into iDFT input.\n+ - ``RTE_BBDEV_FFT_IDFT_BYPASS``: set for bypass the IDFT and get directly the DFT output.\n+ - ``RTE_BBDEV_FFT_WINDOWING_BYPASS``: set for bypass time domain windowing.\n+\n+* For the MLD-TS operation:\n+ - ``RTE_BBDEV_MLDTS_REP``: set to repeat and reuse channel across operations.\n+\n+Installation\n+------------\n+\n+Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.\n+\n+DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.\n+The bbdev test application has been tested with a configuration 40 x 1GB hugepages.\n+The hugepage configuration of a server may be examined using:\n+\n+.. code-block:: console\n+\n+ grep Huge* /proc/meminfo\n+\n+\n+Initialization\n+--------------\n+\n+When the device first powers up, its PCI Physical Functions (PF)\n+can be listed through these commands for Intel vRAN Boost v2:\n+\n+.. code-block:: console\n+\n+ sudo lspci -vd8086:57c2\n+\n+The physical and virtual functions are compatible with Linux UIO drivers:\n+``vfio`` (preferred) and ``igb_uio`` (legacy).\n+However, in order to work the 5G/4G FEC device first needs to be bound\n+to one of these Linux drivers through DPDK.\n+\n+\n+Configure the VFs through PF\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The PCI virtual functions must be configured before working or getting assigned\n+to VMs/Containers.\n+The configuration involves allocating the number of hardware queues, priorities,\n+load balance, bandwidth and other settings necessary for the device\n+to perform FEC functions.\n+\n+This configuration needs to be executed at least once after reboot or PCI FLR\n+and can be achieved by using the functions ``rte_acc_configure()``,\n+which sets up the parameters defined in the compatible ``rte_acc_conf`` structure.\n+\n+\n+Test Application\n+----------------\n+\n+The bbdev class is provided with a test application, ``test-bbdev.py``\n+and range of test data for testing the functionality of the device,\n+depending on the device's capabilities.\n+The test application is located under app/test-bbdev folder\n+and has the following options:\n+\n+.. code-block:: console\n+\n+ \"-p\", \"--testapp-path\": specifies path to the bbdev test app.\n+ \"-e\", \"--eal-params\": EAL arguments which are passed to the test app.\n+ \"-t\", \"--timeout\": Timeout in seconds (default=300).\n+ \"-c\", \"--test-cases\": Defines test cases to run. Run all if not specified.\n+ \"-v\", \"--test-vector\": Test vector path.\n+ \"-n\", \"--num-ops\": Number of operations to process on device (default=32).\n+ \"-b\", \"--burst-size\": Operations enqueue/dequeue burst size (default=32).\n+ \"-s\", \"--snr\": SNR in dB used when generating LLRs for bler tests.\n+ \"-s\", \"--iter_max\": Number of iterations for LDPC decoder.\n+ \"-l\", \"--num-lcores\": Number of lcores to run (default=16).\n+ \"-i\", \"--init-device\": Initialise PF device with default values.\n+\n+\n+To execute the test application tool using simple decode or encode data,\n+type one of the following:\n+\n+.. code-block:: console\n+\n+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_dec_default.data\n+ ./test-bbdev.py -c validation -n 64 -b 1 -v ./ldpc_enc_default.data\n+\n+\n+The test application ``test-bbdev.py``, supports the ability to configure the\n+PF device with a default set of values, if the \"-i\" or \"- -init-device\" option\n+is included. The default values are defined in test_bbdev_perf.c.\n+\n+\n+Test Vectors\n+~~~~~~~~~~~~\n+\n+In addition to the simple LDPC decoder and LDPC encoder tests,\n+bbdev also provides a range of additional tests under the test_vectors folder,\n+which may be useful.\n+The results of these tests will depend on the device capabilities which may\n+cause some test cases to be skipped, but no failure should be reported.\n+\n+\n+Alternate Baseband Device configuration tool\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+On top of the embedded configuration feature supported in test-bbdev using\n+\"- -init-device\" option mentioned above, there is also a tool available\n+to perform that device configuration using a companion application.\n+The ``pf_bb_config`` application notably enables then to run bbdev-test\n+from the VF and not only limited to the PF as captured above.\n+\n+See for more details: https://github.com/intel/pf-bb-config\n+\n+Specifically for the bbdev Intel vRAN Boost v2 PMD, the command below can be used\n+(note that ACC200 was used previously to refer to VRB2):\n+\n+.. code-block:: console\n+\n+ pf_bb_config VRB2 -c ./vrb2/vrb2_config_vf_5g.cfg\n+ test-bbdev.py -e=\"-c 0xff0 -a${VF_PCI_ADDR}\" -c validation -n 64 -b 64 -l 1 -v ./ldpc_dec_default.data\ndiff --git a/doc/guides/rel_notes/release_23_11.rst b/doc/guides/rel_notes/release_23_11.rst\nindex 333e1d95a2..668dd58ee3 100644\n--- a/doc/guides/rel_notes/release_23_11.rst\n+++ b/doc/guides/rel_notes/release_23_11.rst\n@@ -78,6 +78,9 @@ New Features\n * build: Optional libraries can now be selected with the new ``enable_libs``\n build option similarly to the existing ``enable_drivers`` build option.\n \n+* **Updated Intel vRAN Boost bbdev PMD.**\n+\n+ Added support for the new Intel vRAN Boost v2 device variant (GNR-D) within the unified driver.\n \n Removed Items\n -------------\ndiff --git a/drivers/baseband/acc/rte_vrb_pmd.c b/drivers/baseband/acc/rte_vrb_pmd.c\nindex 3907102934..b36dd6ccd8 100644\n--- a/drivers/baseband/acc/rte_vrb_pmd.c\n+++ b/drivers/baseband/acc/rte_vrb_pmd.c\n@@ -37,6 +37,15 @@ vrb1_queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id\n \t\treturn ((qgrp_id << 7) + (aq_id << 3) + VRB1_VfQmgrIngressAq);\n }\n \n+static inline uint32_t\n+vrb2_queue_offset(bool pf_device, uint8_t vf_id, uint8_t qgrp_id, uint16_t aq_id)\n+{\n+\tif (pf_device)\n+\t\treturn ((vf_id << 14) + (qgrp_id << 9) + (aq_id << 3) + VRB2_PfQmgrIngressAq);\n+\telse\n+\t\treturn ((qgrp_id << 9) + (aq_id << 3) + VRB2_VfQmgrIngressAq);\n+}\n+\n enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, MLD, NUM_ACC};\n \n /* Return the accelerator enum for a Queue Group Index. */\n@@ -228,7 +237,7 @@ fetch_acc_config(struct rte_bbdev *dev)\n \tstruct acc_device *d = dev->data->dev_private;\n \tstruct rte_acc_conf *acc_conf = &d->acc_conf;\n \tuint8_t acc, qg;\n-\tuint32_t reg_aq, reg_len0, reg_len1, reg0, reg1;\n+\tuint32_t reg_aq, reg_len0, reg_len1, reg_len2, reg_len3, reg0, reg1, reg2, reg3;\n \tuint32_t reg_mode, idx;\n \tstruct rte_acc_queue_topology *q_top = NULL;\n \tint qman_func_id[VRB_NUM_ACCS] = {ACC_ACCMAP_0, ACC_ACCMAP_1,\n@@ -252,32 +261,81 @@ fetch_acc_config(struct rte_bbdev *dev)\n \tacc_conf->num_vf_bundles = 1;\n \tinitQTop(acc_conf);\n \n-\treg0 = acc_reg_read(d, d->reg_addr->qman_group_func);\n-\treg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4);\n-\tfor (qg = 0; qg < d->num_qgroups; qg++) {\n-\t\treg_aq = acc_reg_read(d, d->queue_offset(d->pf_device, 0, qg, 0));\n-\t\tif (reg_aq & ACC_QUEUE_ENABLE) {\n-\t\t\tif (qg < ACC_NUM_QGRPS_PER_WORD)\n-\t\t\t\tidx = (reg0 >> (qg * 4)) & 0x7;\n+\tif (d->device_variant == VRB1_VARIANT) {\n+\t\treg0 = acc_reg_read(d, d->reg_addr->qman_group_func);\n+\t\treg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4);\n+\t\tfor (qg = 0; qg < d->num_qgroups; qg++) {\n+\t\t\treg_aq = acc_reg_read(d, d->queue_offset(d->pf_device, 0, qg, 0));\n+\t\t\tif (reg_aq & ACC_QUEUE_ENABLE) {\n+\t\t\t\tif (qg < ACC_NUM_QGRPS_PER_WORD)\n+\t\t\t\t\tidx = (reg0 >> (qg * 4)) & 0x7;\n+\t\t\t\telse\n+\t\t\t\t\tidx = (reg1 >> ((qg - ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;\n+\t\t\t\tif (idx < VRB1_NUM_ACCS) {\n+\t\t\t\t\tacc = qman_func_id[idx];\n+\t\t\t\t\tupdateQtop(acc, qg, acc_conf, d);\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Check the depth of the AQs. */\n+\t\treg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset);\n+\t\treg_len1 = acc_reg_read(d, d->reg_addr->depth_log1_offset);\n+\t\tfor (acc = 0; acc < NUM_ACC; acc++) {\n+\t\t\tqtopFromAcc(&q_top, acc, acc_conf);\n+\t\t\tif (q_top->first_qgroup_index < ACC_NUM_QGRPS_PER_WORD)\n+\t\t\t\tq_top->aq_depth_log2 =\n+\t\t\t\t\t\t(reg_len0 >> (q_top->first_qgroup_index * 4)) & 0xF;\n \t\t\telse\n-\t\t\t\tidx = (reg1 >> ((qg - ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;\n-\t\t\tif (idx < VRB1_NUM_ACCS) {\n-\t\t\t\tacc = qman_func_id[idx];\n-\t\t\t\tupdateQtop(acc, qg, acc_conf, d);\n+\t\t\t\tq_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index -\n+\t\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;\n+\t\t}\n+\t} else {\n+\t\treg0 = acc_reg_read(d, d->reg_addr->qman_group_func);\n+\t\treg1 = acc_reg_read(d, d->reg_addr->qman_group_func + 4);\n+\t\treg2 = acc_reg_read(d, d->reg_addr->qman_group_func + 8);\n+\t\treg3 = acc_reg_read(d, d->reg_addr->qman_group_func + 12);\n+\t\t/* printf(\"Debug Function %08x %08x %08x %08x\\n\", reg0, reg1, reg2, reg3);*/\n+\t\tfor (qg = 0; qg < VRB2_NUM_QGRPS; qg++) {\n+\t\t\treg_aq = acc_reg_read(d, vrb2_queue_offset(d->pf_device, 0, qg, 0));\n+\t\t\tif (reg_aq & ACC_QUEUE_ENABLE) {\n+\t\t\t\t/* printf(\"Qg enabled %d %x\\n\", qg, reg_aq);*/\n+\t\t\t\tif (qg / ACC_NUM_QGRPS_PER_WORD == 0)\n+\t\t\t\t\tidx = (reg0 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;\n+\t\t\t\telse if (qg / ACC_NUM_QGRPS_PER_WORD == 1)\n+\t\t\t\t\tidx = (reg1 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;\n+\t\t\t\telse if (qg / ACC_NUM_QGRPS_PER_WORD == 2)\n+\t\t\t\t\tidx = (reg2 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;\n+\t\t\t\telse\n+\t\t\t\t\tidx = (reg3 >> ((qg % ACC_NUM_QGRPS_PER_WORD) * 4)) & 0x7;\n+\t\t\t\tif (idx < VRB_NUM_ACCS) {\n+\t\t\t\t\tacc = qman_func_id[idx];\n+\t\t\t\t\tupdateQtop(acc, qg, acc_conf, d);\n+\t\t\t\t}\n \t\t\t}\n \t\t}\n-\t}\n \n-\t/* Check the depth of the AQs. */\n-\treg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset);\n-\treg_len1 = acc_reg_read(d, d->reg_addr->depth_log1_offset);\n-\tfor (acc = 0; acc < NUM_ACC; acc++) {\n-\t\tqtopFromAcc(&q_top, acc, acc_conf);\n-\t\tif (q_top->first_qgroup_index < ACC_NUM_QGRPS_PER_WORD)\n-\t\t\tq_top->aq_depth_log2 = (reg_len0 >> (q_top->first_qgroup_index * 4)) & 0xF;\n-\t\telse\n-\t\t\tq_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index -\n-\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;\n+\t\t/* Check the depth of the AQs. */\n+\t\treg_len0 = acc_reg_read(d, d->reg_addr->depth_log0_offset);\n+\t\treg_len1 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 4);\n+\t\treg_len2 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 8);\n+\t\treg_len3 = acc_reg_read(d, d->reg_addr->depth_log0_offset + 12);\n+\n+\t\tfor (acc = 0; acc < NUM_ACC; acc++) {\n+\t\t\tqtopFromAcc(&q_top, acc, acc_conf);\n+\t\t\tif (q_top->first_qgroup_index / ACC_NUM_QGRPS_PER_WORD == 0)\n+\t\t\t\tq_top->aq_depth_log2 = (reg_len0 >> ((q_top->first_qgroup_index %\n+\t\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;\n+\t\t\telse if (q_top->first_qgroup_index / ACC_NUM_QGRPS_PER_WORD == 1)\n+\t\t\t\tq_top->aq_depth_log2 = (reg_len1 >> ((q_top->first_qgroup_index %\n+\t\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;\n+\t\t\telse if (q_top->first_qgroup_index / ACC_NUM_QGRPS_PER_WORD == 2)\n+\t\t\t\tq_top->aq_depth_log2 = (reg_len2 >> ((q_top->first_qgroup_index %\n+\t\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;\n+\t\t\telse\n+\t\t\t\tq_top->aq_depth_log2 = (reg_len3 >> ((q_top->first_qgroup_index %\n+\t\t\t\t\t\tACC_NUM_QGRPS_PER_WORD) * 4)) & 0xF;\n+\t\t}\n \t}\n \n \t/* Read PF mode. */\n@@ -469,7 +527,10 @@ allocate_info_ring(struct rte_bbdev *dev)\n \tphys_low = (uint32_t)(info_ring_iova);\n \tacc_reg_write(d, d->reg_addr->info_ring_hi, phys_high);\n \tacc_reg_write(d, d->reg_addr->info_ring_lo, phys_low);\n-\tacc_reg_write(d, d->reg_addr->info_ring_en, VRB1_REG_IRQ_EN_ALL);\n+\tif (d->device_variant == VRB1_VARIANT)\n+\t\tacc_reg_write(d, d->reg_addr->info_ring_en, VRB1_REG_IRQ_EN_ALL);\n+\telse\n+\t\tacc_reg_write(d, d->reg_addr->info_ring_en, VRB2_REG_IRQ_EN_ALL);\n \td->info_ring_head = (acc_reg_read(d, d->reg_addr->info_ring_ptr) &\n \t\t\t0xFFF) / sizeof(union acc_info_ring_data);\n \treturn 0;\n@@ -548,6 +609,10 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n \tacc_reg_write(d, d->reg_addr->dma_ring_dl4g_lo, phys_low);\n \tacc_reg_write(d, d->reg_addr->dma_ring_fft_hi, phys_high);\n \tacc_reg_write(d, d->reg_addr->dma_ring_fft_lo, phys_low);\n+\tif (d->device_variant == VRB2_VARIANT) {\n+\t\tacc_reg_write(d, d->reg_addr->dma_ring_mld_hi, phys_high);\n+\t\tacc_reg_write(d, d->reg_addr->dma_ring_mld_lo, phys_low);\n+\t}\n \t/*\n \t * Configure Ring Size to the max queue ring size\n \t * (used for wrapping purpose).\n@@ -581,6 +646,10 @@ vrb_setup_queues(struct rte_bbdev *dev, uint16_t num_queues, int socket_id)\n \tacc_reg_write(d, d->reg_addr->tail_ptrs_dl4g_lo, phys_low);\n \tacc_reg_write(d, d->reg_addr->tail_ptrs_fft_hi, phys_high);\n \tacc_reg_write(d, d->reg_addr->tail_ptrs_fft_lo, phys_low);\n+\tif (d->device_variant == VRB2_VARIANT) {\n+\t\tacc_reg_write(d, d->reg_addr->tail_ptrs_mld_hi, phys_high);\n+\t\tacc_reg_write(d, d->reg_addr->tail_ptrs_mld_lo, phys_low);\n+\t}\n \n \tret = allocate_info_ring(dev);\n \tif (ret < 0) {\n@@ -678,10 +747,17 @@ vrb_intr_enable(struct rte_bbdev *dev)\n \t\t\treturn ret;\n \t\t}\n \n-\t\tif (acc_dev->pf_device)\n-\t\t\tmax_queues = VRB1_MAX_PF_MSIX;\n-\t\telse\n-\t\t\tmax_queues = VRB1_MAX_VF_MSIX;\n+\t\tif (d->device_variant == VRB1_VARIANT) {\n+\t\t\tif (acc_dev->pf_device)\n+\t\t\t\tmax_queues = VRB1_MAX_PF_MSIX;\n+\t\t\telse\n+\t\t\t\tmax_queues = VRB1_MAX_VF_MSIX;\n+\t\t} else {\n+\t\t\tif (acc_dev->pf_device)\n+\t\t\t\tmax_queues = VRB2_MAX_PF_MSIX;\n+\t\t\telse\n+\t\t\t\tmax_queues = VRB2_MAX_VF_MSIX;\n+\t\t}\n \n \t\tif (rte_intr_efd_enable(dev->intr_handle, max_queues)) {\n \t\t\trte_bbdev_log(ERR, \"Failed to create fds for %u queues\",\n@@ -1158,6 +1234,10 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)\n \t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n \t};\n \n+\tstatic const struct rte_bbdev_op_cap vrb2_bbdev_capabilities[] = {\n+\t\tRTE_BBDEV_END_OF_CAPABILITIES_LIST()\n+\t};\n+\n \tstatic struct rte_bbdev_queue_conf default_queue_conf;\n \tdefault_queue_conf.socket = dev->data->socket_id;\n \tdefault_queue_conf.queue_size = ACC_MAX_QUEUE_DEPTH;\n@@ -1202,7 +1282,10 @@ vrb_dev_info_get(struct rte_bbdev *dev, struct rte_bbdev_driver_info *dev_info)\n \tdev_info->default_queue_conf = default_queue_conf;\n \tdev_info->cpu_flag_reqs = NULL;\n \tdev_info->min_alignment = 1;\n-\tdev_info->capabilities = vrb1_bbdev_capabilities;\n+\tif (d->device_variant == VRB1_VARIANT)\n+\t\tdev_info->capabilities = vrb1_bbdev_capabilities;\n+\telse\n+\t\tdev_info->capabilities = vrb2_bbdev_capabilities;\n \tdev_info->harq_buffer_size = 0;\n \n \tvrb_check_ir(d);\n@@ -1251,6 +1334,9 @@ static struct rte_pci_id pci_id_vrb_pf_map[] = {\n \t{\n \t\tRTE_PCI_DEVICE(RTE_VRB1_VENDOR_ID, RTE_VRB1_PF_DEVICE_ID)\n \t},\n+\t{\n+\t\tRTE_PCI_DEVICE(RTE_VRB2_VENDOR_ID, RTE_VRB2_PF_DEVICE_ID)\n+\t},\n \t{.device_id = 0},\n };\n \n@@ -1259,6 +1345,9 @@ static struct rte_pci_id pci_id_vrb_vf_map[] = {\n \t{\n \t\tRTE_PCI_DEVICE(RTE_VRB1_VENDOR_ID, RTE_VRB1_VF_DEVICE_ID)\n \t},\n+\t{\n+\t\tRTE_PCI_DEVICE(RTE_VRB2_VENDOR_ID, RTE_VRB2_VF_DEVICE_ID)\n+\t},\n \t{.device_id = 0},\n };\n \n@@ -3444,6 +3533,15 @@ vrb_bbdev_init(struct rte_bbdev *dev, struct rte_pci_driver *drv)\n \t\t\td->reg_addr = &vrb1_pf_reg_addr;\n \t\telse\n \t\t\td->reg_addr = &vrb1_vf_reg_addr;\n+\t} else {\n+\t\td->device_variant = VRB2_VARIANT;\n+\t\td->queue_offset = vrb2_queue_offset;\n+\t\td->num_qgroups = VRB2_NUM_QGRPS;\n+\t\td->num_aqs = VRB2_NUM_AQS;\n+\t\tif (d->pf_device)\n+\t\t\td->reg_addr = &vrb2_pf_reg_addr;\n+\t\telse\n+\t\t\td->reg_addr = &vrb2_vf_reg_addr;\n \t}\n \n \trte_bbdev_log_debug(\"Init device %s [%s] @ vaddr %p paddr %#\"PRIx64\"\",\ndiff --git a/drivers/baseband/acc/vrb2_pf_enum.h b/drivers/baseband/acc/vrb2_pf_enum.h\nnew file mode 100644\nindex 0000000000..28f10dc35b\n--- /dev/null\n+++ b/drivers/baseband/acc/vrb2_pf_enum.h\n@@ -0,0 +1,124 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef VRB2_PF_ENUM_H\n+#define VRB2_PF_ENUM_H\n+\n+/*\n+ * VRB2 Register mapping on PF BAR0\n+ * This is automatically generated from RDL, format may change with new RDL\n+ * Release.\n+ * Variable names are as is\n+ */\n+enum {\n+\tVRB2_PfQmgrEgressQueuesTemplate = 0x0007FC00,\n+\tVRB2_PfQmgrIngressAq = 0x00100000,\n+\tVRB2_PfQmgrSoftReset = 0x00A00034,\n+\tVRB2_PfQmgrAramAllocEn\t = 0x00A000a0,\n+\tVRB2_PfQmgrAramAllocSetupN0 = 0x00A000b0,\n+\tVRB2_PfQmgrAramAllocSetupN1 = 0x00A000b4,\n+\tVRB2_PfQmgrAramAllocSetupN2 = 0x00A000b8,\n+\tVRB2_PfQmgrAramAllocSetupN3 = 0x00A000bc,\n+\tVRB2_PfQmgrDepthLog2Grp = 0x00A00200,\n+\tVRB2_PfQmgrTholdGrp = 0x00A00300,\n+\tVRB2_PfQmgrGrpTmplateReg0Indx = 0x00A00600,\n+\tVRB2_PfQmgrGrpTmplateReg1Indx = 0x00A00700,\n+\tVRB2_PfQmgrGrpTmplateReg2Indx = 0x00A00800,\n+\tVRB2_PfQmgrGrpTmplateReg3Indx = 0x00A00900,\n+\tVRB2_PfQmgrGrpTmplateReg4Indx = 0x00A00A00,\n+\tVRB2_PfQmgrGrpTmplateReg5Indx = 0x00A00B00,\n+\tVRB2_PfQmgrGrpTmplateReg6Indx = 0x00A00C00,\n+\tVRB2_PfQmgrGrpTmplateReg7Indx = 0x00A00D00,\n+\tVRB2_PfQmgrGrpTmplateEnRegIndx = 0x00A00E00,\n+\tVRB2_PfQmgrArbQDepthGrp = 0x00A02F00,\n+\tVRB2_PfQmgrGrpFunction0 = 0x00A02F80,\n+\tVRB2_PfQmgrGrpPriority = 0x00A02FC0,\n+\tVRB2_PfQmgrVfBaseAddr = 0x00A08000,\n+\tVRB2_PfQmgrAqEnableVf = 0x00A10000,\n+\tVRB2_PfQmgrRingSizeVf = 0x00A20010,\n+\tVRB2_PfQmgrGrpDepthLog20Vf = 0x00A20020,\n+\tVRB2_PfQmgrGrpDepthLog21Vf = 0x00A20024,\n+\tVRB2_PfFabricM2iBufferReg = 0x00B30000,\n+\tVRB2_PfFecUl5gIbDebug0Reg = 0x00B401FC,\n+\tVRB2_PfFftConfig0 = 0x00B58004,\n+\tVRB2_PfFftParityMask8 = 0x00B5803C,\n+\tVRB2_PfDmaConfig0Reg = 0x00B80000,\n+\tVRB2_PfDmaConfig1Reg = 0x00B80004,\n+\tVRB2_PfDmaQmgrAddrReg = 0x00B80008,\n+\tVRB2_PfDmaAxcacheReg = 0x00B80010,\n+\tVRB2_PfDmaAxiControl = 0x00B8002C,\n+\tVRB2_PfDmaQmanen = 0x00B80040,\n+\tVRB2_PfDmaQmanenSelect = 0x00B80044,\n+\tVRB2_PfDmaCfgRrespBresp = 0x00B80814,\n+\tVRB2_PfDmaDescriptorSignature = 0x00B80868,\n+\tVRB2_PfDmaErrorDetectionEn = 0x00B80870,\n+\tVRB2_PfDmaFec5GulDescBaseLoRegVf = 0x00B88020,\n+\tVRB2_PfDmaFec5GulDescBaseHiRegVf = 0x00B88024,\n+\tVRB2_PfDmaFec5GulRespPtrLoRegVf = 0x00B88028,\n+\tVRB2_PfDmaFec5GulRespPtrHiRegVf = 0x00B8802C,\n+\tVRB2_PfDmaFec5GdlDescBaseLoRegVf = 0x00B88040,\n+\tVRB2_PfDmaFec5GdlDescBaseHiRegVf = 0x00B88044,\n+\tVRB2_PfDmaFec5GdlRespPtrLoRegVf = 0x00B88048,\n+\tVRB2_PfDmaFec5GdlRespPtrHiRegVf = 0x00B8804C,\n+\tVRB2_PfDmaFec4GulDescBaseLoRegVf = 0x00B88060,\n+\tVRB2_PfDmaFec4GulDescBaseHiRegVf = 0x00B88064,\n+\tVRB2_PfDmaFec4GulRespPtrLoRegVf = 0x00B88068,\n+\tVRB2_PfDmaFec4GulRespPtrHiRegVf = 0x00B8806C,\n+\tVRB2_PfDmaFec4GdlDescBaseLoRegVf = 0x00B88080,\n+\tVRB2_PfDmaFec4GdlDescBaseHiRegVf = 0x00B88084,\n+\tVRB2_PfDmaFec4GdlRespPtrLoRegVf = 0x00B88088,\n+\tVRB2_PfDmaFec4GdlRespPtrHiRegVf = 0x00B8808C,\n+\tVRB2_PfDmaFftDescBaseLoRegVf = 0x00B880A0,\n+\tVRB2_PfDmaFftDescBaseHiRegVf = 0x00B880A4,\n+\tVRB2_PfDmaFftRespPtrLoRegVf = 0x00B880A8,\n+\tVRB2_PfDmaFftRespPtrHiRegVf = 0x00B880AC,\n+\tVRB2_PfDmaMldDescBaseLoRegVf = 0x00B880C0,\n+\tVRB2_PfDmaMldDescBaseHiRegVf = 0x00B880C4,\n+\tVRB2_PfQosmonAEvalOverflow0 = 0x00B90008,\n+\tVRB2_PfPermonACntrlRegVf = 0x00B98000,\n+\tVRB2_PfQosmonBEvalOverflow0 = 0x00BA0008,\n+\tVRB2_PfPermonBCntrlRegVf = 0x00BA8000,\n+\tVRB2_PfPermonCCntrlRegVf = 0x00BB8000,\n+\tVRB2_PfHiInfoRingBaseLoRegPf = 0x00C84014,\n+\tVRB2_PfHiInfoRingBaseHiRegPf = 0x00C84018,\n+\tVRB2_PfHiInfoRingPointerRegPf = 0x00C8401C,\n+\tVRB2_PfHiInfoRingIntWrEnRegPf = 0x00C84020,\n+\tVRB2_PfHiBlockTransmitOnErrorEn = 0x00C84038,\n+\tVRB2_PfHiCfgMsiIntWrEnRegPf = 0x00C84040,\n+\tVRB2_PfHiMsixVectorMapperPf = 0x00C84060,\n+\tVRB2_PfHiPfMode = 0x00C84108,\n+\tVRB2_PfHiClkGateHystReg = 0x00C8410C,\n+\tVRB2_PfHiMsiDropEnableReg = 0x00C84114,\n+\tVRB2_PfHiSectionPowerGatingReq = 0x00C84128,\n+\tVRB2_PfHiSectionPowerGatingAck = 0x00C8412C,\n+};\n+\n+/* TIP PF Interrupt numbers */\n+enum {\n+\tVRB2_PF_INT_QMGR_AQ_OVERFLOW = 0,\n+\tVRB2_PF_INT_DOORBELL_VF_2_PF = 1,\n+\tVRB2_PF_INT_ILLEGAL_FORMAT = 2,\n+\tVRB2_PF_INT_QMGR_DISABLED_ACCESS = 3,\n+\tVRB2_PF_INT_QMGR_AQ_OVERTHRESHOLD = 4,\n+\tVRB2_PF_INT_DMA_DL_DESC_IRQ = 5,\n+\tVRB2_PF_INT_DMA_UL_DESC_IRQ = 6,\n+\tVRB2_PF_INT_DMA_FFT_DESC_IRQ = 7,\n+\tVRB2_PF_INT_DMA_UL5G_DESC_IRQ = 8,\n+\tVRB2_PF_INT_DMA_DL5G_DESC_IRQ = 9,\n+\tVRB2_PF_INT_DMA_MLD_DESC_IRQ = 10,\n+\tVRB2_PF_INT_ARAM_ACCESS_ERR = 11,\n+\tVRB2_PF_INT_ARAM_ECC_1BIT_ERR = 12,\n+\tVRB2_PF_INT_PARITY_ERR = 13,\n+\tVRB2_PF_INT_QMGR_OVERFLOW = 14,\n+\tVRB2_PF_INT_QMGR_ERR = 15,\n+\tVRB2_PF_INT_ATS_ERR = 22,\n+\tVRB2_PF_INT_ARAM_FUUL = 23,\n+\tVRB2_PF_INT_EXTRA_READ = 24,\n+\tVRB2_PF_INT_COMPLETION_TIMEOUT = 25,\n+\tVRB2_PF_INT_CORE_HANG = 26,\n+\tVRB2_PF_INT_DMA_HANG = 28,\n+\tVRB2_PF_INT_DS_HANG = 27,\n+};\n+\n+#endif /* VRB2_PF_ENUM_H */\ndiff --git a/drivers/baseband/acc/vrb2_vf_enum.h b/drivers/baseband/acc/vrb2_vf_enum.h\nnew file mode 100644\nindex 0000000000..9c6e451010\n--- /dev/null\n+++ b/drivers/baseband/acc/vrb2_vf_enum.h\n@@ -0,0 +1,121 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2023 Intel Corporation\n+ */\n+\n+#ifndef VRB2_VF_ENUM_H\n+#define VRB2_VF_ENUM_H\n+\n+/*\n+ * VRB2 Register mapping on VF BAR0\n+ * This is automatically generated from RDL, format may change with new RDL\n+ */\n+enum {\n+\tVRB2_VfHiVfToPfDbellVf = 0x00000000,\n+\tVRB2_VfHiPfToVfDbellVf = 0x00000008,\n+\tVRB2_VfHiInfoRingBaseLoVf = 0x00000010,\n+\tVRB2_VfHiInfoRingBaseHiVf = 0x00000014,\n+\tVRB2_VfHiInfoRingPointerVf = 0x00000018,\n+\tVRB2_VfHiInfoRingIntWrEnVf = 0x00000020,\n+\tVRB2_VfHiInfoRingPf2VfWrEnVf = 0x00000024,\n+\tVRB2_VfHiMsixVectorMapperVf = 0x00000060,\n+\tVRB2_VfHiDeviceStatus = 0x00000068,\n+\tVRB2_VfHiInterruptSrc = 0x00000070,\n+\tVRB2_VfDmaFec5GulDescBaseLoRegVf = 0x00000120,\n+\tVRB2_VfDmaFec5GulDescBaseHiRegVf = 0x00000124,\n+\tVRB2_VfDmaFec5GulRespPtrLoRegVf = 0x00000128,\n+\tVRB2_VfDmaFec5GulRespPtrHiRegVf = 0x0000012C,\n+\tVRB2_VfDmaFec5GdlDescBaseLoRegVf = 0x00000140,\n+\tVRB2_VfDmaFec5GdlDescBaseHiRegVf = 0x00000144,\n+\tVRB2_VfDmaFec5GdlRespPtrLoRegVf = 0x00000148,\n+\tVRB2_VfDmaFec5GdlRespPtrHiRegVf = 0x0000014C,\n+\tVRB2_VfDmaFec4GulDescBaseLoRegVf = 0x00000160,\n+\tVRB2_VfDmaFec4GulDescBaseHiRegVf = 0x00000164,\n+\tVRB2_VfDmaFec4GulRespPtrLoRegVf = 0x00000168,\n+\tVRB2_VfDmaFec4GulRespPtrHiRegVf = 0x0000016C,\n+\tVRB2_VfDmaFec4GdlDescBaseLoRegVf = 0x00000180,\n+\tVRB2_VfDmaFec4GdlDescBaseHiRegVf = 0x00000184,\n+\tVRB2_VfDmaFec4GdlRespPtrLoRegVf = 0x00000188,\n+\tVRB2_VfDmaFec4GdlRespPtrHiRegVf = 0x0000018C,\n+\tVRB2_VfDmaFftDescBaseLoRegVf = 0x000001A0,\n+\tVRB2_VfDmaFftDescBaseHiRegVf = 0x000001A4,\n+\tVRB2_VfDmaFftRespPtrLoRegVf = 0x000001A8,\n+\tVRB2_VfDmaFftRespPtrHiRegVf = 0x000001AC,\n+\tVRB2_VfDmaMldDescBaseLoRegVf = 0x000001C0,\n+\tVRB2_VfDmaMldDescBaseHiRegVf = 0x000001C4,\n+\tVRB2_VfDmaMldRespPtrLoRegVf = 0x000001C8,\n+\tVRB2_VfDmaMldRespPtrHiRegVf = 0x000001CC,\n+\tVRB2_VfPmACntrlRegVf = 0x00000200,\n+\tVRB2_VfPmACountVf = 0x00000208,\n+\tVRB2_VfPmAKCntLoVf = 0x00000210,\n+\tVRB2_VfPmAKCntHiVf = 0x00000214,\n+\tVRB2_VfPmADeltaCntLoVf = 0x00000220,\n+\tVRB2_VfPmADeltaCntHiVf = 0x00000224,\n+\tVRB2_VfPmBCntrlRegVf = 0x00000240,\n+\tVRB2_VfPmBCountVf = 0x00000248,\n+\tVRB2_VfPmBKCntLoVf = 0x00000250,\n+\tVRB2_VfPmBKCntHiVf = 0x00000254,\n+\tVRB2_VfPmBDeltaCntLoVf = 0x00000260,\n+\tVRB2_VfPmBDeltaCntHiVf = 0x00000264,\n+\tVRB2_VfPmCCntrlRegVf = 0x00000280,\n+\tVRB2_VfPmCCountVf = 0x00000288,\n+\tVRB2_VfPmCKCntLoVf = 0x00000290,\n+\tVRB2_VfPmCKCntHiVf = 0x00000294,\n+\tVRB2_VfPmCDeltaCntLoVf = 0x000002A0,\n+\tVRB2_VfPmCDeltaCntHiVf = 0x000002A4,\n+\tVRB2_VfPmDCntrlRegVf = 0x000002C0,\n+\tVRB2_VfPmDCountVf = 0x000002C8,\n+\tVRB2_VfPmDKCntLoVf = 0x000002D0,\n+\tVRB2_VfPmDKCntHiVf = 0x000002D4,\n+\tVRB2_VfPmDDeltaCntLoVf = 0x000002E0,\n+\tVRB2_VfPmDDeltaCntHiVf = 0x000002E4,\n+\tVRB2_VfPmECntrlRegVf = 0x00000300,\n+\tVRB2_VfPmECountVf = 0x00000308,\n+\tVRB2_VfPmEKCntLoVf = 0x00000310,\n+\tVRB2_VfPmEKCntHiVf = 0x00000314,\n+\tVRB2_VfPmEDeltaCntLoVf = 0x00000320,\n+\tVRB2_VfPmEDeltaCntHiVf = 0x00000324,\n+\tVRB2_VfPmFCntrlRegVf = 0x00000340,\n+\tVRB2_VfPmFCountVf = 0x00000348,\n+\tVRB2_VfPmFKCntLoVf = 0x00000350,\n+\tVRB2_VfPmFKCntHiVf = 0x00000354,\n+\tVRB2_VfPmFDeltaCntLoVf = 0x00000360,\n+\tVRB2_VfPmFDeltaCntHiVf = 0x00000364,\n+\tVRB2_VfQmgrAqReset0 = 0x00000600,\n+\tVRB2_VfQmgrAqReset1 = 0x00000604,\n+\tVRB2_VfQmgrAqReset2 = 0x00000608,\n+\tVRB2_VfQmgrAqReset3 = 0x0000060C,\n+\tVRB2_VfQmgrRingSizeVf = 0x00000610,\n+\tVRB2_VfQmgrGrpDepthLog20Vf = 0x00000620,\n+\tVRB2_VfQmgrGrpDepthLog21Vf = 0x00000624,\n+\tVRB2_VfQmgrGrpDepthLog22Vf = 0x00000628,\n+\tVRB2_VfQmgrGrpDepthLog23Vf = 0x0000062C,\n+\tVRB2_VfQmgrGrpFunction0Vf = 0x00000630,\n+\tVRB2_VfQmgrGrpFunction1Vf = 0x00000634,\n+\tVRB2_VfQmgrAramUsageN0 = 0x00000640,\n+\tVRB2_VfQmgrAramUsageN1 = 0x00000644,\n+\tVRB2_VfQmgrAramUsageN2 = 0x00000648,\n+\tVRB2_VfQmgrAramUsageN3 = 0x0000064C,\n+\tVRB2_VfHiMSIXBaseLoRegVf = 0x00001000,\n+\tVRB2_VfHiMSIXBaseHiRegVf = 0x00001004,\n+\tVRB2_VfHiMSIXBaseDataRegVf = 0x00001008,\n+\tVRB2_VfHiMSIXBaseMaskRegVf = 0x0000100C,\n+\tVRB2_VfHiMSIXPBABaseLoRegVf = 0x00003000,\n+\tVRB2_VfQmgrIngressAq = 0x00004000,\n+};\n+\n+/* TIP VF Interrupt numbers */\n+enum {\n+\tVRB2_VF_INT_QMGR_AQ_OVERFLOW = 0,\n+\tVRB2_VF_INT_DOORBELL_PF_2_VF = 1,\n+\tVRB2_VF_INT_ILLEGAL_FORMAT = 2,\n+\tVRB2_VF_INT_QMGR_DISABLED_ACCESS = 3,\n+\tVRB2_VF_INT_QMGR_AQ_OVERTHRESHOLD = 4,\n+\tVRB2_VF_INT_DMA_DL_DESC_IRQ = 5,\n+\tVRB2_VF_INT_DMA_UL_DESC_IRQ = 6,\n+\tVRB2_VF_INT_DMA_FFT_DESC_IRQ = 7,\n+\tVRB2_VF_INT_DMA_UL5G_DESC_IRQ = 8,\n+\tVRB2_VF_INT_DMA_DL5G_DESC_IRQ = 9,\n+\tVRB2_VF_INT_DMA_MLD_DESC_IRQ = 10,\n+};\n+\n+#endif /* VRB2_VF_ENUM_H */\ndiff --git a/drivers/baseband/acc/vrb_pmd.h b/drivers/baseband/acc/vrb_pmd.h\nindex 1cabc0b7f4..0371db9972 100644\n--- a/drivers/baseband/acc/vrb_pmd.h\n+++ b/drivers/baseband/acc/vrb_pmd.h\n@@ -8,6 +8,8 @@\n #include \"acc_common.h\"\n #include \"vrb1_pf_enum.h\"\n #include \"vrb1_vf_enum.h\"\n+#include \"vrb2_pf_enum.h\"\n+#include \"vrb2_vf_enum.h\"\n #include \"vrb_cfg.h\"\n \n /* Helper macro for logging */\n@@ -31,12 +33,13 @@\n #define RTE_VRB1_VENDOR_ID (0x8086)\n #define RTE_VRB1_PF_DEVICE_ID (0x57C0)\n #define RTE_VRB1_VF_DEVICE_ID (0x57C1)\n-\n-#define VRB1_VARIANT 2\n+#define RTE_VRB2_VENDOR_ID (0x8086)\n+#define RTE_VRB2_PF_DEVICE_ID (0x57C2)\n+#define RTE_VRB2_VF_DEVICE_ID (0x57C3)\n \n #define VRB_NUM_ACCS 6\n #define VRB_MAX_QGRPS 32\n-#define VRB_MAX_AQS 32\n+#define VRB_MAX_AQS 64\n \n #define ACC_STATUS_WAIT 10\n #define ACC_STATUS_TO 100\n@@ -46,8 +49,6 @@\n #define VRB1_NUM_VFS 16\n #define VRB1_NUM_QGRPS 16\n #define VRB1_NUM_AQS 16\n-#define VRB1_GRP_ID_SHIFT 10 /* Queue Index Hierarchy */\n-#define VRB1_VF_ID_SHIFT 4 /* Queue Index Hierarchy */\n #define VRB1_WORDS_IN_ARAM_SIZE (256 * 1024 / 4)\n \n /* VRB1 Mapping of signals for the available engines */\n@@ -61,7 +62,6 @@\n #define VRB1_SIG_DL_4G_LAST 23\n #define VRB1_SIG_FFT 24\n #define VRB1_SIG_FFT_LAST 24\n-\n #define VRB1_NUM_ACCS 5\n \n /* VRB1 Configuration */\n@@ -90,6 +90,67 @@\n #define VRB1_MAX_PF_MSIX (256+32)\n #define VRB1_MAX_VF_MSIX (256+7)\n \n+/* VRB2 specific flags */\n+\n+#define VRB2_NUM_VFS 64\n+#define VRB2_NUM_QGRPS 32\n+#define VRB2_NUM_AQS 64\n+#define VRB2_WORDS_IN_ARAM_SIZE (512 * 1024 / 4)\n+#define VRB2_NUM_ACCS 6\n+#define VRB2_AQ_REG_NUM 4\n+\n+/* VRB2 Mapping of signals for the available engines */\n+#define VRB2_SIG_UL_5G 0\n+#define VRB2_SIG_UL_5G_LAST 5\n+#define VRB2_SIG_DL_5G 9\n+#define VRB2_SIG_DL_5G_LAST 11\n+#define VRB2_SIG_UL_4G 12\n+#define VRB2_SIG_UL_4G_LAST 16\n+#define VRB2_SIG_DL_4G 21\n+#define VRB2_SIG_DL_4G_LAST 23\n+#define VRB2_SIG_FFT 24\n+#define VRB2_SIG_FFT_LAST 26\n+#define VRB2_SIG_MLD 30\n+#define VRB2_SIG_MLD_LAST 31\n+#define VRB2_FFT_NUM 3\n+\n+#define VRB2_FCW_MLDTS_BLEN 32\n+#define VRB2_MLD_MIN_LAYER 2\n+#define VRB2_MLD_MAX_LAYER 4\n+#define VRB2_MLD_MAX_RREP 5\n+#define VRB2_MLD_LAY_SIZE 3\n+#define VRB2_MLD_RREP_SIZE 6\n+#define VRB2_MLD_M2DLEN 3\n+\n+#define VRB2_MAX_PF_MSIX (256+32)\n+#define VRB2_MAX_VF_MSIX (64+7)\n+#define VRB2_REG_IRQ_EN_ALL 0xFFFFFFFF /* Enable all interrupts */\n+#define VRB2_FABRIC_MODE 0x8000103\n+#define VRB2_CFG_DMA_ERROR 0x7DF\n+#define VRB2_CFG_AXI_CACHE 0x11\n+#define VRB2_CFG_QMGR_HI_P 0x0F0F\n+#define VRB2_RESET_HARD 0x1FF\n+#define VRB2_ENGINES_MAX 9\n+#define VRB2_GPEX_AXIMAP_NUM 17\n+#define VRB2_CLOCK_GATING_EN 0x30000\n+#define VRB2_FFT_CFG_0 0x2001\n+#define VRB2_FFT_ECC 0x60\n+#define VRB2_FFT_RAM_EN 0x80008000\n+#define VRB2_FFT_RAM_DIS 0x0\n+#define VRB2_FFT_RAM_SIZE 512\n+#define VRB2_CLK_EN 0x00010A01\n+#define VRB2_CLK_DIS 0x01F10A01\n+#define VRB2_PG_MASK_0 0x1F\n+#define VRB2_PG_MASK_1 0xF\n+#define VRB2_PG_MASK_2 0x1\n+#define VRB2_PG_MASK_3 0x0\n+#define VRB2_PG_MASK_FFT 1\n+#define VRB2_PG_MASK_4GUL 4\n+#define VRB2_PG_MASK_5GUL 8\n+#define VRB2_PF_PM_REG_OFFSET 0x10000\n+#define VRB2_VF_PM_REG_OFFSET 0x40\n+#define VRB2_PM_START 0x2\n+\n struct acc_registry_addr {\n \tunsigned int dma_ring_dl5g_hi;\n \tunsigned int dma_ring_dl5g_lo;\n@@ -218,4 +279,92 @@ static const struct acc_registry_addr vrb1_vf_reg_addr = {\n \t.pf2vf_doorbell = VRB1_VfHiPfToVfDbellVf,\n };\n \n+\n+/* Structure holding registry addresses for PF */\n+static const struct acc_registry_addr vrb2_pf_reg_addr = {\n+\t.dma_ring_dl5g_hi = VRB2_PfDmaFec5GdlDescBaseHiRegVf,\n+\t.dma_ring_dl5g_lo = VRB2_PfDmaFec5GdlDescBaseLoRegVf,\n+\t.dma_ring_ul5g_hi = VRB2_PfDmaFec5GulDescBaseHiRegVf,\n+\t.dma_ring_ul5g_lo = VRB2_PfDmaFec5GulDescBaseLoRegVf,\n+\t.dma_ring_dl4g_hi = VRB2_PfDmaFec4GdlDescBaseHiRegVf,\n+\t.dma_ring_dl4g_lo = VRB2_PfDmaFec4GdlDescBaseLoRegVf,\n+\t.dma_ring_ul4g_hi = VRB2_PfDmaFec4GulDescBaseHiRegVf,\n+\t.dma_ring_ul4g_lo = VRB2_PfDmaFec4GulDescBaseLoRegVf,\n+\t.dma_ring_fft_hi = VRB2_PfDmaFftDescBaseHiRegVf,\n+\t.dma_ring_fft_lo = VRB2_PfDmaFftDescBaseLoRegVf,\n+\t.dma_ring_mld_hi = VRB2_PfDmaMldDescBaseHiRegVf,\n+\t.dma_ring_mld_lo = VRB2_PfDmaMldDescBaseLoRegVf,\n+\t.ring_size = VRB2_PfQmgrRingSizeVf,\n+\t.info_ring_hi = VRB2_PfHiInfoRingBaseHiRegPf,\n+\t.info_ring_lo = VRB2_PfHiInfoRingBaseLoRegPf,\n+\t.info_ring_en = VRB2_PfHiInfoRingIntWrEnRegPf,\n+\t.info_ring_ptr = VRB2_PfHiInfoRingPointerRegPf,\n+\t.tail_ptrs_dl5g_hi = VRB2_PfDmaFec5GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl5g_lo = VRB2_PfDmaFec5GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul5g_hi = VRB2_PfDmaFec5GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul5g_lo = VRB2_PfDmaFec5GulRespPtrLoRegVf,\n+\t.tail_ptrs_dl4g_hi = VRB2_PfDmaFec4GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl4g_lo = VRB2_PfDmaFec4GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul4g_hi = VRB2_PfDmaFec4GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul4g_lo = VRB2_PfDmaFec4GulRespPtrLoRegVf,\n+\t.tail_ptrs_fft_hi = VRB2_PfDmaFftRespPtrHiRegVf,\n+\t.tail_ptrs_fft_lo = VRB2_PfDmaFftRespPtrLoRegVf,\n+\t.tail_ptrs_mld_hi = VRB2_PfDmaFftRespPtrHiRegVf,\n+\t.tail_ptrs_mld_lo = VRB2_PfDmaFftRespPtrLoRegVf,\n+\t.depth_log0_offset = VRB2_PfQmgrGrpDepthLog20Vf,\n+\t.depth_log1_offset = VRB2_PfQmgrGrpDepthLog21Vf,\n+\t.qman_group_func = VRB2_PfQmgrGrpFunction0,\n+\t.hi_mode = VRB2_PfHiMsixVectorMapperPf,\n+\t.pf_mode = VRB2_PfHiPfMode,\n+\t.pmon_ctrl_a = VRB2_PfPermonACntrlRegVf,\n+\t.pmon_ctrl_b = VRB2_PfPermonBCntrlRegVf,\n+\t.pmon_ctrl_c = VRB2_PfPermonCCntrlRegVf,\n+\t.vf2pf_doorbell = 0,\n+\t.pf2vf_doorbell = 0,\n+};\n+\n+/* Structure holding registry addresses for VF */\n+static const struct acc_registry_addr vrb2_vf_reg_addr = {\n+\t.dma_ring_dl5g_hi = VRB2_VfDmaFec5GdlDescBaseHiRegVf,\n+\t.dma_ring_dl5g_lo = VRB2_VfDmaFec5GdlDescBaseLoRegVf,\n+\t.dma_ring_ul5g_hi = VRB2_VfDmaFec5GulDescBaseHiRegVf,\n+\t.dma_ring_ul5g_lo = VRB2_VfDmaFec5GulDescBaseLoRegVf,\n+\t.dma_ring_dl4g_hi = VRB2_VfDmaFec4GdlDescBaseHiRegVf,\n+\t.dma_ring_dl4g_lo = VRB2_VfDmaFec4GdlDescBaseLoRegVf,\n+\t.dma_ring_ul4g_hi = VRB2_VfDmaFec4GulDescBaseHiRegVf,\n+\t.dma_ring_ul4g_lo = VRB2_VfDmaFec4GulDescBaseLoRegVf,\n+\t.dma_ring_fft_hi = VRB2_VfDmaFftDescBaseHiRegVf,\n+\t.dma_ring_fft_lo = VRB2_VfDmaFftDescBaseLoRegVf,\n+\t.dma_ring_mld_hi = VRB2_VfDmaMldDescBaseHiRegVf,\n+\t.dma_ring_mld_lo = VRB2_VfDmaMldDescBaseLoRegVf,\n+\t.ring_size = VRB2_VfQmgrRingSizeVf,\n+\t.info_ring_hi = VRB2_VfHiInfoRingBaseHiVf,\n+\t.info_ring_lo = VRB2_VfHiInfoRingBaseLoVf,\n+\t.info_ring_en = VRB2_VfHiInfoRingIntWrEnVf,\n+\t.info_ring_ptr = VRB2_VfHiInfoRingPointerVf,\n+\t.tail_ptrs_dl5g_hi = VRB2_VfDmaFec5GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl5g_lo = VRB2_VfDmaFec5GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul5g_hi = VRB2_VfDmaFec5GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul5g_lo = VRB2_VfDmaFec5GulRespPtrLoRegVf,\n+\t.tail_ptrs_dl4g_hi = VRB2_VfDmaFec4GdlRespPtrHiRegVf,\n+\t.tail_ptrs_dl4g_lo = VRB2_VfDmaFec4GdlRespPtrLoRegVf,\n+\t.tail_ptrs_ul4g_hi = VRB2_VfDmaFec4GulRespPtrHiRegVf,\n+\t.tail_ptrs_ul4g_lo = VRB2_VfDmaFec4GulRespPtrLoRegVf,\n+\t.tail_ptrs_fft_hi = VRB2_VfDmaFftRespPtrHiRegVf,\n+\t.tail_ptrs_fft_lo = VRB2_VfDmaFftRespPtrLoRegVf,\n+\t.tail_ptrs_mld_hi = VRB2_VfDmaMldRespPtrHiRegVf,\n+\t.tail_ptrs_mld_lo = VRB2_VfDmaMldRespPtrLoRegVf,\n+\t.depth_log0_offset = VRB2_VfQmgrGrpDepthLog20Vf,\n+\t.depth_log1_offset = VRB2_VfQmgrGrpDepthLog21Vf,\n+\t.qman_group_func = VRB2_VfQmgrGrpFunction0Vf,\n+\t.hi_mode = VRB2_VfHiMsixVectorMapperVf,\n+\t.pf_mode = 0,\n+\t.pmon_ctrl_a = VRB2_VfPmACntrlRegVf,\n+\t.pmon_ctrl_b = VRB2_VfPmBCntrlRegVf,\n+\t.pmon_ctrl_c = VRB2_VfPmCCntrlRegVf,\n+\t.vf2pf_doorbell = VRB2_VfHiVfToPfDbellVf,\n+\t.pf2vf_doorbell = VRB2_VfHiPfToVfDbellVf,\n+};\n+\n+\n #endif /* _VRB_PMD_H_ */\n", "prefixes": [ "v5", "07/12" ] }