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GET /api/patches/132703/?format=api
{ "id": 132703, "url": "http://patchwork.dpdk.org/api/patches/132703/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231017054545.1692509-14-chaoyong.he@corigine.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231017054545.1692509-14-chaoyong.he@corigine.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231017054545.1692509-14-chaoyong.he@corigine.com", "date": "2023-10-17T05:45:33", "name": "[13/25] drivers: add the common ctrl module", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "f03123b2b1fe2ee8c74bc14c2c0c75c7d4dbf31a", "submitter": { "id": 2554, "url": "http://patchwork.dpdk.org/api/people/2554/?format=api", "name": "Chaoyong He", "email": "chaoyong.he@corigine.com" }, "delegate": { "id": 319, "url": "http://patchwork.dpdk.org/api/users/319/?format=api", "username": "fyigit", "first_name": "Ferruh", "last_name": "Yigit", "email": "ferruh.yigit@amd.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231017054545.1692509-14-chaoyong.he@corigine.com/mbox/", "series": [ { "id": 29865, "url": "http://patchwork.dpdk.org/api/series/29865/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=29865", "date": "2023-10-17T05:45:20", "name": "add the NFP vDPA PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/29865/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/132703/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/132703/checks/", "tags": {}, "related": [], "headers": { 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"Authentication-Results": "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=corigine.com;", "From": "Chaoyong He <chaoyong.he@corigine.com>", "To": "dev@dpdk.org", "Cc": "oss-drivers@corigine.com, Chaoyong He <chaoyong.he@corigine.com>,\n Long Wu <long.wu@corigine.com>, Peng Zhang <peng.zhang@corigine.com>", "Subject": "[PATCH 13/25] drivers: add the common ctrl module", "Date": "Tue, 17 Oct 2023 13:45:33 +0800", "Message-Id": "<20231017054545.1692509-14-chaoyong.he@corigine.com>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20231017054545.1692509-1-chaoyong.he@corigine.com>", "References": "<20231017054545.1692509-1-chaoyong.he@corigine.com>", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "PH7PR17CA0069.namprd17.prod.outlook.com\n (2603:10b6:510:325::29) To PH0PR13MB5568.namprd13.prod.outlook.com\n (2603:10b6:510:12b::16)", "MIME-Version": "1.0", "X-MS-PublicTrafficType": "Email", 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"X-OriginatorOrg": "corigine.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8307c350-a973-483e-2fe3-08dbced471b9", "X-MS-Exchange-CrossTenant-AuthSource": "PH0PR13MB5568.namprd13.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "17 Oct 2023 05:46:47.2954 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "fe128f2c-073b-4c20-818e-7246a585940c", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n +TMmgfzToXVmn+B3WvKSnhL+q8M2+GFrpSq4F1ZPID6CXa1ngMWNUnW90tXozK2nK6zLOqWC1yHoDR1N+sl4ZFLNAroL/0dW2vMs+VtmGbI=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW5PR13MB5904", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add the common ctrl module.\n\nSigned-off-by: Chaoyong He <chaoyong.he@corigine.com>\nReviewed-by: Long Wu <long.wu@corigine.com>\nReviewed-by: Peng Zhang <peng.zhang@corigine.com>\n---\n drivers/common/nfp/nfp_common_ctrl.h | 374 +++++++++++++++++++++++++++\n drivers/net/nfp/nfp_net_ctrl.h | 365 +-------------------------\n 2 files changed, 375 insertions(+), 364 deletions(-)\n create mode 100644 drivers/common/nfp/nfp_common_ctrl.h", "diff": "diff --git a/drivers/common/nfp/nfp_common_ctrl.h b/drivers/common/nfp/nfp_common_ctrl.h\nnew file mode 100644\nindex 0000000000..3c8cd916cf\n--- /dev/null\n+++ b/drivers/common/nfp/nfp_common_ctrl.h\n@@ -0,0 +1,374 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2023 Corigine, Inc.\n+ * All rights reserved.\n+ */\n+\n+#ifndef __NFP_COMMON_CTRL_H__\n+#define __NFP_COMMON_CTRL_H__\n+\n+/*\n+ * Configuration BAR size.\n+ *\n+ * On the NFP6000, due to THB-350, the configuration BAR is 32K in size.\n+ */\n+#define NFP_NET_CFG_BAR_SZ (32 * 1024)\n+\n+/* Offset in Freelist buffer where packet starts on RX */\n+#define NFP_NET_RX_OFFSET 32\n+\n+/* Working with metadata api (NFD version > 3.0) */\n+#define NFP_NET_META_FIELD_SIZE 4\n+#define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1)\n+#define NFP_NET_META_HEADER_SIZE 4\n+#define NFP_NET_META_NFDK_LENGTH 8\n+\n+/* Working with metadata vlan api (NFD version >= 2.0) */\n+#define NFP_NET_META_VLAN_INFO 16\n+#define NFP_NET_META_VLAN_OFFLOAD 31\n+#define NFP_NET_META_VLAN_TPID 3\n+#define NFP_NET_META_VLAN_MASK ((1 << NFP_NET_META_VLAN_INFO) - 1)\n+#define NFP_NET_META_VLAN_TPID_MASK ((1 << NFP_NET_META_VLAN_TPID) - 1)\n+#define NFP_NET_META_TPID(d) (((d) >> NFP_NET_META_VLAN_INFO) & \\\n+\t\t\t\t\t\tNFP_NET_META_VLAN_TPID_MASK)\n+\n+/* Prepend field types */\n+#define NFP_NET_META_HASH 1 /* Next field carries hash type */\n+#define NFP_NET_META_VLAN 4\n+#define NFP_NET_META_PORTID 5\n+#define NFP_NET_META_IPSEC 9\n+\n+#define NFP_META_PORT_ID_CTRL ~0U\n+\n+/* Hash type prepended when a RSS hash was computed */\n+#define NFP_NET_RSS_NONE 0\n+#define NFP_NET_RSS_IPV4 1\n+#define NFP_NET_RSS_IPV6 2\n+#define NFP_NET_RSS_IPV6_EX 3\n+#define NFP_NET_RSS_IPV4_TCP 4\n+#define NFP_NET_RSS_IPV6_TCP 5\n+#define NFP_NET_RSS_IPV6_EX_TCP 6\n+#define NFP_NET_RSS_IPV4_UDP 7\n+#define NFP_NET_RSS_IPV6_UDP 8\n+#define NFP_NET_RSS_IPV6_EX_UDP 9\n+#define NFP_NET_RSS_IPV4_SCTP 10\n+#define NFP_NET_RSS_IPV6_SCTP 11\n+\n+/*\n+ * @NFP_NET_TXR_MAX: Maximum number of TX rings\n+ * @NFP_NET_TXR_MASK: Mask for TX rings\n+ * @NFP_NET_RXR_MAX: Maximum number of RX rings\n+ * @NFP_NET_RXR_MASK: Mask for RX rings\n+ */\n+#define NFP_NET_TXR_MAX 64\n+#define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1)\n+#define NFP_NET_RXR_MAX 64\n+#define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1)\n+\n+/*\n+ * Read/Write config words (0x0000 - 0x002c)\n+ * @NFP_NET_CFG_CTRL: Global control\n+ * @NFP_NET_CFG_UPDATE: Indicate which fields are updated\n+ * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings\n+ * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings\n+ * @NFP_NET_CFG_MTU: Set MTU size\n+ * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)\n+ * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions\n+ * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes\n+ * @NFP_NET_CFG_MACADDR: MAC address\n+ *\n+ * TODO:\n+ * - define Error details in UPDATE\n+ */\n+#define NFP_NET_CFG_CTRL 0x0000\n+#define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */\n+#define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */\n+#define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */\n+#define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */\n+#define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */\n+#define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */\n+#define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */\n+#define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */\n+#define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */\n+#define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */\n+#define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */\n+#define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable QINQ strip */\n+#define NFP_NET_CFG_CTRL_RXVLAN_V2 (0x1 << 15) /* Enable VLAN strip with metadata */\n+#define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */\n+#define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */\n+#define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */\n+#define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */\n+#define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */\n+#define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring */\n+#define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */\n+#define NFP_NET_CFG_CTRL_TXVLAN_V2 (0x1 << 23) /* Enable VLAN insert with metadata */\n+#define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */\n+#define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */\n+#define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */\n+#define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */\n+#define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */\n+#define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */\n+#define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31) /* Live MAC addr change */\n+#define NFP_NET_CFG_UPDATE 0x0004\n+#define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */\n+#define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */\n+#define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */\n+#define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */\n+#define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */\n+#define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */\n+#define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */\n+#define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */\n+#define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */\n+#define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */\n+#define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */\n+#define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */\n+#define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */\n+#define NFP_NET_CFG_TXRS_ENABLE 0x0008\n+#define NFP_NET_CFG_RXRS_ENABLE 0x0010\n+#define NFP_NET_CFG_MTU 0x0018\n+#define NFP_NET_CFG_FLBUFSZ 0x001c\n+#define NFP_NET_CFG_EXN 0x001f\n+#define NFP_NET_CFG_LSC 0x0020\n+#define NFP_NET_CFG_MACADDR 0x0024\n+\n+#define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2)\n+#define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | NFP_NET_CFG_CTRL_RSS2)\n+\n+#define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \\\n+\t\t\t\t\tNFP_NET_CFG_CTRL_CSUM_COMPLETE)\n+\n+/* Version number helper defines */\n+struct nfp_net_fw_ver {\n+\tuint8_t minor;\n+\tuint8_t major;\n+\tuint8_t class;\n+\t/**\n+\t * This byte can be extended for more use.\n+\t * BIT0: NFD dp type, refer NFP_NET_CFG_VERSION_DP_NFDx\n+\t * BIT[7:1]: reserved\n+\t */\n+\tuint8_t extend;\n+};\n+\n+/*\n+ * Read-only words (0x0030 - 0x0050):\n+ * @NFP_NET_CFG_VERSION: Firmware version number\n+ * @NFP_NET_CFG_STS: Status\n+ * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL)\n+ * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings\n+ * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings\n+ * @NFP_NET_MAX_MTU: Maximum support MTU\n+ * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only)\n+ * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only)\n+ *\n+ * TODO:\n+ * - define more STS bits\n+ */\n+#define NFP_NET_CFG_VERSION 0x0030\n+#define NFP_NET_CFG_VERSION_DP_NFD3 0\n+#define NFP_NET_CFG_VERSION_DP_NFDK 1\n+#define NFP_NET_CFG_STS 0x0034\n+#define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */\n+/* Link rate */\n+#define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1\n+#define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF\n+#define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0\n+#define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1\n+#define NFP_NET_CFG_STS_LINK_RATE_1G 2\n+#define NFP_NET_CFG_STS_LINK_RATE_10G 3\n+#define NFP_NET_CFG_STS_LINK_RATE_25G 4\n+#define NFP_NET_CFG_STS_LINK_RATE_40G 5\n+#define NFP_NET_CFG_STS_LINK_RATE_50G 6\n+#define NFP_NET_CFG_STS_LINK_RATE_100G 7\n+\n+/*\n+ * NSP Link rate is a 16-bit word. It is no longer determined by\n+ * firmware, instead it is read from the nfp_eth_table of the\n+ * associated pf_dev and written to the NFP_NET_CFG_STS_NSP_LINK_RATE\n+ * address by the PMD each time the port is reconfigured.\n+ */\n+#define NFP_NET_CFG_STS_NSP_LINK_RATE 0x0036\n+\n+#define NFP_NET_CFG_CAP 0x0038\n+#define NFP_NET_CFG_MAX_TXRINGS 0x003c\n+#define NFP_NET_CFG_MAX_RXRINGS 0x0040\n+#define NFP_NET_CFG_MAX_MTU 0x0044\n+/* Next two words are being used by VFs for solving THB350 issue */\n+#define NFP_NET_CFG_START_TXQ 0x0048\n+#define NFP_NET_CFG_START_RXQ 0x004c\n+\n+/*\n+ * NFP-3200 workaround (0x0050 - 0x0058)\n+ * @NFP_NET_CFG_SPARE_ADDR: DMA address for ME code to use (e.g. YDS-155 fix)\n+ */\n+#define NFP_NET_CFG_SPARE_ADDR 0x0050\n+/*\n+ * NFP6000/NFP4000 - Prepend configuration\n+ */\n+#define NFP_NET_CFG_RX_OFFSET 0x0050\n+#define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */\n+\n+/* Start anchor of the TLV area */\n+#define NFP_NET_CFG_TLV_BASE 0x0058\n+\n+/**\n+ * Reuse spare address to contain the offset from the start of\n+ * the host buffer where the first byte of the received frame\n+ * will land. Any metadata will come prior to that offset. If the\n+ * value in this field is 0, it means that the metadata will\n+ * always land starting at the first byte of the host buffer and\n+ * packet data will immediately follow the metadata. As always,\n+ * the RX descriptor indicates the presence or absence of metadata\n+ * along with the length thereof.\n+ */\n+#define NFP_NET_CFG_RX_OFFSET_ADDR 0x0050\n+\n+#define NFP_NET_CFG_VXLAN_PORT 0x0060\n+#define NFP_NET_CFG_VXLAN_SZ 0x0008\n+\n+/* Offload definitions */\n+#define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t))\n+\n+/*\n+ * 3 words reserved for extended ctrl words (0x0098 - 0x00a4)\n+ * 3 words reserved for extended cap words (0x00a4 - 0x00b0)\n+ * Currently only one word is used, can be extended in future.\n+ */\n+#define NFP_NET_CFG_CTRL_WORD1 0x0098\n+#define NFP_NET_CFG_CTRL_PKT_TYPE (0x1 << 0)\n+#define NFP_NET_CFG_CTRL_IPSEC (0x1 << 1) /**< IPsec offload */\n+#define NFP_NET_CFG_CTRL_IPSEC_SM_LOOKUP (0x1 << 3) /**< SA short match lookup */\n+#define NFP_NET_CFG_CTRL_IPSEC_LM_LOOKUP (0x1 << 4) /**< SA long match lookup */\n+\n+#define NFP_NET_CFG_CAP_WORD1 0x00a4\n+\n+/* 16B reserved for future use (0x00b0 - 0x00c0). */\n+#define NFP_NET_CFG_RESERVED 0x00b0\n+#define NFP_NET_CFG_RESERVED_SZ 0x0010\n+\n+/*\n+ * RSS configuration (0x0100 - 0x01ac):\n+ * Used only when NFP_NET_CFG_CTRL_RSS_ANY is enabled\n+ * @NFP_NET_CFG_RSS_CFG: RSS configuration word\n+ * @NFP_NET_CFG_RSS_KEY: RSS \"secret\" key\n+ * @NFP_NET_CFG_RSS_ITBL: RSS indirection table\n+ */\n+#define NFP_NET_CFG_RSS_BASE 0x0100\n+#define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE\n+#define NFP_NET_CFG_RSS_MASK (0x7f)\n+#define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f)\n+#define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */\n+#define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */\n+#define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */\n+#define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */\n+#define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */\n+#define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */\n+#define NFP_NET_CFG_RSS_IPV4_SCTP (1 << 14) /* RSS for IPv4/SCTP */\n+#define NFP_NET_CFG_RSS_IPV6_SCTP (1 << 15) /* RSS for IPv6/SCTP */\n+#define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */\n+#define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4)\n+#define NFP_NET_CFG_RSS_KEY_SZ 0x28\n+#define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \\\n+\t\t\t\t\t NFP_NET_CFG_RSS_KEY_SZ)\n+#define NFP_NET_CFG_RSS_ITBL_SZ 0x80\n+\n+/*\n+ * TX ring configuration (0x200 - 0x800)\n+ * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration\n+ * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries)\n+ * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)\n+ * @NFP_NET_CFG_TXR_SZ: Per TX ring size (1B entries)\n+ * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries)\n+ * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)\n+ * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)\n+ */\n+#define NFP_NET_CFG_TXR_BASE 0x0200\n+#define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))\n+#define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \\\n+\t\t\t\t\t ((_x) * 0x8))\n+#define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))\n+#define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))\n+#define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))\n+#define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \\\n+\t\t\t\t\t ((_x) * 0x4))\n+\n+/*\n+ * RX ring configuration (0x0800 - 0x0c00)\n+ * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration\n+ * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries)\n+ * @NFP_NET_CFG_RXR_SZ: Per TX ring size (1B entries)\n+ * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries)\n+ * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries)\n+ * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)\n+ */\n+#define NFP_NET_CFG_RXR_BASE 0x0800\n+#define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))\n+#define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))\n+#define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))\n+#define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))\n+#define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \\\n+\t\t\t\t\t ((_x) * 0x4))\n+\n+/*\n+ * Interrupt Control/Cause registers (0x0c00 - 0x0d00)\n+ * These registers are only used when MSI-X auto-masking is not\n+ * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index\n+ * by MSI-X entry and are 1B in size. If an entry is zero, the\n+ * corresponding entry is enabled. If the FW generates an interrupt,\n+ * it writes a cause into the corresponding field. This also masks\n+ * the MSI-X entry and the host driver must clear the register to\n+ * re-enable the interrupt.\n+ */\n+#define NFP_NET_CFG_ICR_BASE 0x0c00\n+#define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x))\n+#define NFP_NET_CFG_ICR_UNMASKED 0x0\n+#define NFP_NET_CFG_ICR_RXTX 0x1\n+#define NFP_NET_CFG_ICR_LSC 0x2\n+\n+/*\n+ * General device stats (0x0d00 - 0x0d90)\n+ * All counters are 64bit.\n+ */\n+#define NFP_NET_CFG_STATS_BASE 0x0d00\n+#define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00)\n+#define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)\n+#define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)\n+#define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18)\n+#define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20)\n+#define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28)\n+#define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)\n+#define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38)\n+#define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40)\n+\n+#define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48)\n+#define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)\n+#define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)\n+#define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60)\n+#define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68)\n+#define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70)\n+#define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)\n+#define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80)\n+#define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88)\n+\n+#define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90)\n+#define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98)\n+#define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0)\n+#define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8)\n+#define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0)\n+#define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8)\n+#define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0)\n+#define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8)\n+\n+/*\n+ * Per ring stats (0x1000 - 0x1800)\n+ * Options, 64bit per entry\n+ * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)\n+ * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)\n+ */\n+#define NFP_NET_CFG_TXR_STATS_BASE 0x1000\n+#define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \\\n+\t\t\t\t\t ((_x) * 0x10))\n+#define NFP_NET_CFG_RXR_STATS_BASE 0x1400\n+#define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \\\n+\t\t\t\t\t ((_x) * 0x10))\n+\n+#endif /* __NFP_COMMON_CTRL_H__ */\ndiff --git a/drivers/net/nfp/nfp_net_ctrl.h b/drivers/net/nfp/nfp_net_ctrl.h\nindex 3772b28a66..ee1b784bb1 100644\n--- a/drivers/net/nfp/nfp_net_ctrl.h\n+++ b/drivers/net/nfp/nfp_net_ctrl.h\n@@ -10,370 +10,7 @@\n \n #include <ethdev_driver.h>\n \n-/*\n- * Configuration BAR size.\n- *\n- * On the NFP6000, due to THB-350, the configuration BAR is 32K in size.\n- */\n-#define NFP_NET_CFG_BAR_SZ (32 * 1024)\n-\n-/* Offset in Freelist buffer where packet starts on RX */\n-#define NFP_NET_RX_OFFSET 32\n-\n-/* Working with metadata api (NFD version > 3.0) */\n-#define NFP_NET_META_FIELD_SIZE 4\n-#define NFP_NET_META_FIELD_MASK ((1 << NFP_NET_META_FIELD_SIZE) - 1)\n-#define NFP_NET_META_HEADER_SIZE 4\n-#define NFP_NET_META_NFDK_LENGTH 8\n-\n-/* Working with metadata vlan api (NFD version >= 2.0) */\n-#define NFP_NET_META_VLAN_INFO 16\n-#define NFP_NET_META_VLAN_OFFLOAD 31\n-#define NFP_NET_META_VLAN_TPID 3\n-#define NFP_NET_META_VLAN_MASK ((1 << NFP_NET_META_VLAN_INFO) - 1)\n-#define NFP_NET_META_VLAN_TPID_MASK ((1 << NFP_NET_META_VLAN_TPID) - 1)\n-#define NFP_NET_META_TPID(d) (((d) >> NFP_NET_META_VLAN_INFO) & \\\n-\t\t\t\t\t\tNFP_NET_META_VLAN_TPID_MASK)\n-\n-/* Prepend field types */\n-#define NFP_NET_META_HASH 1 /* Next field carries hash type */\n-#define NFP_NET_META_VLAN 4\n-#define NFP_NET_META_PORTID 5\n-#define NFP_NET_META_IPSEC 9\n-\n-#define NFP_META_PORT_ID_CTRL ~0U\n-\n-/* Hash type prepended when a RSS hash was computed */\n-#define NFP_NET_RSS_NONE 0\n-#define NFP_NET_RSS_IPV4 1\n-#define NFP_NET_RSS_IPV6 2\n-#define NFP_NET_RSS_IPV6_EX 3\n-#define NFP_NET_RSS_IPV4_TCP 4\n-#define NFP_NET_RSS_IPV6_TCP 5\n-#define NFP_NET_RSS_IPV6_EX_TCP 6\n-#define NFP_NET_RSS_IPV4_UDP 7\n-#define NFP_NET_RSS_IPV6_UDP 8\n-#define NFP_NET_RSS_IPV6_EX_UDP 9\n-#define NFP_NET_RSS_IPV4_SCTP 10\n-#define NFP_NET_RSS_IPV6_SCTP 11\n-\n-/*\n- * @NFP_NET_TXR_MAX: Maximum number of TX rings\n- * @NFP_NET_TXR_MASK: Mask for TX rings\n- * @NFP_NET_RXR_MAX: Maximum number of RX rings\n- * @NFP_NET_RXR_MASK: Mask for RX rings\n- */\n-#define NFP_NET_TXR_MAX 64\n-#define NFP_NET_TXR_MASK (NFP_NET_TXR_MAX - 1)\n-#define NFP_NET_RXR_MAX 64\n-#define NFP_NET_RXR_MASK (NFP_NET_RXR_MAX - 1)\n-\n-/*\n- * Read/Write config words (0x0000 - 0x002c)\n- * @NFP_NET_CFG_CTRL: Global control\n- * @NFP_NET_CFG_UPDATE: Indicate which fields are updated\n- * @NFP_NET_CFG_TXRS_ENABLE: Bitmask of enabled TX rings\n- * @NFP_NET_CFG_RXRS_ENABLE: Bitmask of enabled RX rings\n- * @NFP_NET_CFG_MTU: Set MTU size\n- * @NFP_NET_CFG_FLBUFSZ: Set freelist buffer size (must be larger than MTU)\n- * @NFP_NET_CFG_EXN: MSI-X table entry for exceptions\n- * @NFP_NET_CFG_LSC: MSI-X table entry for link state changes\n- * @NFP_NET_CFG_MACADDR: MAC address\n- *\n- * TODO:\n- * - define Error details in UPDATE\n- */\n-#define NFP_NET_CFG_CTRL 0x0000\n-#define NFP_NET_CFG_CTRL_ENABLE (0x1 << 0) /* Global enable */\n-#define NFP_NET_CFG_CTRL_PROMISC (0x1 << 1) /* Enable Promisc mode */\n-#define NFP_NET_CFG_CTRL_L2BC (0x1 << 2) /* Allow L2 Broadcast */\n-#define NFP_NET_CFG_CTRL_L2MC (0x1 << 3) /* Allow L2 Multicast */\n-#define NFP_NET_CFG_CTRL_RXCSUM (0x1 << 4) /* Enable RX Checksum */\n-#define NFP_NET_CFG_CTRL_TXCSUM (0x1 << 5) /* Enable TX Checksum */\n-#define NFP_NET_CFG_CTRL_RXVLAN (0x1 << 6) /* Enable VLAN strip */\n-#define NFP_NET_CFG_CTRL_TXVLAN (0x1 << 7) /* Enable VLAN insert */\n-#define NFP_NET_CFG_CTRL_SCATTER (0x1 << 8) /* Scatter DMA */\n-#define NFP_NET_CFG_CTRL_GATHER (0x1 << 9) /* Gather DMA */\n-#define NFP_NET_CFG_CTRL_LSO (0x1 << 10) /* LSO/TSO */\n-#define NFP_NET_CFG_CTRL_RXQINQ (0x1 << 13) /* Enable QINQ strip */\n-#define NFP_NET_CFG_CTRL_RXVLAN_V2 (0x1 << 15) /* Enable VLAN strip with metadata */\n-#define NFP_NET_CFG_CTRL_RINGCFG (0x1 << 16) /* Ring runtime changes */\n-#define NFP_NET_CFG_CTRL_RSS (0x1 << 17) /* RSS */\n-#define NFP_NET_CFG_CTRL_IRQMOD (0x1 << 18) /* Interrupt moderation */\n-#define NFP_NET_CFG_CTRL_RINGPRIO (0x1 << 19) /* Ring priorities */\n-#define NFP_NET_CFG_CTRL_MSIXAUTO (0x1 << 20) /* MSI-X auto-masking */\n-#define NFP_NET_CFG_CTRL_TXRWB (0x1 << 21) /* Write-back of TX ring */\n-#define NFP_NET_CFG_CTRL_L2SWITCH (0x1 << 22) /* L2 Switch */\n-#define NFP_NET_CFG_CTRL_TXVLAN_V2 (0x1 << 23) /* Enable VLAN insert with metadata */\n-#define NFP_NET_CFG_CTRL_VXLAN (0x1 << 24) /* Enable VXLAN */\n-#define NFP_NET_CFG_CTRL_NVGRE (0x1 << 25) /* Enable NVGRE */\n-#define NFP_NET_CFG_CTRL_MSIX_TX_OFF (0x1 << 26) /* Disable MSIX for TX */\n-#define NFP_NET_CFG_CTRL_LSO2 (0x1 << 28) /* LSO/TSO (version 2) */\n-#define NFP_NET_CFG_CTRL_RSS2 (0x1 << 29) /* RSS (version 2) */\n-#define NFP_NET_CFG_CTRL_CSUM_COMPLETE (0x1 << 30) /* Checksum complete */\n-#define NFP_NET_CFG_CTRL_LIVE_ADDR (0x1U << 31) /* Live MAC addr change */\n-#define NFP_NET_CFG_UPDATE 0x0004\n-#define NFP_NET_CFG_UPDATE_GEN (0x1 << 0) /* General update */\n-#define NFP_NET_CFG_UPDATE_RING (0x1 << 1) /* Ring config change */\n-#define NFP_NET_CFG_UPDATE_RSS (0x1 << 2) /* RSS config change */\n-#define NFP_NET_CFG_UPDATE_TXRPRIO (0x1 << 3) /* TX Ring prio change */\n-#define NFP_NET_CFG_UPDATE_RXRPRIO (0x1 << 4) /* RX Ring prio change */\n-#define NFP_NET_CFG_UPDATE_MSIX (0x1 << 5) /* MSI-X change */\n-#define NFP_NET_CFG_UPDATE_L2SWITCH (0x1 << 6) /* Switch changes */\n-#define NFP_NET_CFG_UPDATE_RESET (0x1 << 7) /* Update due to FLR */\n-#define NFP_NET_CFG_UPDATE_IRQMOD (0x1 << 8) /* IRQ mod change */\n-#define NFP_NET_CFG_UPDATE_VXLAN (0x1 << 9) /* VXLAN port change */\n-#define NFP_NET_CFG_UPDATE_MACADDR (0x1 << 11) /* MAC address change */\n-#define NFP_NET_CFG_UPDATE_MBOX (0x1 << 12) /* Mailbox update */\n-#define NFP_NET_CFG_UPDATE_ERR (0x1U << 31) /* A error occurred */\n-#define NFP_NET_CFG_TXRS_ENABLE 0x0008\n-#define NFP_NET_CFG_RXRS_ENABLE 0x0010\n-#define NFP_NET_CFG_MTU 0x0018\n-#define NFP_NET_CFG_FLBUFSZ 0x001c\n-#define NFP_NET_CFG_EXN 0x001f\n-#define NFP_NET_CFG_LSC 0x0020\n-#define NFP_NET_CFG_MACADDR 0x0024\n-\n-#define NFP_NET_CFG_CTRL_LSO_ANY (NFP_NET_CFG_CTRL_LSO | NFP_NET_CFG_CTRL_LSO2)\n-#define NFP_NET_CFG_CTRL_RSS_ANY (NFP_NET_CFG_CTRL_RSS | NFP_NET_CFG_CTRL_RSS2)\n-\n-#define NFP_NET_CFG_CTRL_CHAIN_META (NFP_NET_CFG_CTRL_RSS2 | \\\n-\t\t\t\t\tNFP_NET_CFG_CTRL_CSUM_COMPLETE)\n-\n-/* Version number helper defines */\n-struct nfp_net_fw_ver {\n-\tuint8_t minor;\n-\tuint8_t major;\n-\tuint8_t class;\n-\t/**\n-\t * This byte can be extended for more use.\n-\t * BIT0: NFD dp type, refer NFP_NET_CFG_VERSION_DP_NFDx\n-\t * BIT[7:1]: reserved\n-\t */\n-\tuint8_t extend;\n-};\n-\n-/*\n- * Read-only words (0x0030 - 0x0050):\n- * @NFP_NET_CFG_VERSION: Firmware version number\n- * @NFP_NET_CFG_STS: Status\n- * @NFP_NET_CFG_CAP: Capabilities (same bits as @NFP_NET_CFG_CTRL)\n- * @NFP_NET_MAX_TXRINGS: Maximum number of TX rings\n- * @NFP_NET_MAX_RXRINGS: Maximum number of RX rings\n- * @NFP_NET_MAX_MTU: Maximum support MTU\n- * @NFP_NET_CFG_START_TXQ: Start Queue Control Queue to use for TX (PF only)\n- * @NFP_NET_CFG_START_RXQ: Start Queue Control Queue to use for RX (PF only)\n- *\n- * TODO:\n- * - define more STS bits\n- */\n-#define NFP_NET_CFG_VERSION 0x0030\n-#define NFP_NET_CFG_VERSION_DP_NFD3 0\n-#define NFP_NET_CFG_VERSION_DP_NFDK 1\n-#define NFP_NET_CFG_STS 0x0034\n-#define NFP_NET_CFG_STS_LINK (0x1 << 0) /* Link up or down */\n-/* Link rate */\n-#define NFP_NET_CFG_STS_LINK_RATE_SHIFT 1\n-#define NFP_NET_CFG_STS_LINK_RATE_MASK 0xF\n-#define NFP_NET_CFG_STS_LINK_RATE_UNSUPPORTED 0\n-#define NFP_NET_CFG_STS_LINK_RATE_UNKNOWN 1\n-#define NFP_NET_CFG_STS_LINK_RATE_1G 2\n-#define NFP_NET_CFG_STS_LINK_RATE_10G 3\n-#define NFP_NET_CFG_STS_LINK_RATE_25G 4\n-#define NFP_NET_CFG_STS_LINK_RATE_40G 5\n-#define NFP_NET_CFG_STS_LINK_RATE_50G 6\n-#define NFP_NET_CFG_STS_LINK_RATE_100G 7\n-\n-/*\n- * NSP Link rate is a 16-bit word. It is no longer determined by\n- * firmware, instead it is read from the nfp_eth_table of the\n- * associated pf_dev and written to the NFP_NET_CFG_STS_NSP_LINK_RATE\n- * address by the PMD each time the port is reconfigured.\n- */\n-#define NFP_NET_CFG_STS_NSP_LINK_RATE 0x0036\n-\n-#define NFP_NET_CFG_CAP 0x0038\n-#define NFP_NET_CFG_MAX_TXRINGS 0x003c\n-#define NFP_NET_CFG_MAX_RXRINGS 0x0040\n-#define NFP_NET_CFG_MAX_MTU 0x0044\n-/* Next two words are being used by VFs for solving THB350 issue */\n-#define NFP_NET_CFG_START_TXQ 0x0048\n-#define NFP_NET_CFG_START_RXQ 0x004c\n-\n-/*\n- * NFP-3200 workaround (0x0050 - 0x0058)\n- * @NFP_NET_CFG_SPARE_ADDR: DMA address for ME code to use (e.g. YDS-155 fix)\n- */\n-#define NFP_NET_CFG_SPARE_ADDR 0x0050\n-/*\n- * NFP6000/NFP4000 - Prepend configuration\n- */\n-#define NFP_NET_CFG_RX_OFFSET 0x0050\n-#define NFP_NET_CFG_RX_OFFSET_DYNAMIC 0 /* Prepend mode */\n-\n-/* Start anchor of the TLV area */\n-#define NFP_NET_CFG_TLV_BASE 0x0058\n-\n-/**\n- * Reuse spare address to contain the offset from the start of\n- * the host buffer where the first byte of the received frame\n- * will land. Any metadata will come prior to that offset. If the\n- * value in this field is 0, it means that the metadata will\n- * always land starting at the first byte of the host buffer and\n- * packet data will immediately follow the metadata. As always,\n- * the RX descriptor indicates the presence or absence of metadata\n- * along with the length thereof.\n- */\n-#define NFP_NET_CFG_RX_OFFSET_ADDR 0x0050\n-\n-#define NFP_NET_CFG_VXLAN_PORT 0x0060\n-#define NFP_NET_CFG_VXLAN_SZ 0x0008\n-\n-/* Offload definitions */\n-#define NFP_NET_N_VXLAN_PORTS (NFP_NET_CFG_VXLAN_SZ / sizeof(uint16_t))\n-\n-/*\n- * 3 words reserved for extended ctrl words (0x0098 - 0x00a4)\n- * 3 words reserved for extended cap words (0x00a4 - 0x00b0)\n- * Currently only one word is used, can be extended in future.\n- */\n-#define NFP_NET_CFG_CTRL_WORD1 0x0098\n-#define NFP_NET_CFG_CTRL_PKT_TYPE (0x1 << 0)\n-#define NFP_NET_CFG_CTRL_IPSEC (0x1 << 1) /**< IPsec offload */\n-#define NFP_NET_CFG_CTRL_IPSEC_SM_LOOKUP (0x1 << 3) /**< SA short match lookup */\n-#define NFP_NET_CFG_CTRL_IPSEC_LM_LOOKUP (0x1 << 4) /**< SA long match lookup */\n-\n-#define NFP_NET_CFG_CAP_WORD1 0x00a4\n-\n-/* 16B reserved for future use (0x00b0 - 0x00c0). */\n-#define NFP_NET_CFG_RESERVED 0x00b0\n-#define NFP_NET_CFG_RESERVED_SZ 0x0010\n-\n-/*\n- * RSS configuration (0x0100 - 0x01ac):\n- * Used only when NFP_NET_CFG_CTRL_RSS_ANY is enabled\n- * @NFP_NET_CFG_RSS_CFG: RSS configuration word\n- * @NFP_NET_CFG_RSS_KEY: RSS \"secret\" key\n- * @NFP_NET_CFG_RSS_ITBL: RSS indirection table\n- */\n-#define NFP_NET_CFG_RSS_BASE 0x0100\n-#define NFP_NET_CFG_RSS_CTRL NFP_NET_CFG_RSS_BASE\n-#define NFP_NET_CFG_RSS_MASK (0x7f)\n-#define NFP_NET_CFG_RSS_MASK_of(_x) ((_x) & 0x7f)\n-#define NFP_NET_CFG_RSS_IPV4 (1 << 8) /* RSS for IPv4 */\n-#define NFP_NET_CFG_RSS_IPV6 (1 << 9) /* RSS for IPv6 */\n-#define NFP_NET_CFG_RSS_IPV4_TCP (1 << 10) /* RSS for IPv4/TCP */\n-#define NFP_NET_CFG_RSS_IPV4_UDP (1 << 11) /* RSS for IPv4/UDP */\n-#define NFP_NET_CFG_RSS_IPV6_TCP (1 << 12) /* RSS for IPv6/TCP */\n-#define NFP_NET_CFG_RSS_IPV6_UDP (1 << 13) /* RSS for IPv6/UDP */\n-#define NFP_NET_CFG_RSS_IPV4_SCTP (1 << 14) /* RSS for IPv4/SCTP */\n-#define NFP_NET_CFG_RSS_IPV6_SCTP (1 << 15) /* RSS for IPv6/SCTP */\n-#define NFP_NET_CFG_RSS_TOEPLITZ (1 << 24) /* Use Toeplitz hash */\n-#define NFP_NET_CFG_RSS_KEY (NFP_NET_CFG_RSS_BASE + 0x4)\n-#define NFP_NET_CFG_RSS_KEY_SZ 0x28\n-#define NFP_NET_CFG_RSS_ITBL (NFP_NET_CFG_RSS_BASE + 0x4 + \\\n-\t\t\t\t\t NFP_NET_CFG_RSS_KEY_SZ)\n-#define NFP_NET_CFG_RSS_ITBL_SZ 0x80\n-\n-/*\n- * TX ring configuration (0x200 - 0x800)\n- * @NFP_NET_CFG_TXR_BASE: Base offset for TX ring configuration\n- * @NFP_NET_CFG_TXR_ADDR: Per TX ring DMA address (8B entries)\n- * @NFP_NET_CFG_TXR_WB_ADDR: Per TX ring write back DMA address (8B entries)\n- * @NFP_NET_CFG_TXR_SZ: Per TX ring size (1B entries)\n- * @NFP_NET_CFG_TXR_VEC: Per TX ring MSI-X table entry (1B entries)\n- * @NFP_NET_CFG_TXR_PRIO: Per TX ring priority (1B entries)\n- * @NFP_NET_CFG_TXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)\n- */\n-#define NFP_NET_CFG_TXR_BASE 0x0200\n-#define NFP_NET_CFG_TXR_ADDR(_x) (NFP_NET_CFG_TXR_BASE + ((_x) * 0x8))\n-#define NFP_NET_CFG_TXR_WB_ADDR(_x) (NFP_NET_CFG_TXR_BASE + 0x200 + \\\n-\t\t\t\t\t ((_x) * 0x8))\n-#define NFP_NET_CFG_TXR_SZ(_x) (NFP_NET_CFG_TXR_BASE + 0x400 + (_x))\n-#define NFP_NET_CFG_TXR_VEC(_x) (NFP_NET_CFG_TXR_BASE + 0x440 + (_x))\n-#define NFP_NET_CFG_TXR_PRIO(_x) (NFP_NET_CFG_TXR_BASE + 0x480 + (_x))\n-#define NFP_NET_CFG_TXR_IRQ_MOD(_x) (NFP_NET_CFG_TXR_BASE + 0x500 + \\\n-\t\t\t\t\t ((_x) * 0x4))\n-\n-/*\n- * RX ring configuration (0x0800 - 0x0c00)\n- * @NFP_NET_CFG_RXR_BASE: Base offset for RX ring configuration\n- * @NFP_NET_CFG_RXR_ADDR: Per TX ring DMA address (8B entries)\n- * @NFP_NET_CFG_RXR_SZ: Per TX ring size (1B entries)\n- * @NFP_NET_CFG_RXR_VEC: Per TX ring MSI-X table entry (1B entries)\n- * @NFP_NET_CFG_RXR_PRIO: Per TX ring priority (1B entries)\n- * @NFP_NET_CFG_RXR_IRQ_MOD: Per TX ring interrupt moderation (4B entries)\n- */\n-#define NFP_NET_CFG_RXR_BASE 0x0800\n-#define NFP_NET_CFG_RXR_ADDR(_x) (NFP_NET_CFG_RXR_BASE + ((_x) * 0x8))\n-#define NFP_NET_CFG_RXR_SZ(_x) (NFP_NET_CFG_RXR_BASE + 0x200 + (_x))\n-#define NFP_NET_CFG_RXR_VEC(_x) (NFP_NET_CFG_RXR_BASE + 0x240 + (_x))\n-#define NFP_NET_CFG_RXR_PRIO(_x) (NFP_NET_CFG_RXR_BASE + 0x280 + (_x))\n-#define NFP_NET_CFG_RXR_IRQ_MOD(_x) (NFP_NET_CFG_RXR_BASE + 0x300 + \\\n-\t\t\t\t\t ((_x) * 0x4))\n-\n-/*\n- * Interrupt Control/Cause registers (0x0c00 - 0x0d00)\n- * These registers are only used when MSI-X auto-masking is not\n- * enabled (@NFP_NET_CFG_CTRL_MSIXAUTO not set). The array is index\n- * by MSI-X entry and are 1B in size. If an entry is zero, the\n- * corresponding entry is enabled. If the FW generates an interrupt,\n- * it writes a cause into the corresponding field. This also masks\n- * the MSI-X entry and the host driver must clear the register to\n- * re-enable the interrupt.\n- */\n-#define NFP_NET_CFG_ICR_BASE 0x0c00\n-#define NFP_NET_CFG_ICR(_x) (NFP_NET_CFG_ICR_BASE + (_x))\n-#define NFP_NET_CFG_ICR_UNMASKED 0x0\n-#define NFP_NET_CFG_ICR_RXTX 0x1\n-#define NFP_NET_CFG_ICR_LSC 0x2\n-\n-/*\n- * General device stats (0x0d00 - 0x0d90)\n- * All counters are 64bit.\n- */\n-#define NFP_NET_CFG_STATS_BASE 0x0d00\n-#define NFP_NET_CFG_STATS_RX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x00)\n-#define NFP_NET_CFG_STATS_RX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x08)\n-#define NFP_NET_CFG_STATS_RX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x10)\n-#define NFP_NET_CFG_STATS_RX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x18)\n-#define NFP_NET_CFG_STATS_RX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x20)\n-#define NFP_NET_CFG_STATS_RX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x28)\n-#define NFP_NET_CFG_STATS_RX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x30)\n-#define NFP_NET_CFG_STATS_RX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x38)\n-#define NFP_NET_CFG_STATS_RX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x40)\n-\n-#define NFP_NET_CFG_STATS_TX_DISCARDS (NFP_NET_CFG_STATS_BASE + 0x48)\n-#define NFP_NET_CFG_STATS_TX_ERRORS (NFP_NET_CFG_STATS_BASE + 0x50)\n-#define NFP_NET_CFG_STATS_TX_OCTETS (NFP_NET_CFG_STATS_BASE + 0x58)\n-#define NFP_NET_CFG_STATS_TX_UC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x60)\n-#define NFP_NET_CFG_STATS_TX_MC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x68)\n-#define NFP_NET_CFG_STATS_TX_BC_OCTETS (NFP_NET_CFG_STATS_BASE + 0x70)\n-#define NFP_NET_CFG_STATS_TX_FRAMES (NFP_NET_CFG_STATS_BASE + 0x78)\n-#define NFP_NET_CFG_STATS_TX_MC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x80)\n-#define NFP_NET_CFG_STATS_TX_BC_FRAMES (NFP_NET_CFG_STATS_BASE + 0x88)\n-\n-#define NFP_NET_CFG_STATS_APP0_FRAMES (NFP_NET_CFG_STATS_BASE + 0x90)\n-#define NFP_NET_CFG_STATS_APP0_BYTES (NFP_NET_CFG_STATS_BASE + 0x98)\n-#define NFP_NET_CFG_STATS_APP1_FRAMES (NFP_NET_CFG_STATS_BASE + 0xa0)\n-#define NFP_NET_CFG_STATS_APP1_BYTES (NFP_NET_CFG_STATS_BASE + 0xa8)\n-#define NFP_NET_CFG_STATS_APP2_FRAMES (NFP_NET_CFG_STATS_BASE + 0xb0)\n-#define NFP_NET_CFG_STATS_APP2_BYTES (NFP_NET_CFG_STATS_BASE + 0xb8)\n-#define NFP_NET_CFG_STATS_APP3_FRAMES (NFP_NET_CFG_STATS_BASE + 0xc0)\n-#define NFP_NET_CFG_STATS_APP3_BYTES (NFP_NET_CFG_STATS_BASE + 0xc8)\n-\n-/*\n- * Per ring stats (0x1000 - 0x1800)\n- * Options, 64bit per entry\n- * @NFP_NET_CFG_TXR_STATS: TX ring statistics (Packet and Byte count)\n- * @NFP_NET_CFG_RXR_STATS: RX ring statistics (Packet and Byte count)\n- */\n-#define NFP_NET_CFG_TXR_STATS_BASE 0x1000\n-#define NFP_NET_CFG_TXR_STATS(_x) (NFP_NET_CFG_TXR_STATS_BASE + \\\n-\t\t\t\t\t ((_x) * 0x10))\n-#define NFP_NET_CFG_RXR_STATS_BASE 0x1400\n-#define NFP_NET_CFG_RXR_STATS(_x) (NFP_NET_CFG_RXR_STATS_BASE + \\\n-\t\t\t\t\t ((_x) * 0x10))\n+#include <nfp_common_ctrl.h>\n \n /*\n * Mac stats (0x0000 - 0x0200)\n", "prefixes": [ "13/25" ] }