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GET /api/patches/133388/?format=api
{ "id": 133388, "url": "http://patchwork.dpdk.org/api/patches/133388/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231026124347.22477-2-syalavarthi@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231026124347.22477-2-syalavarthi@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231026124347.22477-2-syalavarthi@marvell.com", "date": "2023-10-26T12:43:10", "name": "[v9,01/34] ml/cnxk: drop support for register polling", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "b5b2291cbdd165488a6c01e8818fbd31f3617176", "submitter": { "id": 2480, "url": "http://patchwork.dpdk.org/api/people/2480/?format=api", "name": "Srikanth Yalavarthi", "email": "syalavarthi@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231026124347.22477-2-syalavarthi@marvell.com/mbox/", "series": [ { "id": 30002, "url": "http://patchwork.dpdk.org/api/series/30002/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30002", "date": "2023-10-26T12:43:09", "name": "Implementation of revised ml/cnxk driver", "version": 9, "mbox": "http://patchwork.dpdk.org/series/30002/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133388/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/133388/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 701F643208;\n\tThu, 26 Oct 2023 14:44:02 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 3186342830;\n\tThu, 26 Oct 2023 14:43:58 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 6B1964025F\n for <dev@dpdk.org>; Thu, 26 Oct 2023 14:43:55 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 39QAKqcO006841 for <dev@dpdk.org>; Thu, 26 Oct 2023 05:43:54 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com (PPS) with ESMTPS id 3txcsr25pj-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 26 Oct 2023 05:43:54 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.48;\n Thu, 26 Oct 2023 05:43:52 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend\n Transport; Thu, 26 Oct 2023 05:43:52 -0700", "from ml-host-33.caveonetworks.com (unknown [10.110.143.233])\n by maili.marvell.com (Postfix) with ESMTP id D73F03F709C;\n Thu, 26 Oct 2023 05:43:51 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=IUf2NZ9FXs0E50CY00rNrQjHil0qfq9P8jRBvaeQPjs=;\n b=LYEP32zLHoFi0BeXIh/dWW0YxKmM3wxWCk74ku5gncrii2KL3XW4wN+BmJl20Jzxkfy3\n rJt9L7OfXDhajXQvhtvsSrtrJuOQTbZxE1V+rL794anBx5t4OeopAjNfdHCTllSjw3AE\n xTmolxa7Hjazd7buTFx90sETjFFomrjjhIMLoyafKQ8VFY1Du7BZNNI7o7yhHB5jbFrl\n PJMH3luuAoanYy2qKTs76R1eteKIvjtqkUlSoGAdAvtjVeOPgtB1ZPm1m4mvSezWpyvG\n qrRwM1cusrZhQQM0iGr4aJ/VA6y9VryQ7vCNZWqac/KxZovC0da4wIDINvOdwqBsJ9Fi ZQ==", "From": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "To": "Srikanth Yalavarthi <syalavarthi@marvell.com>", "CC": "<dev@dpdk.org>, <sshankarnara@marvell.com>, <aprabhu@marvell.com>,\n <ptakkar@marvell.com>", "Subject": "[PATCH v9 01/34] ml/cnxk: drop support for register polling", "Date": "Thu, 26 Oct 2023 05:43:10 -0700", "Message-ID": "<20231026124347.22477-2-syalavarthi@marvell.com>", "X-Mailer": "git-send-email 2.42.0", "In-Reply-To": "<20231026124347.22477-1-syalavarthi@marvell.com>", "References": "<20230830155927.3566-1-syalavarthi@marvell.com>\n <20231026124347.22477-1-syalavarthi@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "qdH4G50jNbj0QkIAfNXVQ40X9kn3JLSO", "X-Proofpoint-GUID": "qdH4G50jNbj0QkIAfNXVQ40X9kn3JLSO", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26\n definitions=2023-10-26_10,2023-10-26_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Dropped support for device argument \"poll_mem\" for cnxk\nML driver. Support to use registers for polling is removed\nand DDR addresses would be used for polling.\n\nSigned-off-by: Srikanth Yalavarthi <syalavarthi@marvell.com>\n---\n doc/guides/mldevs/cnxk.rst | 16 -----\n drivers/ml/cnxk/cn10k_ml_dev.c | 36 +----------\n drivers/ml/cnxk/cn10k_ml_dev.h | 13 +---\n drivers/ml/cnxk/cn10k_ml_ops.c | 111 ++++-----------------------------\n drivers/ml/cnxk/cn10k_ml_ops.h | 6 --\n 5 files changed, 18 insertions(+), 164 deletions(-)", "diff": "diff --git a/doc/guides/mldevs/cnxk.rst b/doc/guides/mldevs/cnxk.rst\nindex b79bc540d9..1834b1f905 100644\n--- a/doc/guides/mldevs/cnxk.rst\n+++ b/doc/guides/mldevs/cnxk.rst\n@@ -180,22 +180,6 @@ Runtime Config Options\n in the fast path enqueue burst operation.\n \n \n-**Polling memory location** (default ``ddr``)\n-\n- ML cnxk driver provides the option to select the memory location to be used\n- for polling to check the inference request completion.\n- Driver supports using either the DDR address space (``ddr``)\n- or ML registers (``register``) as polling locations.\n- The parameter ``poll_mem`` is used to specify the poll location.\n-\n- For example::\n-\n- -a 0000:00:10.0,poll_mem=\"register\"\n-\n- With the above configuration, ML cnxk driver is configured to use ML registers\n- for polling in fastpath requests.\n-\n-\n Debugging Options\n -----------------\n \ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.c b/drivers/ml/cnxk/cn10k_ml_dev.c\nindex 983138a7f2..e3c2badcef 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.c\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.c\n@@ -23,7 +23,6 @@\n #define CN10K_ML_DEV_CACHE_MODEL_DATA\t\"cache_model_data\"\n #define CN10K_ML_OCM_ALLOC_MODE\t\t\"ocm_alloc_mode\"\n #define CN10K_ML_DEV_HW_QUEUE_LOCK\t\"hw_queue_lock\"\n-#define CN10K_ML_FW_POLL_MEM\t\t\"poll_mem\"\n #define CN10K_ML_OCM_PAGE_SIZE\t\t\"ocm_page_size\"\n \n #define CN10K_ML_FW_PATH_DEFAULT\t\t\"/lib/firmware/mlip-fw.bin\"\n@@ -32,7 +31,6 @@\n #define CN10K_ML_DEV_CACHE_MODEL_DATA_DEFAULT\t1\n #define CN10K_ML_OCM_ALLOC_MODE_DEFAULT\t\t\"lowest\"\n #define CN10K_ML_DEV_HW_QUEUE_LOCK_DEFAULT\t1\n-#define CN10K_ML_FW_POLL_MEM_DEFAULT\t\t\"ddr\"\n #define CN10K_ML_OCM_PAGE_SIZE_DEFAULT\t\t16384\n \n /* ML firmware macros */\n@@ -54,7 +52,6 @@ static const char *const valid_args[] = {CN10K_ML_FW_PATH,\n \t\t\t\t\t CN10K_ML_DEV_CACHE_MODEL_DATA,\n \t\t\t\t\t CN10K_ML_OCM_ALLOC_MODE,\n \t\t\t\t\t CN10K_ML_DEV_HW_QUEUE_LOCK,\n-\t\t\t\t\t CN10K_ML_FW_POLL_MEM,\n \t\t\t\t\t CN10K_ML_OCM_PAGE_SIZE,\n \t\t\t\t\t NULL};\n \n@@ -103,9 +100,7 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \tbool hw_queue_lock_set = false;\n \tbool ocm_page_size_set = false;\n \tchar *ocm_alloc_mode = NULL;\n-\tbool poll_mem_set = false;\n \tbool fw_path_set = false;\n-\tchar *poll_mem = NULL;\n \tchar *fw_path = NULL;\n \tint ret = 0;\n \tbool found;\n@@ -189,17 +184,6 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t\thw_queue_lock_set = true;\n \t}\n \n-\tif (rte_kvargs_count(kvlist, CN10K_ML_FW_POLL_MEM) == 1) {\n-\t\tret = rte_kvargs_process(kvlist, CN10K_ML_FW_POLL_MEM, &parse_string_arg,\n-\t\t\t\t\t &poll_mem);\n-\t\tif (ret < 0) {\n-\t\t\tplt_err(\"Error processing arguments, key = %s\\n\", CN10K_ML_FW_POLL_MEM);\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto exit;\n-\t\t}\n-\t\tpoll_mem_set = true;\n-\t}\n-\n \tif (rte_kvargs_count(kvlist, CN10K_ML_OCM_PAGE_SIZE) == 1) {\n \t\tret = rte_kvargs_process(kvlist, CN10K_ML_OCM_PAGE_SIZE, &parse_integer_arg,\n \t\t\t\t\t &mldev->ocm_page_size);\n@@ -280,18 +264,6 @@ cn10k_mldev_parse_devargs(struct rte_devargs *devargs, struct cn10k_ml_dev *mlde\n \t}\n \tplt_info(\"ML: %s = %d\", CN10K_ML_DEV_HW_QUEUE_LOCK, mldev->hw_queue_lock);\n \n-\tif (!poll_mem_set) {\n-\t\tmldev->fw.poll_mem = CN10K_ML_FW_POLL_MEM_DEFAULT;\n-\t} else {\n-\t\tif (!((strcmp(poll_mem, \"ddr\") == 0) || (strcmp(poll_mem, \"register\") == 0))) {\n-\t\t\tplt_err(\"Invalid argument, %s = %s\\n\", CN10K_ML_FW_POLL_MEM, poll_mem);\n-\t\t\tret = -EINVAL;\n-\t\t\tgoto exit;\n-\t\t}\n-\t\tmldev->fw.poll_mem = poll_mem;\n-\t}\n-\tplt_info(\"ML: %s = %s\", CN10K_ML_FW_POLL_MEM, mldev->fw.poll_mem);\n-\n \tif (!ocm_page_size_set) {\n \t\tmldev->ocm_page_size = CN10K_ML_OCM_PAGE_SIZE_DEFAULT;\n \t} else {\n@@ -450,10 +422,7 @@ cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw)\n \tif (fw->report_dpe_warnings)\n \t\tflags = flags | FW_REPORT_DPE_WARNING_BITMASK;\n \n-\tif (strcmp(fw->poll_mem, \"ddr\") == 0)\n-\t\tflags = flags | FW_USE_DDR_POLL_ADDR_FP;\n-\telse if (strcmp(fw->poll_mem, \"register\") == 0)\n-\t\tflags = flags & ~FW_USE_DDR_POLL_ADDR_FP;\n+\tflags = flags | FW_USE_DDR_POLL_ADDR_FP;\n \n \treturn flags;\n }\n@@ -863,5 +832,4 @@ RTE_PMD_REGISTER_PARAM_STRING(MLDEV_NAME_CN10K_PMD, CN10K_ML_FW_PATH\n \t\t\t \"=<0|1>\" CN10K_ML_DEV_CACHE_MODEL_DATA\n \t\t\t \"=<0|1>\" CN10K_ML_OCM_ALLOC_MODE\n \t\t\t \"=<lowest|largest>\" CN10K_ML_DEV_HW_QUEUE_LOCK\n-\t\t\t \"=<0|1>\" CN10K_ML_FW_POLL_MEM \"=<ddr|register>\" CN10K_ML_OCM_PAGE_SIZE\n-\t\t\t \"=<1024|2048|4096|8192|16384>\");\n+\t\t\t \"=<0|1>\" CN10K_ML_OCM_PAGE_SIZE \"=<1024|2048|4096|8192|16384>\");\ndiff --git a/drivers/ml/cnxk/cn10k_ml_dev.h b/drivers/ml/cnxk/cn10k_ml_dev.h\nindex c73bf7d001..4aaeecff03 100644\n--- a/drivers/ml/cnxk/cn10k_ml_dev.h\n+++ b/drivers/ml/cnxk/cn10k_ml_dev.h\n@@ -390,9 +390,6 @@ struct cn10k_ml_fw {\n \t/* Report DPE warnings */\n \tint report_dpe_warnings;\n \n-\t/* Memory to be used for polling in fast-path requests */\n-\tconst char *poll_mem;\n-\n \t/* Data buffer */\n \tuint8_t *data;\n \n@@ -525,13 +522,9 @@ struct cn10k_ml_dev {\n \tbool (*ml_jcmdq_enqueue)(struct roc_ml *roc_ml, struct ml_job_cmd_s *job_cmd);\n \n \t/* Poll handling function pointers */\n-\tvoid (*set_poll_addr)(struct cn10k_ml_qp *qp, struct cn10k_ml_req *req, uint64_t idx);\n-\tvoid (*set_poll_ptr)(struct roc_ml *roc_ml, struct cn10k_ml_req *req);\n-\tuint64_t (*get_poll_ptr)(struct roc_ml *roc_ml, struct cn10k_ml_req *req);\n-\n-\t/* Memory barrier function pointers to handle synchronization */\n-\tvoid (*set_enq_barrier)(void);\n-\tvoid (*set_deq_barrier)(void);\n+\tvoid (*set_poll_addr)(struct cn10k_ml_req *req);\n+\tvoid (*set_poll_ptr)(struct cn10k_ml_req *req);\n+\tuint64_t (*get_poll_ptr)(struct cn10k_ml_req *req);\n };\n \n uint64_t cn10k_ml_fw_flags_get(struct cn10k_ml_fw *fw);\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.c b/drivers/ml/cnxk/cn10k_ml_ops.c\nindex 4abf4ae0d3..11531afd8c 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.c\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.c\n@@ -23,11 +23,6 @@\n #define ML_FLAGS_POLL_COMPL BIT(0)\n #define ML_FLAGS_SSO_COMPL BIT(1)\n \n-/* Scratch register range for poll mode requests */\n-#define ML_POLL_REGISTER_SYNC 1023\n-#define ML_POLL_REGISTER_START 1024\n-#define ML_POLL_REGISTER_END 2047\n-\n /* Error message length */\n #define ERRMSG_LEN 32\n \n@@ -82,79 +77,23 @@ print_line(FILE *fp, int len)\n }\n \n static inline void\n-cn10k_ml_set_poll_addr_ddr(struct cn10k_ml_qp *qp, struct cn10k_ml_req *req, uint64_t idx)\n+cn10k_ml_set_poll_addr(struct cn10k_ml_req *req)\n {\n-\tPLT_SET_USED(qp);\n-\tPLT_SET_USED(idx);\n-\n \treq->compl_W1 = PLT_U64_CAST(&req->status);\n }\n \n static inline void\n-cn10k_ml_set_poll_addr_reg(struct cn10k_ml_qp *qp, struct cn10k_ml_req *req, uint64_t idx)\n-{\n-\treq->compl_W1 = ML_SCRATCH(qp->block_start + idx % qp->block_size);\n-}\n-\n-static inline void\n-cn10k_ml_set_poll_ptr_ddr(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n+cn10k_ml_set_poll_ptr(struct cn10k_ml_req *req)\n {\n-\tPLT_SET_USED(roc_ml);\n-\n \tplt_write64(ML_CN10K_POLL_JOB_START, req->compl_W1);\n }\n \n-static inline void\n-cn10k_ml_set_poll_ptr_reg(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n-{\n-\troc_ml_reg_write64(roc_ml, ML_CN10K_POLL_JOB_START, req->compl_W1);\n-}\n-\n static inline uint64_t\n-cn10k_ml_get_poll_ptr_ddr(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n+cn10k_ml_get_poll_ptr(struct cn10k_ml_req *req)\n {\n-\tPLT_SET_USED(roc_ml);\n-\n \treturn plt_read64(req->compl_W1);\n }\n \n-static inline uint64_t\n-cn10k_ml_get_poll_ptr_reg(struct roc_ml *roc_ml, struct cn10k_ml_req *req)\n-{\n-\treturn roc_ml_reg_read64(roc_ml, req->compl_W1);\n-}\n-\n-static inline void\n-cn10k_ml_set_sync_addr(struct cn10k_ml_dev *mldev, struct cn10k_ml_req *req)\n-{\n-\tif (strcmp(mldev->fw.poll_mem, \"ddr\") == 0)\n-\t\treq->compl_W1 = PLT_U64_CAST(&req->status);\n-\telse if (strcmp(mldev->fw.poll_mem, \"register\") == 0)\n-\t\treq->compl_W1 = ML_SCRATCH(ML_POLL_REGISTER_SYNC);\n-}\n-\n-static inline void\n-cn10k_ml_enq_barrier_ddr(void)\n-{\n-}\n-\n-static inline void\n-cn10k_ml_deq_barrier_ddr(void)\n-{\n-}\n-\n-static inline void\n-cn10k_ml_enq_barrier_register(void)\n-{\n-\tdmb_st;\n-}\n-\n-static inline void\n-cn10k_ml_deq_barrier_register(void)\n-{\n-\tdsb_st;\n-}\n-\n static void\n qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n {\n@@ -242,9 +181,6 @@ cn10k_ml_qp_create(const struct rte_ml_dev *dev, uint16_t qp_id, uint32_t nb_des\n \tqp->stats.dequeued_count = 0;\n \tqp->stats.enqueue_err_count = 0;\n \tqp->stats.dequeue_err_count = 0;\n-\tqp->block_size =\n-\t\t(ML_POLL_REGISTER_END - ML_POLL_REGISTER_START + 1) / dev->data->nb_queue_pairs;\n-\tqp->block_start = ML_POLL_REGISTER_START + qp_id * qp->block_size;\n \n \t/* Initialize job command */\n \tfor (i = 0; i < qp->nb_desc; i++) {\n@@ -933,11 +869,7 @@ cn10k_ml_dev_info_get(struct rte_ml_dev *dev, struct rte_ml_dev_info *dev_info)\n \telse\n \t\tdev_info->max_queue_pairs = ML_CN10K_MAX_QP_PER_DEVICE_LF;\n \n-\tif (strcmp(mldev->fw.poll_mem, \"register\") == 0)\n-\t\tdev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP / dev_info->max_queue_pairs;\n-\telse if (strcmp(mldev->fw.poll_mem, \"ddr\") == 0)\n-\t\tdev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP;\n-\n+\tdev_info->max_desc = ML_CN10K_MAX_DESC_PER_QP;\n \tdev_info->max_io = ML_CN10K_MAX_INPUT_OUTPUT;\n \tdev_info->max_segments = ML_CN10K_MAX_SEGMENTS;\n \tdev_info->align_size = ML_CN10K_ALIGN_SIZE;\n@@ -1118,24 +1050,9 @@ cn10k_ml_dev_configure(struct rte_ml_dev *dev, const struct rte_ml_dev_config *c\n \t\tmldev->ml_jcmdq_enqueue = roc_ml_jcmdq_enqueue_lf;\n \n \t/* Set polling function pointers */\n-\tif (strcmp(mldev->fw.poll_mem, \"ddr\") == 0) {\n-\t\tmldev->set_poll_addr = cn10k_ml_set_poll_addr_ddr;\n-\t\tmldev->set_poll_ptr = cn10k_ml_set_poll_ptr_ddr;\n-\t\tmldev->get_poll_ptr = cn10k_ml_get_poll_ptr_ddr;\n-\t} else if (strcmp(mldev->fw.poll_mem, \"register\") == 0) {\n-\t\tmldev->set_poll_addr = cn10k_ml_set_poll_addr_reg;\n-\t\tmldev->set_poll_ptr = cn10k_ml_set_poll_ptr_reg;\n-\t\tmldev->get_poll_ptr = cn10k_ml_get_poll_ptr_reg;\n-\t}\n-\n-\t/* Set barrier function pointers */\n-\tif (strcmp(mldev->fw.poll_mem, \"ddr\") == 0) {\n-\t\tmldev->set_enq_barrier = cn10k_ml_enq_barrier_ddr;\n-\t\tmldev->set_deq_barrier = cn10k_ml_deq_barrier_ddr;\n-\t} else if (strcmp(mldev->fw.poll_mem, \"register\") == 0) {\n-\t\tmldev->set_enq_barrier = cn10k_ml_enq_barrier_register;\n-\t\tmldev->set_deq_barrier = cn10k_ml_deq_barrier_register;\n-\t}\n+\tmldev->set_poll_addr = cn10k_ml_set_poll_addr;\n+\tmldev->set_poll_ptr = cn10k_ml_set_poll_ptr;\n+\tmldev->get_poll_ptr = cn10k_ml_get_poll_ptr;\n \n \tdev->enqueue_burst = cn10k_ml_enqueue_burst;\n \tdev->dequeue_burst = cn10k_ml_dequeue_burst;\n@@ -2390,15 +2307,14 @@ cn10k_ml_enqueue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \top = ops[count];\n \treq = &queue->reqs[head];\n \n-\tmldev->set_poll_addr(qp, req, head);\n+\tmldev->set_poll_addr(req);\n \tcn10k_ml_prep_fp_job_descriptor(dev, req, op);\n \n \tmemset(&req->result, 0, sizeof(struct cn10k_ml_result));\n \treq->result.error_code.s.etype = ML_ETYPE_UNKNOWN;\n \treq->result.user_ptr = op->user_ptr;\n-\tmldev->set_enq_barrier();\n \n-\tmldev->set_poll_ptr(&mldev->roc, req);\n+\tmldev->set_poll_ptr(req);\n \tenqueued = mldev->ml_jcmdq_enqueue(&mldev->roc, &req->jcmd);\n \tif (unlikely(!enqueued))\n \t\tgoto jcmdq_full;\n@@ -2445,7 +2361,7 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \n dequeue_req:\n \treq = &queue->reqs[tail];\n-\tstatus = mldev->get_poll_ptr(&mldev->roc, req);\n+\tstatus = mldev->get_poll_ptr(req);\n \tif (unlikely(status != ML_CN10K_POLL_JOB_FINISH)) {\n \t\tif (plt_tsc_cycles() < req->timeout)\n \t\t\tgoto empty_or_active;\n@@ -2453,7 +2369,6 @@ cn10k_ml_dequeue_burst(struct rte_ml_dev *dev, uint16_t qp_id, struct rte_ml_op\n \t\t\treq->result.error_code.s.etype = ML_ETYPE_DRIVER;\n \t}\n \n-\tmldev->set_deq_barrier();\n \tcn10k_ml_result_update(dev, qp_id, &req->result, req->op);\n \tops[count] = req->op;\n \n@@ -2515,14 +2430,14 @@ cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)\n \tmodel = dev->data->models[op->model_id];\n \treq = model->req;\n \n-\tcn10k_ml_set_sync_addr(mldev, req);\n+\tcn10k_ml_set_poll_addr(req);\n \tcn10k_ml_prep_fp_job_descriptor(dev, req, op);\n \n \tmemset(&req->result, 0, sizeof(struct cn10k_ml_result));\n \treq->result.error_code.s.etype = ML_ETYPE_UNKNOWN;\n \treq->result.user_ptr = op->user_ptr;\n \n-\tmldev->set_poll_ptr(&mldev->roc, req);\n+\tmldev->set_poll_ptr(req);\n \treq->jcmd.w1.s.jobptr = PLT_U64_CAST(&req->jd);\n \n \ttimeout = true;\n@@ -2542,7 +2457,7 @@ cn10k_ml_inference_sync(struct rte_ml_dev *dev, struct rte_ml_op *op)\n \n \ttimeout = true;\n \tdo {\n-\t\tif (mldev->get_poll_ptr(&mldev->roc, req) == ML_CN10K_POLL_JOB_FINISH) {\n+\t\tif (mldev->get_poll_ptr(req) == ML_CN10K_POLL_JOB_FINISH) {\n \t\t\ttimeout = false;\n \t\t\tbreak;\n \t\t}\ndiff --git a/drivers/ml/cnxk/cn10k_ml_ops.h b/drivers/ml/cnxk/cn10k_ml_ops.h\nindex d64a9f27e6..005b093e45 100644\n--- a/drivers/ml/cnxk/cn10k_ml_ops.h\n+++ b/drivers/ml/cnxk/cn10k_ml_ops.h\n@@ -67,12 +67,6 @@ struct cn10k_ml_qp {\n \n \t/* Statistics per queue-pair */\n \tstruct rte_ml_dev_stats stats;\n-\n-\t/* Register block start for polling */\n-\tuint32_t block_start;\n-\n-\t/* Register block end for polling */\n-\tuint32_t block_size;\n };\n \n /* Device ops */\n", "prefixes": [ "v9", "01/34" ] }