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GET /api/patches/133598/?format=api
{ "id": 133598, "url": "http://patchwork.dpdk.org/api/patches/133598/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-25-getelson@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231029163202.216450-25-getelson@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231029163202.216450-25-getelson@nvidia.com", "date": "2023-10-29T16:31:57", "name": "[25/30] net/mlx5: sample the srv6 last segment", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "a7f858d7e64aeb1cabc81736b8491c39604290cd", "submitter": { "id": 1882, "url": "http://patchwork.dpdk.org/api/people/1882/?format=api", "name": "Gregory Etelson", "email": "getelson@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231029163202.216450-25-getelson@nvidia.com/mbox/", "series": [ { "id": 30049, "url": "http://patchwork.dpdk.org/api/series/30049/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30049", "date": "2023-10-29T16:31:33", "name": "[01/30] net/mlx5/hws: Definer, add mlx5dr context to definer_conv_data", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30049/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133598/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133598/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 82C0443238;\n\tSun, 29 Oct 2023 17:36:19 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DE01F42DE8;\n\tSun, 29 Oct 2023 17:33:56 +0100 (CET)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2063.outbound.protection.outlook.com [40.107.94.63])\n by mails.dpdk.org (Postfix) with ESMTP id 0199D42DE8\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gregory Etelson <getelson@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<getelson@nvidia.com>, <mkashani@nvidia.com>, <rasland@nvidia.com>,\n Rongwei Liu <rongweil@nvidia.com>, Ori Kam <orika@nvidia.com>, Suanming Mou\n <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>, Viacheslav Ovsiienko\n <viacheslavo@nvidia.com>", "Subject": "[PATCH 25/30] net/mlx5: sample the srv6 last segment", "Date": "Sun, 29 Oct 2023 18:31:57 +0200", "Message-ID": "<20231029163202.216450-25-getelson@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20231029163202.216450-1-getelson@nvidia.com>", "References": "<20231029163202.216450-1-getelson@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A0FF:EE_|LV2PR12MB5776:EE_", "X-MS-Office365-Filtering-Correlation-Id": "ef57af83-3fc0-4be2-4bda-08dbd89cd261", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n BS0IUrU3tYzMgwO1/4ew63s6X7E2TA1LRQJ1wbEQC8/xTHvsYSwX1uhJ+0anVWv2TylhkwlzKctQGd+dbkk0RymzJfVXkzVMZOBhWqqFZ1rZkzrGitHVBg0dVrA/NgLRx7g3xye32bqKUH2ebFd+ZzYkKr2rlg+v0/uw3nGeqrEC5plzLBbFSemEUyE2zMbDVmUWMMJaLU4tET4cwRS+2Z5zLeHUQfgBgSLBXuSFzqmJO8GtEZQDgP9GoT0F6dhCKbc8P6Cn8sylhi8NmTvQNT+LZHO0MlKiAQqiXG179XWnZZvCHVz3cZaTf2mfxmuDAwlVcd+yu9x1w1uT8IKeEMfS/0iokIywbwPsDdJ0GLqqY2Hr/I66y7TzSuberEZRBsbWBWLTCnwJLgGnW49fCrsZurIwOfbgf10UKXlHeyXSkS0XGvDzJ0LVeVv++PDKkO5Is7+zJVN1B04aX/Fac3WJAr73FdUvzDrAC+DJVql7x302gJdVLi9nzPT1CgjgY/I2IBvNMRAOXVFciUrtUAOQeiO8ruISosjs8Dz9AnRdX7Vf8WTaZm2laZcIa8+TfO5zVpCDA7fwRjx5rH3UA7L0Hc+g9aco/RGn0GD4aafriajP4GxVnGTXe8J5ojkfAm62z1SguXrpc/T56Uy9ooZyJ12JahiBfg/1APDnQyHLNNY6VoMQeYI1lbchC/hNVL8YfC7N3t7g9fw/lOsHMA==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(396003)(39860400002)(136003)(346002)(376002)(230922051799003)(1800799009)(64100799003)(186009)(451199024)(82310400011)(46966006)(36840700001)(1076003)(26005)(6286002)(336012)(426003)(356005)(2616005)(7636003)(36756003)(7696005)(36860700001)(82740400003)(107886003)(6666004)(55016003)(316002)(16526019)(86362001)(70586007)(54906003)(70206006)(478600001)(6916009)(83380400001)(47076005)(4326008)(41300700001)(8676002)(8936002)(2906002)(40480700001)(5660300002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Oct 2023 16:33:45.7115 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n ef57af83-3fc0-4be2-4bda-08dbd89cd261", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A0FF.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5776", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Rongwei Liu <rongweil@nvidia.com>\n\nWhen removing the IPv6 routing extension header from the\npackets, the destination address should be updated to the\nlast one in the segment list.\n\nEnlarge the hardware sample scope to cover the last segment.\n\nSigned-off-by: Rongwei Liu <rongweil@nvidia.com>\nAcked-by: Ori Kam <orika@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/net/mlx5/mlx5.c | 41 ++++++++++++++++++++++++++++++-----------\n drivers/net/mlx5/mlx5.h | 6 ++++++\n 2 files changed, 36 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5.c b/drivers/net/mlx5/mlx5.c\nindex cdb4eeb612..afb9c717dc 100644\n--- a/drivers/net/mlx5/mlx5.c\n+++ b/drivers/net/mlx5/mlx5.c\n@@ -1067,6 +1067,7 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev)\n \tstruct mlx5_devx_graph_node_attr node = {\n \t\t.modify_field_select = 0,\n \t};\n+\tuint32_t i;\n \tuint32_t ids[MLX5_GRAPH_NODE_SAMPLE_NUM];\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_common_dev_config *config = &priv->sh->cdev->config;\n@@ -1100,10 +1101,18 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev)\n \tnode.next_header_field_size = 0x8;\n \tnode.in[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_IP;\n \tnode.in[0].compare_condition_value = IPPROTO_ROUTING;\n-\tnode.sample[0].flow_match_sample_en = 1;\n-\t/* First come first serve no matter inner or outer. */\n-\tnode.sample[0].flow_match_sample_tunnel_mode = MLX5_GRAPH_SAMPLE_TUNNEL_FIRST;\n-\tnode.sample[0].flow_match_sample_offset_mode = MLX5_GRAPH_SAMPLE_OFFSET_FIXED;\n+\t/* Final IPv6 address. */\n+\tfor (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {\n+\t\tnode.sample[i].flow_match_sample_en = 1;\n+\t\tnode.sample[i].flow_match_sample_offset_mode =\n+\t\t\t\t\tMLX5_GRAPH_SAMPLE_OFFSET_FIXED;\n+\t\t/* First come first serve no matter inner or outer. */\n+\t\tnode.sample[i].flow_match_sample_tunnel_mode =\n+\t\t\t\t\tMLX5_GRAPH_SAMPLE_TUNNEL_FIRST;\n+\t\tnode.sample[i].flow_match_sample_field_base_offset =\n+\t\t\t\t\t(i + 1) * sizeof(uint32_t); /* in bytes */\n+\t}\n+\tnode.sample[0].flow_match_sample_field_base_offset = 0;\n \tnode.out[0].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_TCP;\n \tnode.out[0].compare_condition_value = IPPROTO_TCP;\n \tnode.out[1].arc_parse_graph_node = MLX5_GRAPH_ARC_NODE_UDP;\n@@ -1116,8 +1125,8 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev)\n \t\tgoto error;\n \t}\n \tpriv->sh->srh_flex_parser.flex.devx_fp->devx_obj = fp;\n-\tpriv->sh->srh_flex_parser.flex.mapnum = 1;\n-\tpriv->sh->srh_flex_parser.flex.devx_fp->num_samples = 1;\n+\tpriv->sh->srh_flex_parser.flex.mapnum = MLX5_SRV6_SAMPLE_NUM;\n+\tpriv->sh->srh_flex_parser.flex.devx_fp->num_samples = MLX5_SRV6_SAMPLE_NUM;\n \n \tret = mlx5_devx_cmd_query_parse_samples(fp, ids, priv->sh->srh_flex_parser.flex.mapnum,\n \t\t\t\t\t\t&priv->sh->srh_flex_parser.flex.devx_fp->anchor_id);\n@@ -1125,12 +1134,22 @@ mlx5_alloc_srh_flex_parser(struct rte_eth_dev *dev)\n \t\tDRV_LOG(ERR, \"Failed to query sample IDs.\");\n \t\tgoto error;\n \t}\n-\tret = mlx5_devx_cmd_match_sample_info_query(ibv_ctx, ids[0],\n-\t\t\t\t&priv->sh->srh_flex_parser.flex.devx_fp->sample_info[0]);\n-\tif (ret) {\n-\t\tDRV_LOG(ERR, \"Failed to query sample id information.\");\n-\t\tgoto error;\n+\tfor (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {\n+\t\tret = mlx5_devx_cmd_match_sample_info_query(ibv_ctx, ids[i],\n+\t\t\t\t\t&priv->sh->srh_flex_parser.flex.devx_fp->sample_info[i]);\n+\t\tif (ret) {\n+\t\t\tDRV_LOG(ERR, \"Failed to query sample id %u information.\", ids[i]);\n+\t\t\tgoto error;\n+\t\t}\n+\t}\n+\tfor (i = 0; i <= MLX5_SRV6_SAMPLE_NUM - 1 && i < MLX5_GRAPH_NODE_SAMPLE_NUM; i++) {\n+\t\tpriv->sh->srh_flex_parser.flex.devx_fp->sample_ids[i] = ids[i];\n+\t\tpriv->sh->srh_flex_parser.flex.map[i].width = sizeof(uint32_t) * CHAR_BIT;\n+\t\tpriv->sh->srh_flex_parser.flex.map[i].reg_id = i;\n+\t\tpriv->sh->srh_flex_parser.flex.map[i].shift =\n+\t\t\t\t\t\t(i + 1) * sizeof(uint32_t) * CHAR_BIT;\n \t}\n+\tpriv->sh->srh_flex_parser.flex.map[0].shift = 0;\n \treturn 0;\n error:\n \tif (fp)\ndiff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 0289cbd04b..ad82d8060e 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -1335,6 +1335,7 @@ struct mlx5_flex_pattern_field {\n \tuint16_t shift:5;\n \tuint16_t reg_id:5;\n };\n+\n #define MLX5_INVALID_SAMPLE_REG_ID 0x1F\n \n /* Port flex item context. */\n@@ -1346,6 +1347,11 @@ struct mlx5_flex_item {\n \tstruct mlx5_flex_pattern_field map[MLX5_FLEX_ITEM_MAPPING_NUM];\n };\n \n+/*\n+ * Sample an IPv6 address and the first dword of SRv6 header.\n+ * Then it is 16 + 4 = 20 bytes which is 5 dwords.\n+ */\n+#define MLX5_SRV6_SAMPLE_NUM 5\n /* Mlx5 internal flex parser profile structure. */\n struct mlx5_internal_flex_parser_profile {\n \tuint32_t refcnt;\n", "prefixes": [ "25/30" ] }