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GET /api/patches/133730/?format=api
{ "id": 133730, "url": "http://patchwork.dpdk.org/api/patches/133730/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231101145710.2356260-1-akozyrev@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231101145710.2356260-1-akozyrev@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231101145710.2356260-1-akozyrev@nvidia.com", "date": "2023-11-01T14:57:10", "name": "[v2] net/mlx5: replenish MPRQ buffers for miniCQEs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f689db344ca09bcc7e635609fe4e37b8a089e458", "submitter": { "id": 1873, "url": "http://patchwork.dpdk.org/api/people/1873/?format=api", "name": "Alexander Kozyrev", "email": "akozyrev@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231101145710.2356260-1-akozyrev@nvidia.com/mbox/", "series": [ { "id": 30097, "url": "http://patchwork.dpdk.org/api/series/30097/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30097", "date": "2023-11-01T14:57:10", "name": "[v2] net/mlx5: replenish MPRQ buffers for miniCQEs", "version": 2, "mbox": "http://patchwork.dpdk.org/series/30097/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133730/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133730/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=VLpdljX3xnfdsgOxGPr9ZT2gEOQ4o45amrO5Nzgcr3/8N7SNOj5f1w+2IQBF4YAx0S3Dw9yQmyh48QZ3HUKIwoIOmlTH1r/S/YuEZuQZDChq6K1t0qjO7uL28oHILAnF/2lFzzGxbWC01Aj4F5vf321ZSNVDiJZwmG3WRUxWUgXW8xdOp7MII1PcQcxXB9JHsMdIMRyL9mvpslFrGsHMJcCgeLuQqRWQKXPnpbLQ6+dpywA0yoZMljYEsK6733tnPkNdDKahazCPDWR5LYkRXavsQj5Cw3C38a6DUHh9PJFq+VF9ZP8iWAYRo2mWADAIRzz2RWYQwIQXMTIBJJmh2g==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.161)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.161 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.161; helo=mail.nvidia.com; pr=C", "From": "Alexander Kozyrev <akozyrev@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<suanmingm@nvidia.com>, <viacheslavo@nvidia.com>, <rasland@nvidia.com>", "Subject": "[PATCH v2] net/mlx5: replenish MPRQ buffers for miniCQEs", "Date": "Wed, 1 Nov 2023 16:57:10 +0200", "Message-ID": "<20231101145710.2356260-1-akozyrev@nvidia.com>", "X-Mailer": "git-send-email 2.18.2", "In-Reply-To": "<20231101144354.2296367-1-akozyrev@nvidia.com>", "References": "<20231101144354.2296367-1-akozyrev@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9D5:EE_|BL1PR12MB5945:EE_", "X-MS-Office365-Filtering-Correlation-Id": "e98a56b8-9c26-4930-742d-08dbdaeae356", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Kfg1YBhKwA6OZc5mqZmg7GfrlUvoW/1Ku9bkcSXbzyqIKKxejJ+3TRRWgvY9MadbLm6cETZEJRgbTmYOl8D/b87M51/lz5Vy9psyvoKcoTppp7T2kCT5VDM2djYEG9wrHmu5yYAvP5JsWGjzQ7r0S1j0EpaprGdXJh/IvulM8AeCPr+2H3ZWrzw28Zbjt3iRafdzBODYOh13eVJ2F6ySLvBoN+7EVkzl4PAvyW+evlCogDBE2x16HhrBq8uZmMvWFCRCcZ2+uYdrM161z83bGWivdsX+dwtc312zoifugYPdnBBJ12DG4WbkElAVywBCaAh6iaLpEo5qDefxB+kMQW4ojozH9CaUIBx2N7AfRLV2xRO0RHwj/3qH1PCqDaOP8A2fyT08SzUWt/N5owu4/jEvSrdG9KSMhcANjkON6fkqC+hp7vwwV6jmodX3QAbgfVhqgZvOJ9u6LAjpNKkR2R0ZNFkqz8awSPVeHnANMHHqq2LrDs0Ab9DgnkAmEPkqt/9aMZAfZEOrR7tKbCr/UKtLawEqDXSEaIWGn+V8Bfa2U+/vHCH5PiCOeybRjUxHOhN4fUeviz19byJJ4XgdA85I56W/F6NAp4khY051PZ+5SNoabrvC2aopUfTNqMxNg+yWCc58tghvyieWS5fZPXl1Mrb7D9TpsSIbltnbs6TYXiOD1otU8k82y/wrF1y4QsxcuZXnBnfj7ce4ft07xaUiXcXkft/XCe8GIdugL5mui5j3YMHurpeE4fg2pbEKG6kYk2Sk4TJGQJEzZVdmLw==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge2.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(39860400002)(396003)(346002)(136003)(376002)(230922051799003)(82310400011)(1800799009)(186009)(64100799003)(451199024)(40470700004)(36840700001)(46966006)(40480700001)(36860700001)(40460700003)(16526019)(54906003)(70206006)(47076005)(7636003)(83380400001)(6916009)(316002)(36756003)(356005)(2616005)(426003)(478600001)(70586007)(336012)(2906002)(107886003)(26005)(1076003)(86362001)(5660300002)(8936002)(41300700001)(4326008)(8676002)(82740400003)(6666004)(334744004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Nov 2023 14:57:37.2790 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n e98a56b8-9c26-4930-742d-08dbdaeae356", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000E9D5.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5945", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Keep unzipping if the next CQE is the miniCQE array in\nrxq_cq_decompress_v() routine only for non-MPRQ scenario,\nMPRQ requires buffer replenishment between the miniCQEs.\n\nRestore the check for the initial compressed CQE for SPRQ\nand check that the current CQE is not compressed before\ncopying it as a possible title CQE.\n\nSigned-off-by: Alexander Kozyrev <akozyrev@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rxtx_vec.c | 56 ++++++++++++++++++------\n drivers/net/mlx5/mlx5_rxtx_vec_altivec.h | 6 ++-\n drivers/net/mlx5/mlx5_rxtx_vec_neon.h | 6 ++-\n drivers/net/mlx5/mlx5_rxtx_vec_sse.h | 6 ++-\n 4 files changed, 54 insertions(+), 20 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_rxtx_vec.c b/drivers/net/mlx5/mlx5_rxtx_vec.c\nindex 2363d7ed27..1872bf310c 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec.c\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec.c\n@@ -331,6 +331,15 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts,\n \t}\n \t/* At this point, there shouldn't be any remaining packets. */\n \tMLX5_ASSERT(rxq->decompressed == 0);\n+\t/* Go directly to unzipping in case the first CQE is compressed. */\n+\tif (rxq->cqe_comp_layout) {\n+\t\tret = check_cqe_iteration(cq, rxq->cqe_n, rxq->cq_ci);\n+\t\tif (ret == MLX5_CQE_STATUS_SW_OWN &&\n+\t\t (MLX5_CQE_FORMAT(cq->op_own) == MLX5_COMPRESSED)) {\n+\t\t\tcomp_idx = 0;\n+\t\t\tgoto decompress;\n+\t\t}\n+\t}\n \t/* Process all the CQEs */\n \tnocmp_n = rxq_cq_process_v(rxq, cq, elts, pkts, pkts_n, err, &comp_idx);\n \t/* If no new CQE seen, return without updating cq_db. */\n@@ -345,18 +354,23 @@ rxq_burst_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts,\n \trcvd_pkt += nocmp_n;\n \t/* Copy title packet for future compressed sessions. */\n \tif (rxq->cqe_comp_layout) {\n-\t\tnext = &(*rxq->cqes)[rxq->cq_ci & q_mask];\n-\t\tret = check_cqe_iteration(next,\trxq->cqe_n, rxq->cq_ci);\n-\t\tif (ret != MLX5_CQE_STATUS_SW_OWN ||\n-\t\t MLX5_CQE_FORMAT(next->op_own) == MLX5_COMPRESSED)\n-\t\t\trte_memcpy(&rxq->title_pkt, elts[nocmp_n - 1],\n-\t\t\t\t sizeof(struct rte_mbuf));\n+\t\tret = check_cqe_iteration(cq, rxq->cqe_n, rxq->cq_ci);\n+\t\tif (ret == MLX5_CQE_STATUS_SW_OWN &&\n+\t\t (MLX5_CQE_FORMAT(cq->op_own) != MLX5_COMPRESSED)) {\n+\t\t\tnext = &(*rxq->cqes)[rxq->cq_ci & q_mask];\n+\t\t\tret = check_cqe_iteration(next,\trxq->cqe_n, rxq->cq_ci);\n+\t\t\tif (MLX5_CQE_FORMAT(next->op_own) == MLX5_COMPRESSED ||\n+\t\t\t ret != MLX5_CQE_STATUS_SW_OWN)\n+\t\t\t\trte_memcpy(&rxq->title_pkt, elts[nocmp_n - 1],\n+\t\t\t\t\t sizeof(struct rte_mbuf));\n+\t\t}\n \t}\n+decompress:\n \t/* Decompress the last CQE if compressed. */\n \tif (comp_idx < MLX5_VPMD_DESCS_PER_LOOP) {\n \t\tMLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n \t\trxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],\n-\t\t\t\t\t\t\t&elts[nocmp_n]);\n+\t\t\t\t\t\t\t&elts[nocmp_n], true);\n \t\trxq->cq_ci += rxq->decompressed;\n \t\t/* Return more packets if needed. */\n \t\tif (nocmp_n < pkts_n) {\n@@ -482,6 +496,15 @@ rxq_burst_mprq_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts,\n \t}\n \t/* At this point, there shouldn't be any remaining packets. */\n \tMLX5_ASSERT(rxq->decompressed == 0);\n+\t/* Go directly to unzipping in case the first CQE is compressed. */\n+\tif (rxq->cqe_comp_layout) {\n+\t\tret = check_cqe_iteration(cq, rxq->cqe_n, rxq->cq_ci);\n+\t\tif (ret == MLX5_CQE_STATUS_SW_OWN &&\n+\t\t (MLX5_CQE_FORMAT(cq->op_own) == MLX5_COMPRESSED)) {\n+\t\t\tcomp_idx = 0;\n+\t\t\tgoto decompress;\n+\t\t}\n+\t}\n \t/* Process all the CQEs */\n \tnocmp_n = rxq_cq_process_v(rxq, cq, elts, pkts, pkts_n, err, &comp_idx);\n \t/* If no new CQE seen, return without updating cq_db. */\n@@ -495,18 +518,23 @@ rxq_burst_mprq_v(struct mlx5_rxq_data *rxq, struct rte_mbuf **pkts,\n \trcvd_pkt += cp_pkt;\n \t/* Copy title packet for future compressed sessions. */\n \tif (rxq->cqe_comp_layout) {\n-\t\tnext = &(*rxq->cqes)[rxq->cq_ci & q_mask];\n-\t\tret = check_cqe_iteration(next,\trxq->cqe_n, rxq->cq_ci);\n-\t\tif (ret != MLX5_CQE_STATUS_SW_OWN ||\n-\t\t MLX5_CQE_FORMAT(next->op_own) == MLX5_COMPRESSED)\n-\t\t\trte_memcpy(&rxq->title_pkt, elts[nocmp_n - 1],\n-\t\t\t\t sizeof(struct rte_mbuf));\n+\t\tret = check_cqe_iteration(cq, rxq->cqe_n, rxq->cq_ci);\n+\t\tif (ret == MLX5_CQE_STATUS_SW_OWN &&\n+\t\t (MLX5_CQE_FORMAT(cq->op_own) != MLX5_COMPRESSED)) {\n+\t\t\tnext = &(*rxq->cqes)[rxq->cq_ci & q_mask];\n+\t\t\tret = check_cqe_iteration(next,\trxq->cqe_n, rxq->cq_ci);\n+\t\t\tif (MLX5_CQE_FORMAT(next->op_own) == MLX5_COMPRESSED ||\n+\t\t\t ret != MLX5_CQE_STATUS_SW_OWN)\n+\t\t\t\trte_memcpy(&rxq->title_pkt, elts[nocmp_n - 1],\n+\t\t\t\t\t sizeof(struct rte_mbuf));\n+\t\t}\n \t}\n+decompress:\n \t/* Decompress the last CQE if compressed. */\n \tif (comp_idx < MLX5_VPMD_DESCS_PER_LOOP) {\n \t\tMLX5_ASSERT(comp_idx == (nocmp_n % MLX5_VPMD_DESCS_PER_LOOP));\n \t\trxq->decompressed = rxq_cq_decompress_v(rxq, &cq[nocmp_n],\n-\t\t\t\t\t\t\t&elts[nocmp_n]);\n+\t\t\t\t\t\t\t&elts[nocmp_n], false);\n \t\t/* Return more packets if needed. */\n \t\tif (nocmp_n < pkts_n) {\n \t\t\tuint16_t n = rxq->decompressed;\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\nindex cccfa7f2d3..b2bbc4ba17 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_altivec.h\n@@ -68,13 +68,15 @@ rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n)\n * @param elts\n * Pointer to SW ring to be filled. The first mbuf has to be pre-built from\n * the title completion descriptor to be copied to the rest of mbufs.\n+ * @param keep\n+ * Keep unzipping if the next CQE is the miniCQE array.\n *\n * @return\n * Number of mini-CQEs successfully decompressed.\n */\n static inline uint16_t\n rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n-\t\t struct rte_mbuf **elts)\n+\t\t struct rte_mbuf **elts, bool keep)\n {\n \tvolatile struct mlx5_mini_cqe8 *mcq =\n \t\t(void *)&(cq + !rxq->cqe_comp_layout)->pkt_info;\n@@ -507,7 +509,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\t}\n \t}\n \n-\tif (rxq->cqe_comp_layout) {\n+\tif (rxq->cqe_comp_layout && keep) {\n \t\tint ret;\n \t\t/* Keep unzipping if the next CQE is the miniCQE array. */\n \t\tcq = &cq[mcqe_n];\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\nindex 3ed688191f..510f60b25d 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_neon.h\n@@ -63,13 +63,15 @@ rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n)\n * @param elts\n * Pointer to SW ring to be filled. The first mbuf has to be pre-built from\n * the title completion descriptor to be copied to the rest of mbufs.\n+ * @param keep\n+ * Keep unzipping if the next CQE is the miniCQE array.\n *\n * @return\n * Number of mini-CQEs successfully decompressed.\n */\n static inline uint16_t\n rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n-\t\t struct rte_mbuf **elts)\n+\t\t struct rte_mbuf **elts, bool keep)\n {\n \tvolatile struct mlx5_mini_cqe8 *mcq =\n \t\t(void *)&(cq + !rxq->cqe_comp_layout)->pkt_info;\n@@ -372,7 +374,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\t\t}\n \t\t}\n \t}\n-\tif (rxq->cqe_comp_layout) {\n+\tif (rxq->cqe_comp_layout && keep) {\n \t\tint ret;\n \t\t/* Keep unzipping if the next CQE is the miniCQE array. */\n \t\tcq = &cq[mcqe_n];\ndiff --git a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\nindex 2bdd1f676d..06bec45cdf 100644\n--- a/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n+++ b/drivers/net/mlx5/mlx5_rxtx_vec_sse.h\n@@ -65,13 +65,15 @@ rxq_copy_mbuf_v(struct rte_mbuf **elts, struct rte_mbuf **pkts, uint16_t n)\n * @param elts\n * Pointer to SW ring to be filled. The first mbuf has to be pre-built from\n * the title completion descriptor to be copied to the rest of mbufs.\n+ * @param keep\n+ * Keep unzipping if the next CQE is the miniCQE array.\n *\n * @return\n * Number of mini-CQEs successfully decompressed.\n */\n static inline uint16_t\n rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n-\t\t struct rte_mbuf **elts)\n+\t\t struct rte_mbuf **elts, bool keep)\n {\n \tvolatile struct mlx5_mini_cqe8 *mcq = (void *)(cq + !rxq->cqe_comp_layout);\n \t/* Title packet is pre-built. */\n@@ -361,7 +363,7 @@ rxq_cq_decompress_v(struct mlx5_rxq_data *rxq, volatile struct mlx5_cqe *cq,\n \t\t\t}\n \t\t}\n \t}\n-\tif (rxq->cqe_comp_layout) {\n+\tif (rxq->cqe_comp_layout && keep) {\n \t\tint ret;\n \t\t/* Keep unzipping if the next CQE is the miniCQE array. */\n \t\tcq = &cq[mcqe_n];\n", "prefixes": [ "v2" ] }