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GET /api/patches/133897/?format=api
{ "id": 133897, "url": "http://patchwork.dpdk.org/api/patches/133897/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231103133037.782512-1-venkatx.sivaramakrishnan@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231103133037.782512-1-venkatx.sivaramakrishnan@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20231103133037.782512-1-venkatx.sivaramakrishnan@intel.com", "date": "2023-11-03T13:30:36", "name": "[1/2] crypto/qat: fix block cipher misalignment for AES CBC and 3DES CBC", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2ae39228459c7e8a30ad4a9500337db585bd7add", "submitter": { "id": 3155, "url": "http://patchwork.dpdk.org/api/people/3155/?format=api", "name": "Sivaramakrishnan Venkat", "email": "venkatx.sivaramakrishnan@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231103133037.782512-1-venkatx.sivaramakrishnan@intel.com/mbox/", "series": [ { "id": 30170, "url": "http://patchwork.dpdk.org/api/series/30170/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30170", "date": "2023-11-03T13:30:36", "name": "[1/2] crypto/qat: fix block cipher misalignment for AES CBC and 3DES CBC", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30170/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/133897/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/133897/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 05650432B0;\n\tMon, 6 Nov 2023 15:18:15 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C1BFD402B6;\n\tMon, 6 Nov 2023 15:18:14 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 089CE40273;\n Fri, 3 Nov 2023 14:30:48 +0100 (CET)", "from orviesa001.jf.intel.com ([10.64.159.141])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 Nov 2023 06:30:43 -0700", "from silpixa00401012.ir.intel.com ([10.243.22.112])\n by orviesa001.jf.intel.com with ESMTP; 03 Nov 2023 06:30:42 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1699018249; x=1730554249;\n h=from:to:cc:subject:date:message-id:mime-version:\n content-transfer-encoding;\n bh=gXUequ1arGdD9KOCSCMlKtQHDbr4EYvjgh6h6ibPvNI=;\n b=dtrO0O4Ol9A3A52xpy2NF/W3VAPUilpf6i9gG1Z9M/5fTnFgezChjTEJ\n TERrEqQQw7/6LayYZHqGMBdeId5mIVvvQTDWnVIAK7MoYO41XxtvYkXn3\n cBfov0P/N/4PoE/VJ1txB4iY/teTvr5NHM68LuT2OptpwhXPTz4jikxoq\n qoXIPiQKXd2nZKqSR9G+jtPocUhsZqDcHTd0wjqjLBxDMFho7Q3UuhGKi\n u2jLa7rVsN5AJwP/1MJXht81zIACJmvc9cHQAVSY58WjLwCF4TxzaYRwm\n AuvNSGsDzpDoJlgIL+Dx53n1ht9c6t5q3zVJ7VfpFk0TfaeRPL5Ai+ZEu Q==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10883\"; a=\"388770132\"", "E=Sophos;i=\"6.03,273,1694761200\"; d=\"scan'208\";a=\"388770132\"", "E=Sophos;i=\"6.03,273,1694761200\";\n d=\"scan'208\";a=\"9378740\"" ], "X-ExtLoop1": "1", "From": "Sivaramakrishnan Venkat <venkatx.sivaramakrishnan@intel.com>", "To": "Kai Ji <kai.ji@intel.com>", "Cc": "dev@dpdk.org, stable@dpdk.org, gakhil@marvell.com,\n Sivaramakrishnan Venkat <venkatx.sivaramakrishnan@intel.com>", "Subject": "[PATCH 1/2] crypto/qat: fix block cipher misalignment for AES CBC and\n 3DES CBC", "Date": "Fri, 3 Nov 2023 13:30:36 +0000", "Message-Id": "<20231103133037.782512-1-venkatx.sivaramakrishnan@intel.com>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Mailman-Approved-At": "Mon, 06 Nov 2023 15:18:13 +0100", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "check cipher length alignment for 3DES CBC and AES CBC\nto change it to NULL op for buffer misalignment\n\nFixes: a815a04cea05 (\"crypto/qat: support symmetric build op request\")\nFixes: 85fec6fd9674 (\"crypto/qat: unify raw data path functions\")\nFixes: def38073ac90 (\"crypto/qat: check cipher buffer alignment\")\nCc: kai.ji@intel.com\nCc: stable@dpdk.org\n\nSigned-off-by: Sivaramakrishnan Venkat <venkatx.sivaramakrishnan@intel.com>\n---\n drivers/crypto/qat/dev/qat_crypto_pmd_gens.h | 35 +++++++++++---------\n drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 12 +++----\n drivers/crypto/qat/qat_sym.h | 9 +++++\n 3 files changed, 35 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\nindex 37647374d5..49053e662e 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gens.h\n@@ -616,7 +616,8 @@ static __rte_always_inline void\n enqueue_one_cipher_job_gen1(struct qat_sym_session *ctx,\n \tstruct icp_qat_fw_la_bulk_req *req,\n \tstruct rte_crypto_va_iova_ptr *iv,\n-\tunion rte_crypto_sym_ofs ofs, uint32_t data_len)\n+\tunion rte_crypto_sym_ofs ofs, uint32_t data_len,\n+\tstruct qat_sym_op_cookie *cookie)\n {\n \tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n \n@@ -627,6 +628,15 @@ enqueue_one_cipher_job_gen1(struct qat_sym_session *ctx,\n \tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n \tcipher_param->cipher_length = data_len - ofs.ofs.cipher.head -\n \t\t\tofs.ofs.cipher.tail;\n+\n+\tif (AES_OR_3DES_MISALIGNED) {\n+\t\tQAT_LOG(DEBUG,\n+\t \"Input cipher buffer misalignment detected and change job as NULL operation\");\n+\t\tstruct icp_qat_fw_comn_req_hdr *header = &req->comn_hdr;\n+\t\theader->service_type = ICP_QAT_FW_COMN_REQ_NULL;\n+\t\theader->service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;\n+\t\tcookie->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t}\n }\n \n static __rte_always_inline void\n@@ -683,7 +693,8 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,\n \tstruct rte_crypto_va_iova_ptr *cipher_iv,\n \tstruct rte_crypto_va_iova_ptr *digest,\n \tstruct rte_crypto_va_iova_ptr *auth_iv,\n-\tunion rte_crypto_sym_ofs ofs, uint32_t data_len)\n+\tunion rte_crypto_sym_ofs ofs, uint32_t data_len,\n+\tstruct qat_sym_op_cookie *cookie)\n {\n \tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n \tstruct icp_qat_fw_la_auth_req_params *auth_param;\n@@ -711,20 +722,14 @@ enqueue_one_chain_job_gen1(struct qat_sym_session *ctx,\n \tauth_param->auth_off = ofs.ofs.auth.head;\n \tauth_param->auth_len = auth_len;\n \tauth_param->auth_res_addr = digest->iova;\n-\t/* Input cipher length alignment requirement for 3DES-CBC and AES-CBC.\n-\t * For 3DES-CBC cipher algo, ESP Payload size requires 8 Byte aligned.\n-\t * For AES-CBC cipher algo, ESP Payload size requires 16 Byte aligned.\n-\t * The alignment should be guaranteed by the ESP package padding field\n-\t * according to the RFC4303. Under this condition, QAT will pass through\n-\t * chain job as NULL cipher and NULL auth operation and report misalignment\n-\t * error detected.\n-\t */\n \tif (AES_OR_3DES_MISALIGNED) {\n-\t\tQAT_LOG(ERR, \"Input cipher length alignment error detected.\\n\");\n-\t\tctx->qat_cipher_alg = ICP_QAT_HW_CIPHER_ALGO_NULL;\n-\t\tctx->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_NULL;\n-\t\tcipher_param->cipher_length = 0;\n-\t\tauth_param->auth_len = 0;\n+\t\tQAT_LOG(DEBUG,\n+\t \"Input cipher buffer misalignment detected and change job as NULL operation\");\n+\t\tstruct icp_qat_fw_comn_req_hdr *header = &req->comn_hdr;\n+\t\theader->service_type = ICP_QAT_FW_COMN_REQ_NULL;\n+\t\theader->service_cmd_id = ICP_QAT_FW_NULL_REQ_SERV_ID;\n+\t\tcookie->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\treturn -1;\n \t}\n \n \tswitch (ctx->qat_hash_alg) {\ndiff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\nindex e4bcfa59e7..208b7e0ba6 100644\n--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n@@ -248,7 +248,7 @@ qat_sym_build_op_cipher_gen1(void *in_op, struct qat_sym_session *ctx,\n \t\treturn -EINVAL;\n \t}\n \n-\tenqueue_one_cipher_job_gen1(ctx, req, &cipher_iv, ofs, total_len);\n+\tenqueue_one_cipher_job_gen1(ctx, req, &cipher_iv, ofs, total_len, op_cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, in_sgl.vec, in_sgl.num, &cipher_iv,\n \t\t\tNULL, NULL, NULL);\n@@ -383,7 +383,7 @@ qat_sym_build_op_chain_gen1(void *in_op, struct qat_sym_session *ctx,\n \n \tenqueue_one_chain_job_gen1(ctx, req, in_sgl.vec, in_sgl.num,\n \t\t\tout_sgl.vec, out_sgl.num, &cipher_iv, &digest, &auth_iv,\n-\t\t\tofs, total_len);\n+\t\t\tofs, total_len, cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, in_sgl.vec, in_sgl.num, &cipher_iv,\n \t\t\t&auth_iv, NULL, &digest);\n@@ -507,7 +507,7 @@ qat_sym_dp_enqueue_single_cipher_gen1(void *qp_data, uint8_t *drv_ctx,\n \tif (unlikely(data_len < 0))\n \t\treturn -1;\n \n-\tenqueue_one_cipher_job_gen1(ctx, req, iv, ofs, (uint32_t)data_len);\n+\tenqueue_one_cipher_job_gen1(ctx, req, iv, ofs, (uint32_t)data_len, cookie);\n \n \tqat_sym_debug_log_dump(req, ctx, data, n_data_vecs, iv,\n \t\t\tNULL, NULL, NULL);\n@@ -564,7 +564,7 @@ qat_sym_dp_enqueue_cipher_jobs_gen1(void *qp_data, uint8_t *drv_ctx,\n \t\tif (unlikely(data_len < 0))\n \t\t\tbreak;\n \t\tenqueue_one_cipher_job_gen1(ctx, req, &vec->iv[i], ofs,\n-\t\t\t(uint32_t)data_len);\n+\t\t\t(uint32_t)data_len, cookie);\n \t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\n \n \t\tqat_sym_debug_log_dump(req, ctx, vec->src_sgl[i].vec,\n@@ -740,7 +740,7 @@ qat_sym_dp_enqueue_single_chain_gen1(void *qp_data, uint8_t *drv_ctx,\n \n \tif (unlikely(enqueue_one_chain_job_gen1(ctx, req, data, n_data_vecs,\n \t\t\tNULL, 0, cipher_iv, job_digest, auth_iv, ofs,\n-\t\t\t(uint32_t)data_len)))\n+\t\t\t(uint32_t)data_len, cookie)))\n \t\treturn -1;\n \n \tdp_ctx->tail = tail;\n@@ -811,7 +811,7 @@ qat_sym_dp_enqueue_chain_jobs_gen1(void *qp_data, uint8_t *drv_ctx,\n \t\t\t\tvec->src_sgl[i].vec, vec->src_sgl[i].num,\n \t\t\t\tNULL, 0,\n \t\t\t\t&vec->iv[i], job_digest,\n-\t\t\t\t&vec->auth_iv[i], ofs, (uint32_t)data_len)))\n+\t\t\t\t&vec->auth_iv[i], ofs, (uint32_t)data_len, cookie)))\n \t\t\tbreak;\n \n \t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex d19cadde86..bc25ddf33d 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -115,6 +115,7 @@ struct qat_sym_op_cookie {\n \t} opt;\n \tuint8_t digest_null[4];\n \tphys_addr_t digest_null_phys_addr;\n+\tenum rte_crypto_op_status status;\n };\n \n struct qat_sym_dp_ctx {\n@@ -319,6 +320,7 @@ qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie,\n \t\t\t(resp_msg->opaque_data);\n \tstruct qat_sym_session *sess;\n \tuint8_t is_docsis_sec;\n+\tstruct qat_sym_op_cookie *cookie = NULL;\n \n #if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n \tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat_response:\", (uint8_t *)resp_msg,\n@@ -364,6 +366,13 @@ qat_sym_process_response(void **op, uint8_t *resp, void *op_cookie,\n \t\t\t\tsess->auth_key_length);\n \t}\n \n+\tcookie = (struct qat_sym_op_cookie *) op_cookie;\n+\tif (cookie->status == RTE_CRYPTO_OP_STATUS_INVALID_ARGS) {\n+\t\trx_op->status = cookie->status;\n+\t\tresp_msg->comn_hdr.service_id = ICP_QAT_FW_COMN_RESP_SERV_CPM_FW;\n+\t\tcookie->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\t}\n+\n \t*op = (void *)rx_op;\n \n \t/*\n", "prefixes": [ "1/2" ] }