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GET /api/patches/135243/?format=api
{ "id": 135243, "url": "http://patchwork.dpdk.org/api/patches/135243/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20231217202040.478959-1-chuanyu.xue@uconn.edu/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20231217202040.478959-1-chuanyu.xue@uconn.edu>", "list_archive_url": "https://inbox.dpdk.org/dev/20231217202040.478959-1-chuanyu.xue@uconn.edu", "date": "2023-12-17T20:20:40", "name": "net/e1000: support launchtime feature", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "29dbe9d57437225168bf61288070f1a274741412", "submitter": { "id": 3251, "url": "http://patchwork.dpdk.org/api/people/3251/?format=api", "name": "Chuanyu Xue", "email": "chuanyu.xue@uconn.edu" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20231217202040.478959-1-chuanyu.xue@uconn.edu/mbox/", "series": [ { "id": 30585, "url": "http://patchwork.dpdk.org/api/series/30585/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30585", "date": "2023-12-17T20:20:40", "name": "net/e1000: support launchtime feature", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30585/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135243/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/135243/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D6BF94371D;\n\tSun, 17 Dec 2023 21:21:26 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id A7FB74025C;\n\tSun, 17 Dec 2023 21:21:24 +0100 (CET)", "from mail-qk1-f174.google.com (mail-qk1-f174.google.com\n [209.85.222.174])\n by mails.dpdk.org (Postfix) with ESMTP id DB18140042\n for <dev@dpdk.org>; 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a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1702844482; x=1703449282;\n h=content-transfer-encoding:mime-version:message-id:date:subject:cc\n :to:from:x-gm-message-state:from:to:cc:subject:date:message-id\n :reply-to;\n bh=mHTUH6NB3QTNsEWYKlcwcvSQiVEI4T0BCvU9GaH42kE=;\n b=EryEY3K9KoXTEV0LuhbJi3GH7/sVijs+DP6PwQyiR51JBjkhvlndgJJq8LB3HPpJ95\n HBCkdoZPwl1wjllm3wxUL7w3JeXJEv2slK6zFqtZd7ObV+ZKN+NzY3pBzzAq5e6EM54V\n WHXkKFmNd4YIu+3FsinT4obSMCek/nZcZ92xXonZ5jiuiXqx17Al/CJ992ORs005bQyN\n hw1WAhWeTRTHB9xh3TFsX0vF1ogOPQeyB3jNdcgs6MJPWU0c+QxsMNxJdwumFE9aIl18\n /jn+eZmYDGysR1UJK4ICriyhmXMNhUm6L7PJyeBc31zRZq/HP6SfGnIpDXCX2uJIW3BB\n 1Hxw==", "X-Gm-Message-State": "AOJu0YyeptmIB5l/lvegx9ZfS4BrxSBLyNRjs7hHUsKrqxMqd3qNnLby\n rhfQ3ANdqk24ELCQhRmDePu6gUfq7tjObYSDeCpH0pdy", "X-Google-Smtp-Source": "\n AGHT+IHnH6QUfSfSBWFtq9Px0CQglZ3eStsgaMvrP0dSgOHzZNvVSijpt2KZJElqEwsgC1DNih8XpA==", "X-Received": "by 2002:a05:620a:13c1:b0:77d:8be4:dca6 with SMTP id\n g1-20020a05620a13c100b0077d8be4dca6mr16842184qkl.42.1702844482053;\n Sun, 17 Dec 2023 12:21:22 -0800 (PST)", "From": "Chuanyu Xue <chuanyu.xue@uconn.edu>", "To": "wenzhuo.lu@intel.com,\n\tqi.z.zhang@intel.com,\n\tbeilei.xing@intel.com", "Cc": "dev@dpdk.org,\n\tChuanyu Xue <chuanyu.xue@uconn.edu>", "Subject": "[PATCH] net/e1000: support launchtime feature", "Date": "Sun, 17 Dec 2023 15:20:40 -0500", "Message-Id": "<20231217202040.478959-1-chuanyu.xue@uconn.edu>", "X-Mailer": "git-send-email 2.25.1", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Enable the time-based scheduled Tx of packets based on the\nRTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP flag. The launchtime defines the\npacket transmission time based on PTP clock at MAC layer, which should\nbe set to the advanced transmit descriptor.\n\nSigned-off-by: Chuanyu Xue <chuanyu.xue@uconn.edu>\n---\n drivers/net/e1000/base/e1000_regs.h | 1 +\n drivers/net/e1000/e1000_ethdev.h | 3 ++\n drivers/net/e1000/igb_ethdev.c | 28 ++++++++++++++++++\n drivers/net/e1000/igb_rxtx.c | 44 ++++++++++++++++++++++++-----\n 4 files changed, 69 insertions(+), 7 deletions(-)", "diff": "diff --git a/drivers/net/e1000/base/e1000_regs.h b/drivers/net/e1000/base/e1000_regs.h\nindex d44de59c29..092d9d71e6 100644\n--- a/drivers/net/e1000/base/e1000_regs.h\n+++ b/drivers/net/e1000/base/e1000_regs.h\n@@ -162,6 +162,7 @@\n \n /* QAV Tx mode control register */\n #define E1000_I210_TQAVCTRL\t0x3570\n+#define E1000_I210_LAUNCH_OS0 0x3578\n \n /* QAV Tx mode control register bitfields masks */\n /* QAV enable */\ndiff --git a/drivers/net/e1000/e1000_ethdev.h b/drivers/net/e1000/e1000_ethdev.h\nindex 718a9746ed..174f7aaf52 100644\n--- a/drivers/net/e1000/e1000_ethdev.h\n+++ b/drivers/net/e1000/e1000_ethdev.h\n@@ -382,6 +382,9 @@ extern struct igb_rss_filter_list igb_filter_rss_list;\n TAILQ_HEAD(igb_flow_mem_list, igb_flow_mem);\n extern struct igb_flow_mem_list igb_flow_list;\n \n+extern uint64_t igb_tx_timestamp_dynflag;\n+extern int igb_tx_timestamp_dynfield_offset;\n+\n extern const struct rte_flow_ops igb_flow_ops;\n \n /*\ndiff --git a/drivers/net/e1000/igb_ethdev.c b/drivers/net/e1000/igb_ethdev.c\nindex 8858f975f8..4d3d8ae30a 100644\n--- a/drivers/net/e1000/igb_ethdev.c\n+++ b/drivers/net/e1000/igb_ethdev.c\n@@ -223,6 +223,7 @@ static int igb_timesync_read_time(struct rte_eth_dev *dev,\n \t\t\t\t struct timespec *timestamp);\n static int igb_timesync_write_time(struct rte_eth_dev *dev,\n \t\t\t\t const struct timespec *timestamp);\n+static int eth_igb_read_clock(__rte_unused struct rte_eth_dev *dev, uint64_t *clock);\n static int eth_igb_rx_queue_intr_enable(struct rte_eth_dev *dev,\n \t\t\t\t\tuint16_t queue_id);\n static int eth_igb_rx_queue_intr_disable(struct rte_eth_dev *dev,\n@@ -313,6 +314,9 @@ static const struct rte_pci_id pci_id_igbvf_map[] = {\n \t{ .vendor_id = 0, /* sentinel */ },\n };\n \n+uint64_t igb_tx_timestamp_dynflag;\n+int igb_tx_timestamp_dynfield_offset = -1;\n+\n static const struct rte_eth_desc_lim rx_desc_lim = {\n \t.nb_max = E1000_MAX_RING_DESC,\n \t.nb_min = E1000_MIN_RING_DESC,\n@@ -389,6 +393,7 @@ static const struct eth_dev_ops eth_igb_ops = {\n \t.timesync_adjust_time = igb_timesync_adjust_time,\n \t.timesync_read_time = igb_timesync_read_time,\n \t.timesync_write_time = igb_timesync_write_time,\n+\t.read_clock\t\t = eth_igb_read_clock,\n };\n \n /*\n@@ -1198,6 +1203,7 @@ eth_igb_start(struct rte_eth_dev *dev)\n \tstruct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);\n \tstruct rte_intr_handle *intr_handle = pci_dev->intr_handle;\n \tint ret, mask;\n+\tuint32_t tqavctrl;\n \tuint32_t intr_vector = 0;\n \tuint32_t ctrl_ext;\n \tuint32_t *speeds;\n@@ -1281,6 +1287,15 @@ eth_igb_start(struct rte_eth_dev *dev)\n \t\treturn ret;\n \t}\n \n+\tif (igb_tx_timestamp_dynflag > 0) {\n+\t\ttqavctrl = E1000_READ_REG(hw, E1000_I210_TQAVCTRL);\n+\t\ttqavctrl |= E1000_TQAVCTRL_MODE;\n+\t\ttqavctrl |= E1000_TQAVCTRL_FETCH_ARB; /* Fetch the queue most empty, no Round Robin*/\n+\t\ttqavctrl |= E1000_TQAVCTRL_LAUNCH_TIMER_ENABLE; /* Enable launch time */\n+\t\tE1000_WRITE_REG(hw, E1000_I210_TQAVCTRL, tqavctrl);\n+\t\tE1000_WRITE_REG(hw, E1000_I210_LAUNCH_OS0, 1ULL << 31); /* Set launch offset to default */\n+\t}\n+\n \te1000_clear_hw_cntrs_base_generic(hw);\n \n \t/*\n@@ -4882,6 +4897,19 @@ igb_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n \treturn 0;\n }\n \n+static int\n+eth_igb_read_clock(__rte_unused struct rte_eth_dev *dev, uint64_t *clock)\n+{\n+\tuint64_t systime_cycles;\n+\tstruct e1000_adapter *adapter = dev->data->dev_private;\n+\n+\tsystime_cycles = igb_read_systime_cyclecounter(dev);\n+\tuint64_t ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);\n+\t*clock = ns;\n+\n+\treturn 0;\n+}\n+\n static int\n eth_igb_get_reg_length(struct rte_eth_dev *dev __rte_unused)\n {\ndiff --git a/drivers/net/e1000/igb_rxtx.c b/drivers/net/e1000/igb_rxtx.c\nindex 448c4b7d9d..e5da8e250d 100644\n--- a/drivers/net/e1000/igb_rxtx.c\n+++ b/drivers/net/e1000/igb_rxtx.c\n@@ -212,6 +212,9 @@ struct igb_tx_queue {\n #define IGB_TSO_MAX_HDRLEN\t\t\t(512)\n #define IGB_TSO_MAX_MSS\t\t\t\t(9216)\n \n+/* Macro to compensate latency in launch time offloading*/\n+#define E1000_I210_LT_LATENCY\t\t0x41F9\n+\n /*********************************************************************\n *\n * TX function\n@@ -244,12 +247,13 @@ check_tso_para(uint64_t ol_req, union igb_tx_offload ol_para)\n static inline void\n igbe_set_xmit_ctx(struct igb_tx_queue* txq,\n \t\tvolatile struct e1000_adv_tx_context_desc *ctx_txd,\n-\t\tuint64_t ol_flags, union igb_tx_offload tx_offload)\n+\t\tuint64_t ol_flags, union igb_tx_offload tx_offload, uint64_t txtime)\n {\n \tuint32_t type_tucmd_mlhl;\n \tuint32_t mss_l4len_idx;\n \tuint32_t ctx_idx, ctx_curr;\n \tuint32_t vlan_macip_lens;\n+\tuint32_t launch_time;\n \tunion igb_tx_offload tx_offload_mask;\n \n \tctx_curr = txq->ctx_curr;\n@@ -312,16 +316,25 @@ igbe_set_xmit_ctx(struct igb_tx_queue* txq,\n \t\t}\n \t}\n \n-\ttxq->ctx_cache[ctx_curr].flags = ol_flags;\n-\ttxq->ctx_cache[ctx_curr].tx_offload.data =\n-\t\ttx_offload_mask.data & tx_offload.data;\n-\ttxq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;\n+\tif (!txtime) {\n+\t\ttxq->ctx_cache[ctx_curr].flags = ol_flags;\n+\t\ttxq->ctx_cache[ctx_curr].tx_offload.data =\n+\t\t\ttx_offload_mask.data & tx_offload.data;\n+\t\ttxq->ctx_cache[ctx_curr].tx_offload_mask = tx_offload_mask;\n+\t}\n \n \tctx_txd->type_tucmd_mlhl = rte_cpu_to_le_32(type_tucmd_mlhl);\n \tvlan_macip_lens = (uint32_t)tx_offload.data;\n \tctx_txd->vlan_macip_lens = rte_cpu_to_le_32(vlan_macip_lens);\n \tctx_txd->mss_l4len_idx = rte_cpu_to_le_32(mss_l4len_idx);\n \tctx_txd->u.seqnum_seed = 0;\n+\n+\tif (txtime) {\n+\t\tlaunch_time = (txtime - E1000_I210_LT_LATENCY) % NSEC_PER_SEC;\n+\t\tctx_txd->u.launch_time = rte_cpu_to_le_32(launch_time / 32);\n+\t} else {\n+\t\tctx_txd->u.launch_time = 0;\n+\t}\n }\n \n /*\n@@ -400,6 +413,7 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \tuint32_t new_ctx = 0;\n \tuint32_t ctx = 0;\n \tunion igb_tx_offload tx_offload = {0};\n+\tuint64_t ts;\n \n \ttxq = tx_queue;\n \tsw_ring = txq->sw_ring;\n@@ -552,7 +566,12 @@ eth_igb_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts,\n \t\t\t\t\ttxe->mbuf = NULL;\n \t\t\t\t}\n \n-\t\t\t\tigbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload);\n+\t\t\t\tif (igb_tx_timestamp_dynflag > 0) {\n+\t\t\t\t\tts = *RTE_MBUF_DYNFIELD(tx_pkt, igb_tx_timestamp_dynfield_offset, uint64_t *);\n+\t\t\t\t\tigbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, ts);\n+\t\t\t\t} else {\n+\t\t\t\t\tigbe_set_xmit_ctx(txq, ctx_txd, tx_ol_req, tx_offload, 0);\n+\t\t\t\t}\n \n \t\t\t\ttxe->last_id = tx_last;\n \t\t\t\ttx_id = txe->next_id;\n@@ -1464,7 +1483,8 @@ igb_get_tx_port_offloads_capa(struct rte_eth_dev *dev)\n \t\t\t RTE_ETH_TX_OFFLOAD_TCP_CKSUM |\n \t\t\t RTE_ETH_TX_OFFLOAD_SCTP_CKSUM |\n \t\t\t RTE_ETH_TX_OFFLOAD_TCP_TSO |\n-\t\t\t RTE_ETH_TX_OFFLOAD_MULTI_SEGS;\n+\t\t\t RTE_ETH_TX_OFFLOAD_MULTI_SEGS |\n+\t\t\t RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP;\n \n \treturn tx_offload_capa;\n }\n@@ -2579,9 +2599,11 @@ eth_igb_tx_init(struct rte_eth_dev *dev)\n {\n \tstruct e1000_hw *hw;\n \tstruct igb_tx_queue *txq;\n+\tuint64_t offloads = dev->data->dev_conf.txmode.offloads;\n \tuint32_t tctl;\n \tuint32_t txdctl;\n \tuint16_t i;\n+\tint err;\n \n \thw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n \n@@ -2612,6 +2634,14 @@ eth_igb_tx_init(struct rte_eth_dev *dev)\n \t\tdev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED;\n \t}\n \n+\tif (offloads & RTE_ETH_TX_OFFLOAD_SEND_ON_TIMESTAMP) {\n+\t\terr = rte_mbuf_dyn_tx_timestamp_register(\n+\t\t\t&igb_tx_timestamp_dynfield_offset,\n+\t\t\t&igb_tx_timestamp_dynflag);\n+\t\tif (err)\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to register tx timestamp dynamic field\");\n+\t}\n+\n \t/* Program the Transmit Control Register. */\n \ttctl = E1000_READ_REG(hw, E1000_TCTL);\n \ttctl &= ~E1000_TCTL_CT;\n", "prefixes": [] }