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GET /api/patches/135848/?format=api
{ "id": 135848, "url": "http://patchwork.dpdk.org/api/patches/135848/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240112075055.1288263-3-gavinl@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240112075055.1288263-3-gavinl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240112075055.1288263-3-gavinl@nvidia.com", "date": "2024-01-12T07:50:55", "name": "[V1,2/2] net/mlx5: use traffic class PRM field for IPv6 modification", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "af139e12764e42a27f84f7274822b257ef8c1c1f", "submitter": { "id": 3217, "url": "http://patchwork.dpdk.org/api/people/3217/?format=api", "name": "Gavin Li", "email": "gavinl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240112075055.1288263-3-gavinl@nvidia.com/mbox/", "series": [ { "id": 30787, "url": "http://patchwork.dpdk.org/api/series/30787/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30787", "date": "2024-01-12T07:50:53", "name": "use traffic class PRM field for IPv6 modification", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30787/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135848/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/135848/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 85F544389F;\n\tFri, 12 Jan 2024 08:51:41 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DE8484069D;\n\tFri, 12 Jan 2024 08:51:34 +0100 (CET)", "from NAM04-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam04on2040.outbound.protection.outlook.com [40.107.102.40])\n by mails.dpdk.org (Postfix) with ESMTP id 584DE4067B\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Gavin Li <gavinl@nvidia.com>", "To": "<dev@dpdk.org>, <dsosnowski@nvidia.com>, <viacheslavo@nvidia.com>,\n <orika@nvidia.com>, <suanmingm@nvidia.com>, <matan@nvidia.com>", "CC": "<jiaweiw@nvidia.com>, <rasland@nvidia.com>", "Subject": "[V1 2/2] net/mlx5: use traffic class PRM field for IPv6 modification", "Date": "Fri, 12 Jan 2024 09:50:55 +0200", "Message-ID": "<20240112075055.1288263-3-gavinl@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240112075055.1288263-1-gavinl@nvidia.com>", "References": "<20240112075055.1288263-1-gavinl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF0002636A:EE_|MW3PR12MB4474:EE_", "X-MS-Office365-Filtering-Correlation-Id": "3b772e86-d8fe-43e8-353f-08dc134349fc", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n jJ+v7O6BFVwURodkAnP9Ec88Ax03pCTHZtc2spKcm7Uto6wga+eAU4N/NGu2kmrAUL2V0U4di4lxZsePH73It321cg6SJ4U2iK0IBlLzaK309mXN5SHWyV07kz+6Zajw91viXBOjB8MWUk7Wx4GMsEaBHuTcmo+ABEPoQdoyI2emt4MQr9VweyddRmFTFmJMs5fYKIrlMPPKkxlDUf8C3D7vvEoPps+4E/5jOqXQnhC6kLSqXpWo+Qkz8XQxkteIvdVPwtiX6WGB364pGeR7QvLTMk3XWn9o5j+vTZuHIZUnF2sFMgH4hzZz6ZaGO5gaWfj0WwufaYJXped3w2orZNwjnIn6nvsCKE/vlulVjKR3/TGWLoiAdH5cF4YYuoVZvvYkP+DbttrMhhos4ZPp2YrUEbntN99Zh+2Ekf6ezqg9h0Aa1R89HaY0JnAMMuaczqu+rcAfHVJ4I3sDcBFkeOEnOi2dX4a1hRGFnbdC1XqPe2JW7gOcNjFkczcB5vPL90UhFL0R6+D/uJ4N0S7Bzgv34ypH+t2acK796zehybALj269BUtp2e5N/1S/AZEtqFDFRZ5/bd9Mh9vjKOvqV5I4sARFcchh+lfiUUrDDGKkQy8bDLr4y2JY1c3pw3sHSirLLUN84l4jdvhT7DeeWE0REHyPAgOGvsYKHuMc4TXm79CKMSC6ZJi3wJCpz5je0GTXyEKkKJDQOSiMAqLT5lM0/mGLR26dlB3uss0qEhc6NXJQKZiHnZVDe9kuAPRm5DNycnZRdR9Og+lB221QQQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.161; 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Ip=[216.228.117.161];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SN1PEPF0002636A.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4474", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "New PRM defined new field OUT_IPV6_TRAFFIC_CLASS for IPv6 which will be\nused by both IPv6 ECN and DSCP. A new cap bit\nmodify_out_ipv6_traffic_class is added. It can be used to check if the\nnew field is supported by FW.\n\nHowever, IPv6 ECN and DSCP starts from different offset in the same byte.\nUpdate SWS and HWS to used the new filed and introduce extra offset for\nIPv6 DSCP data and mask to solve the issue.\n\nSigned-off-by: Gavin Li <gavinl@nvidia.com>\nAcked-by: Suanming Mou <suanmingm@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 3 ++\n drivers/common/mlx5/mlx5_devx_cmds.h | 1 +\n drivers/common/mlx5/mlx5_prm.h | 8 ++-\n drivers/net/mlx5/linux/mlx5_os.c | 5 +-\n drivers/net/mlx5/mlx5_flow.h | 3 ++\n drivers/net/mlx5/mlx5_flow_dv.c | 78 ++++++++++++++++++++++++----\n drivers/net/mlx5/mlx5_flow_hw.c | 7 +++\n 7 files changed, 92 insertions(+), 13 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 4d8818924a..3a894f894a 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -1229,6 +1229,9 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->modify_outer_ip_ecn = MLX5_GET\n \t\t(flow_table_nic_cap, hcattr,\n \t\t ft_header_modify_nic_receive.outer_ip_ecn);\n+\tattr->modify_outer_ipv6_traffic_class = MLX5_GET\n+\t\t(flow_table_nic_cap, hcattr,\n+\t\t ft_header_modify_nic_receive.outer_ipv6_traffic_class);\n \tattr->set_reg_c = 0xffff;\n \tif (attr->nic_flow_table) {\n #define GET_RX_REG_X_BITS \\\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex 7f23e925a5..4a6008dc1a 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -304,6 +304,7 @@ struct mlx5_hca_attr {\n \tuint32_t set_reg_c:16;\n \tuint32_t nic_flow_table:1;\n \tuint32_t modify_outer_ip_ecn:1;\n+\tuint32_t modify_outer_ipv6_traffic_class:1;\n \tunion {\n \t\tuint32_t max_flow_counter;\n \t\tstruct {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex 0d46ba9c40..69404b5ed8 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -848,6 +848,7 @@ enum mlx5_modification_field {\n \tMLX5_MODI_META_REG_C_13 = 0x94,\n \tMLX5_MODI_META_REG_C_14 = 0x95,\n \tMLX5_MODI_META_REG_C_15 = 0x96,\n+\tMLX5_MODI_OUT_IPV6_TRAFFIC_CLASS = 0x11C,\n \tMLX5_MODI_OUT_IPV4_TOTAL_LEN = 0x11D,\n \tMLX5_MODI_OUT_IPV6_PAYLOAD_LEN = 0x11E,\n \tMLX5_MODI_OUT_IPV4_IHL = 0x11F,\n@@ -2202,7 +2203,9 @@ struct mlx5_ifc_ft_fields_support_bits {\n \t\tu8 metadata_reg_c_x[0x8];\n \t}; /* end of DW3 */\n \t/* set_action_field_support_2 */\n-\tu8 reserved_at_80[0x80];\n+\tu8 reserved_at_80[0x37];\n+\tu8 outer_ipv6_traffic_class[0x1];\n+\tu8 reserved_at_B8[0x48];\n \t/* add_action_field_support */\n \tu8 reserved_at_100[0x80];\n \t/* add_action_field_support_2 */\n@@ -2240,7 +2243,8 @@ struct mlx5_ifc_ft_fields_support_2_bits {\n \tu8 inner_l4_checksum_ok[0x1];\n \tu8 outer_ipv4_checksum_ok[0x1];\n \tu8 outer_l4_checksum_ok[0x1]; /* end of DW0 */\n-\tu8 reserved_at_20[0x18];\n+\tu8 reserved_at_20[0x17];\n+\tu8 outer_ipv6_traffic_class[0x1];\n \tunion {\n \t\tstruct {\n \t\t\tu8 metadata_reg_c_15[0x1];\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 5ae31c88f4..6ea0296109 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1602,9 +1602,10 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tgoto error;\n \t}\n \trte_rwlock_init(&priv->ind_tbls_lock);\n-\tif (sh->config.dv_flow_en == 1 &&\n+\tif (!priv->sh->cdev->config.hca_attr.modify_outer_ipv6_traffic_class ||\n+\t (sh->config.dv_flow_en == 1 &&\n \t !priv->sh->ipv6_tc_fallback &&\n-\t mlx5_flow_discover_ipv6_tc_support(eth_dev))\n+\t mlx5_flow_discover_ipv6_tc_support(eth_dev)))\n \t\tpriv->sh->ipv6_tc_fallback = 1;\n \tif (priv->sh->config.dv_flow_en == 2) {\n #ifdef HAVE_MLX5_HWS_SUPPORT\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 33d4a28077..fe4f46724b 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -413,6 +413,9 @@ enum mlx5_feature_name {\n #define IPPROTO_MPLS 137\n #endif\n \n+#define MLX5_IPV6_HDR_ECN_MASK 0x3\n+#define MLX5_IPV6_HDR_DSCP_SHIFT 2\n+\n /* UDP port number for MPLS */\n #define MLX5_UDP_PORT_MPLS 6635\n \ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 97f55003c3..ecf86d861d 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -253,6 +253,11 @@ struct field_modify_info modify_ipv6[] = {\n \t{0, 0, 0},\n };\n \n+struct field_modify_info modify_ipv6_traffic_class[] = {\n+\t{1, 0, MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS},\n+\t{0, 0, 0},\n+};\n+\n struct field_modify_info modify_udp[] = {\n \t{2, 0, MLX5_MODI_OUT_UDP_SPORT},\n \t{2, 2, MLX5_MODI_OUT_UDP_DPORT},\n@@ -1323,6 +1328,7 @@ static int\n flow_dv_convert_action_modify_ipv6_dscp\n \t\t\t(struct mlx5_flow_dv_modify_hdr_resource *resource,\n \t\t\t const struct rte_flow_action *action,\n+\t\t\t uint32_t ipv6_tc_off,\n \t\t\t struct rte_flow_error *error)\n {\n \tconst struct rte_flow_action_set_dscp *conf =\n@@ -1330,6 +1336,7 @@ flow_dv_convert_action_modify_ipv6_dscp\n \tstruct rte_flow_item item = { .type = RTE_FLOW_ITEM_TYPE_IPV6 };\n \tstruct rte_flow_item_ipv6 ipv6;\n \tstruct rte_flow_item_ipv6 ipv6_mask;\n+\tstruct field_modify_info *modify_info;\n \n \tmemset(&ipv6, 0, sizeof(ipv6));\n \tmemset(&ipv6_mask, 0, sizeof(ipv6_mask));\n@@ -1338,12 +1345,19 @@ flow_dv_convert_action_modify_ipv6_dscp\n \t * rdma-core only accept the DSCP bits byte aligned start from\n \t * bit 0 to 5 as to be compatible with IPv4. No need to shift the\n \t * bits in IPv6 case as rdma-core requires byte aligned value.\n+\t * IPV6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2\n+\t * bits left. Shift the mask left for IPV6 DSCP. Do it here because\n+\t * it's needed to distinguish DSCP from ECN in data field construct\n \t */\n-\tipv6.hdr.vtc_flow = conf->dscp;\n-\tipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> 22;\n+\tipv6.hdr.vtc_flow = conf->dscp << ipv6_tc_off;\n+\tipv6_mask.hdr.vtc_flow = RTE_IPV6_HDR_DSCP_MASK >> (22 - ipv6_tc_off);\n \titem.spec = &ipv6;\n \titem.mask = &ipv6_mask;\n-\treturn flow_dv_convert_modify_action(&item, modify_ipv6, NULL, resource,\n+\tif (ipv6_tc_off)\n+\t\tmodify_info = modify_ipv6_traffic_class;\n+\telse\n+\t\tmodify_info = modify_ipv6;\n+\treturn flow_dv_convert_modify_action(&item, modify_info, NULL, resource,\n \t\t\t\t\t MLX5_MODIFICATION_TYPE_SET, error);\n }\n \n@@ -1576,6 +1590,12 @@ mlx5_modify_flex_item(const struct rte_eth_dev *dev,\n \t}\n }\n \n+static inline bool\n+mlx5_dv_modify_ipv6_traffic_class_supported(struct mlx5_priv *priv)\n+{\n+\treturn !priv->sh->ipv6_tc_fallback;\n+}\n+\n void\n mlx5_flow_field_id_to_modify_info\n \t\t(const struct rte_flow_action_modify_data *data,\n@@ -1731,9 +1751,20 @@ mlx5_flow_field_id_to_modify_info\n \t\tbreak;\n \tcase RTE_FLOW_FIELD_IPV6_DSCP:\n \t\tMLX5_ASSERT(data->offset + width <= 6);\n-\t\toff_be = 6 - (data->offset + width);\n-\t\tinfo[idx] = (struct field_modify_info){1, 0,\n-\t\t\t\t\tMLX5_MODI_OUT_IP_DSCP};\n+\t\t/*\n+\t\t * IPV6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2\n+\t\t * bits left. Shift the mask left for IPV6 DSCP. Do it here because\n+\t\t * it's needed to distinguish DSCP from ECN in data field construct\n+\t\t */\n+\t\tif (mlx5_dv_modify_ipv6_traffic_class_supported(priv)) {\n+\t\t\toff_be = 6 - (data->offset + width) + MLX5_IPV6_HDR_DSCP_SHIFT;\n+\t\t\tinfo[idx] = (struct field_modify_info){1, 0,\n+\t\t\t\t\t\tMLX5_MODI_OUT_IPV6_TRAFFIC_CLASS};\n+\t\t} else {\n+\t\t\toff_be = 6 - (data->offset + width);\n+\t\t\tinfo[idx] = (struct field_modify_info){1, 0,\n+\t\t\t\t\t\tMLX5_MODI_OUT_IP_DSCP};\n+\t\t}\n \t\tif (mask)\n \t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n \t\telse\n@@ -2029,7 +2060,6 @@ mlx5_flow_field_id_to_modify_info\n \t\t}\n \t\tbreak;\n \tcase RTE_FLOW_FIELD_IPV4_ECN:\n-\tcase RTE_FLOW_FIELD_IPV6_ECN:\n \t\tMLX5_ASSERT(data->offset + width <= 2);\n \t\toff_be = 2 - (data->offset + width);\n \t\tinfo[idx] = (struct field_modify_info){1, 0,\n@@ -2039,6 +2069,20 @@ mlx5_flow_field_id_to_modify_info\n \t\telse\n \t\t\tinfo[idx].offset = off_be;\n \t\tbreak;\n+\tcase RTE_FLOW_FIELD_IPV6_ECN:\n+\t\tMLX5_ASSERT(data->offset + width <= 2);\n+\t\toff_be = 2 - (data->offset + width);\n+\t\tif (mlx5_dv_modify_ipv6_traffic_class_supported(priv))\n+\t\t\tinfo[idx] = (struct field_modify_info){1, 0,\n+\t\t\t\t\t\tMLX5_MODI_OUT_IPV6_TRAFFIC_CLASS};\n+\t\telse\n+\t\t\tinfo[idx] = (struct field_modify_info){1, 0,\n+\t\t\t\t\t\tMLX5_MODI_OUT_IP_ECN};\n+\t\tif (mask)\n+\t\t\tmask[idx] = flow_modify_info_mask_8(width, off_be);\n+\t\telse\n+\t\t\tinfo[idx].offset = off_be;\n+\t\tbreak;\n \tcase RTE_FLOW_FIELD_GTP_PSC_QFI:\n \t\tMLX5_ASSERT(data->offset + width <= 8);\n \t\toff_be = data->offset + 8;\n@@ -2161,7 +2205,7 @@ flow_dv_convert_action_modify_field\n \tstruct field_modify_info dcopy[MLX5_ACT_MAX_MOD_FIELDS] = {\n \t\t\t\t\t\t\t\t{0, 0, 0} };\n \tuint32_t mask[MLX5_ACT_MAX_MOD_FIELDS] = {0, 0, 0, 0, 0};\n-\tuint32_t type, meta = 0;\n+\tuint32_t type, meta = 0, dscp = 0;\n \n \tif (conf->src.field == RTE_FLOW_FIELD_POINTER ||\n \t conf->src.field == RTE_FLOW_FIELD_VALUE) {\n@@ -2181,6 +2225,17 @@ flow_dv_convert_action_modify_field\n \t\t\tmeta = rte_cpu_to_be_32(meta);\n \t\t\titem.spec = &meta;\n \t\t}\n+\t\tif (mlx5_dv_modify_ipv6_traffic_class_supported(dev->data->dev_private) &&\n+\t\t conf->dst.field == RTE_FLOW_FIELD_IPV6_DSCP &&\n+\t\t !(mask[0] & MLX5_IPV6_HDR_ECN_MASK)) {\n+\t\t\tdscp = *(const unaligned_uint32_t *)item.spec;\n+\t\t\t/*\n+\t\t\t * IPV6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2\n+\t\t\t * bits left. Shift the data left for IPV6 DSCP\n+\t\t\t */\n+\t\t\tdscp <<= MLX5_IPV6_HDR_DSCP_SHIFT;\n+\t\t\titem.spec = &dscp;\n+\t\t}\n \t} else {\n \t\ttype = MLX5_MODIFICATION_TYPE_COPY;\n \t\t/** For COPY fill the destination field (dcopy) without mask. */\n@@ -14385,6 +14440,7 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \tstruct mlx5_flow_sub_actions_list *sample_act;\n \tuint32_t sample_act_pos = UINT32_MAX;\n \tuint32_t age_act_pos = UINT32_MAX;\n+\tuint32_t ipv6_tc_off = 0;\n \tuint32_t num_of_dest = 0;\n \tint tmp_actions_n = 0;\n \tuint32_t table;\n@@ -14941,8 +14997,12 @@ flow_dv_translate(struct rte_eth_dev *dev,\n \t\t\taction_flags |= MLX5_FLOW_ACTION_SET_IPV4_DSCP;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_SET_IPV6_DSCP:\n+\t\t\tif (mlx5_dv_modify_ipv6_traffic_class_supported(priv))\n+\t\t\t\tipv6_tc_off = MLX5_IPV6_HDR_DSCP_SHIFT;\n+\t\t\telse\n+\t\t\t\tipv6_tc_off = 0;\n \t\t\tif (flow_dv_convert_action_modify_ipv6_dscp(mhdr_res,\n-\t\t\t\t\t\t\t actions, error))\n+\t\t\t\t\t\t\t actions, ipv6_tc_off, error))\n \t\t\t\treturn -rte_errno;\n \t\t\taction_flags |= MLX5_FLOW_ACTION_SET_IPV6_DSCP;\n \t\t\tbreak;\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex c4a90a3690..504a250e44 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2862,6 +2862,13 @@ flow_hw_modify_field_construct(struct mlx5_hw_q_job *job,\n \t\t}\n \t\toff_b = rte_bsf32(mask);\n \t\tdata = flow_dv_fetch_field(values + field->offset, field->size);\n+\t\t/*\n+\t\t * IPV6 DSCP uses OUT_IPV6_TRAFFIC_CLASS as ID but it starts from 2\n+\t\t * bits left. Shift the data left for IPV6 DSCP\n+\t\t */\n+\t\tif (field->id == MLX5_MODI_OUT_IPV6_TRAFFIC_CLASS &&\n+\t\t !(mask & MLX5_IPV6_HDR_ECN_MASK))\n+\t\t\tdata <<= MLX5_IPV6_HDR_DSCP_SHIFT;\n \t\tdata = (data & mask) >> off_b;\n \t\tjob->mhdr_cmd[i++].data1 = rte_cpu_to_be_32(data);\n \t\t++field;\n", "prefixes": [ "V1", "2/2" ] }