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GET /api/patches/135853/?format=api
{ "id": 135853, "url": "http://patchwork.dpdk.org/api/patches/135853/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240112080210.1288356-6-gavinl@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240112080210.1288356-6-gavinl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240112080210.1288356-6-gavinl@nvidia.com", "date": "2024-01-12T08:02:10", "name": "[V1,5/5] net/mlx5/hws: support VXLAN-GPE matching", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "649529190c37dab75947f9e9f067e8f7eb22059c", "submitter": { "id": 3217, "url": "http://patchwork.dpdk.org/api/people/3217/?format=api", "name": "Gavin Li", "email": "gavinl@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240112080210.1288356-6-gavinl@nvidia.com/mbox/", "series": [ { "id": 30788, "url": "http://patchwork.dpdk.org/api/series/30788/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=30788", "date": "2024-01-12T08:02:06", "name": "support VXLAN-GPE header fields(flags, rsvd0 and rsvd1) matching", "version": 1, "mbox": "http://patchwork.dpdk.org/series/30788/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/135853/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/135853/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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b=TJ48McmQ1Dp3ndDHlyI6zQKHXR46NK6Ul6S5lHO8L76YF3ow2cMN9z0ThHEKjaZGHduNknuxgLFXVUyoBi8hY5BrimYpCL+33DoIA14JdQBVjVUE2D1XCt/TYUTNE9gzliBLeiAaUxUx8CtisT/F7IwX0tgoRUPIDcabBOV2KYGlmFbK9jpgDSlBWBBqVtUt4wJVtYt0dbhdbeo8yq7qPzWkxpovAjyyU0o3dDMpuChm+FCGTCMv1n8sWXTrT6knczXHH6qd6degryvp9k+/w14rL5wUMUG8UeeaBvSVdZ+ABrWMTrHOOc/ypWV9aMy7KGOQwgx4R0iw52fUjl4urA==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Gavin Li <gavinl@nvidia.com>", "To": "<dev@dpdk.org>, <thomas@monjalon.net>, <orika@nvidia.com>,\n <aman.deep.singh@intel.com>, <yuying.zhang@intel.com>,\n <dsosnowski@nvidia.com>, <viacheslavo@nvidia.com>, <suanmingm@nvidia.com>,\n <matan@nvidia.com>", "CC": "<jiaweiw@nvidia.com>, <rasland@nvidia.com>, Itamar Gozlan\n <igozlan@nvidia.com>", "Subject": "[V1 5/5] net/mlx5/hws: support VXLAN-GPE matching", "Date": "Fri, 12 Jan 2024 10:02:10 +0200", "Message-ID": "<20240112080210.1288356-6-gavinl@nvidia.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20240112080210.1288356-1-gavinl@nvidia.com>", "References": "<20240112080210.1288356-1-gavinl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SJ5PEPF000001D0:EE_|LV3PR12MB9265:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b2347234-5658-42cb-9c31-08dc1344ec55", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", 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SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(376002)(39860400002)(396003)(136003)(346002)(230922051799003)(82310400011)(451199024)(186009)(64100799003)(1800799012)(46966006)(40470700004)(36840700001)(70586007)(70206006)(110136005)(36756003)(316002)(54906003)(6636002)(7696005)(6666004)(478600001)(41300700001)(4326008)(8676002)(8936002)(2906002)(5660300002)(86362001)(47076005)(83380400001)(7636003)(356005)(107886003)(82740400003)(55016003)(40480700001)(40460700003)(2616005)(1076003)(426003)(16526019)(336012)(6286002)(36860700001)(26005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "12 Jan 2024 08:03:12.2255 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b2347234-5658-42cb-9c31-08dc1344ec55", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n SJ5PEPF000001D0.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV3PR12MB9265", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add support for matching VXLAN-GPE tunnel header.\n\nSigned-off-by: Gavin Li <gavinl@nvidia.com>\nAcked-by: Itamar Gozlan <igozlan@nvidia.com>\nAcked-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n doc/guides/rel_notes/release_24_03.rst | 6 ++\n drivers/net/mlx5/hws/mlx5dr_definer.c | 117 +++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 13 +++\n drivers/net/mlx5/mlx5_flow_hw.c | 1 +\n 4 files changed, 137 insertions(+)", "diff": "diff --git a/doc/guides/rel_notes/release_24_03.rst b/doc/guides/rel_notes/release_24_03.rst\nindex 2c0e2930cc..d5e1b1ad37 100644\n--- a/doc/guides/rel_notes/release_24_03.rst\n+++ b/doc/guides/rel_notes/release_24_03.rst\n@@ -59,6 +59,12 @@ New Features\n \n * Added support for accumulating from src field to dst field.\n \n+ * Added support for VXLAN-GPE flags/rsvd0/rsvd fields matching in DV flow\n+ engine (``dv_flow_en`` = 1).\n+\n+ * Added support for VXLAN-GPE matching in HW Steering flow engine\n+ (``dv_flow_en`` = 2).\n+\n \n Removed Items\n -------------\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 0b60479406..8958049c8f 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -9,6 +9,7 @@\n #define ETH_TYPE_IPV4_VXLAN\t0x0800\n #define ETH_TYPE_IPV6_VXLAN\t0x86DD\n #define ETH_VXLAN_DEFAULT_PORT\t4789\n+#define ETH_VXLAN_GPE_DEFAULT_PORT\t4790\n #define IP_UDP_PORT_MPLS\t6635\n #define UDP_ROCEV2_PORT\t4791\n #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)\n@@ -167,6 +168,10 @@ struct mlx5dr_definer_conv_data {\n \tX(SET,\t\tgtp_ext_hdr_qfi,\tv->hdr.qfi,\t\trte_flow_item_gtp_psc) \\\n \tX(SET,\t\tvxlan_flags,\t\tv->flags,\t\trte_flow_item_vxlan) \\\n \tX(SET,\t\tvxlan_udp_port,\t\tETH_VXLAN_DEFAULT_PORT,\trte_flow_item_vxlan) \\\n+\tX(SET,\t\tvxlan_gpe_udp_port,\tETH_VXLAN_GPE_DEFAULT_PORT,\trte_flow_item_vxlan_gpe) \\\n+\tX(SET,\t\tvxlan_gpe_flags,\tv->flags,\t\trte_flow_item_vxlan_gpe) \\\n+\tX(SET,\t\tvxlan_gpe_protocol,\tv->protocol,\t\trte_flow_item_vxlan_gpe) \\\n+\tX(SET,\t\tvxlan_gpe_rsvd1,\tv->rsvd1,\t\trte_flow_item_vxlan_gpe) \\\n \tX(SET,\t\tmpls_udp_port,\t\tIP_UDP_PORT_MPLS,\trte_flow_item_mpls) \\\n \tX(SET,\t\tsource_qp,\t\tv->queue,\t\tmlx5_rte_flow_item_sq) \\\n \tX(SET,\t\ttag,\t\t\tv->data,\t\trte_flow_item_tag) \\\n@@ -691,6 +696,28 @@ mlx5dr_definer_ib_l4_qp_set(struct mlx5dr_definer_fc *fc,\n \tmemcpy(tag + fc->byte_off, &v->hdr.dst_qp, sizeof(v->hdr.dst_qp));\n }\n \n+static void\n+mlx5dr_definer_vxlan_gpe_vni_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_vxlan_gpe *v = item_spec;\n+\n+\tmemcpy(tag + fc->byte_off, v->vni, sizeof(v->vni));\n+}\n+\n+static void\n+mlx5dr_definer_vxlan_gpe_rsvd0_set(struct mlx5dr_definer_fc *fc,\n+\t\t\t\t const void *item_spec,\n+\t\t\t\t uint8_t *tag)\n+{\n+\tconst struct rte_flow_item_vxlan_gpe *v = item_spec;\n+\tuint16_t rsvd0;\n+\n+\trsvd0 = (v->rsvd0[0] << 8 | v->rsvd0[1]);\n+\tDR_SET(tag, rsvd0, fc->byte_off, fc->bit_off, fc->bit_mask);\n+}\n+\n static int\n mlx5dr_definer_conv_item_eth(struct mlx5dr_definer_conv_data *cd,\n \t\t\t struct rte_flow_item *item,\n@@ -2385,6 +2412,92 @@ mlx5dr_definer_conv_item_ib_l4(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_vxlan_gpe(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t\t struct rte_flow_item *item,\n+\t\t\t\t int item_idx)\n+{\n+\tconst struct rte_flow_item_vxlan_gpe *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\tif (inner) {\n+\t\tDR_LOG(ERR, \"Inner VXLAN GPE item not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\t/* In order to match on VXLAN GPE we must match on ip_protocol and l4_dport */\n+\tif (!cd->relaxed) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_udp_protocol_set;\n+\t\t\tDR_CALC_SET(fc, eth_l2, l4_type_bwc, inner);\n+\t\t}\n+\n+\t\tfc = &cd->fc[DR_CALC_FNAME(L4_DPORT, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_udp_port_set;\n+\t\t\tDR_CALC_SET(fc, eth_l4, destination_port, inner);\n+\t\t}\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->flags) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_flags_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, flags);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, flags);\n+\t}\n+\n+\tif (!is_mem_zero(m->rsvd0, 2)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd0_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd0);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd0);\n+\t}\n+\n+\tif (m->protocol) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_protocol_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->byte_off += MLX5_BYTE_OFF(header_vxlan_gpe, protocol);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, protocol);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, protocol);\n+\t}\n+\n+\tif (!is_mem_zero(m->vni, 3)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_vni_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, vni);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, vni);\n+\t}\n+\n+\tif (m->rsvd1) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_vxlan_gpe_rsvd1_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_1);\n+\t\tfc->bit_mask = __mlx5_mask(header_vxlan_gpe, rsvd1);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_vxlan_gpe, rsvd1);\n+\t}\n+\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\t\tstruct mlx5dr_match_template *mt,\n@@ -2537,6 +2650,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tret = mlx5dr_definer_conv_item_ptype(&cd, items, i);\n \t\t\titem_flags |= MLX5_FLOW_ITEM_PTYPE;\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN_GPE:\n+\t\t\tret = mlx5dr_definer_conv_item_vxlan_gpe(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_VXLAN_GPE;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\trte_errno = ENOTSUP;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex 6f1c99e37a..3dc5f4438d 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -91,6 +91,11 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_VPORT_REG_C_0,\n \tMLX5DR_DEFINER_FNAME_VXLAN_FLAGS,\n \tMLX5DR_DEFINER_FNAME_VXLAN_VNI,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_FLAGS,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD0,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_PROTO,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_VNI,\n+\tMLX5DR_DEFINER_FNAME_VXLAN_GPE_RSVD1,\n \tMLX5DR_DEFINER_FNAME_SOURCE_QP,\n \tMLX5DR_DEFINER_FNAME_REG_0,\n \tMLX5DR_DEFINER_FNAME_REG_1,\n@@ -593,6 +598,14 @@ struct mlx5_ifc_header_vxlan_bits {\n \tu8 reserved2[0x8];\n };\n \n+struct mlx5_ifc_header_vxlan_gpe_bits {\n+\tu8 flags[0x8];\n+\tu8 rsvd0[0x10];\n+\tu8 protocol[0x8];\n+\tu8 vni[0x18];\n+\tu8 rsvd1[0x8];\n+};\n+\n struct mlx5_ifc_header_gre_bits {\n \tunion {\n \t\tu8 c_rsvd0_ver[0x10];\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex c4a90a3690..6d8f4f8f8b 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -6827,6 +6827,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP:\n \t\tcase RTE_FLOW_ITEM_TYPE_GTP_PSC:\n \t\tcase RTE_FLOW_ITEM_TYPE_VXLAN:\n+\t\tcase RTE_FLOW_ITEM_TYPE_VXLAN_GPE:\n \t\tcase RTE_FLOW_ITEM_TYPE_MPLS:\n \t\tcase MLX5_RTE_FLOW_ITEM_TYPE_SQ:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE:\n", "prefixes": [ "V1", "5/5" ] }