Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/136625/?format=api
{ "id": 136625, "url": "http://patchwork.dpdk.org/api/patches/136625/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240213095038.451299-3-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240213095038.451299-3-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240213095038.451299-3-igozlan@nvidia.com", "date": "2024-02-13T09:50:31", "name": "[3/9] net/mlx5/hws: add support for resizable matchers", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9b4eddbd2fe54cc822477e0d73eae1eae1e4c0c2", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240213095038.451299-3-igozlan@nvidia.com/mbox/", "series": [ { "id": 31082, "url": "http://patchwork.dpdk.org/api/series/31082/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31082", "date": "2024-02-13T09:50:29", "name": "[1/9] net/mlx5/hws: skip RTE item when inserting rules by index", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31082/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/136625/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/136625/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BE31E43913;\n\tTue, 13 Feb 2024 10:51:19 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 5651541132;\n\tTue, 13 Feb 2024 10:51:13 +0100 (CET)", "from NAM04-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam04on2068.outbound.protection.outlook.com [40.107.101.68])\n by mails.dpdk.org (Postfix) with ESMTP id 23AA041109\n for <dev@dpdk.org>; Tue, 13 Feb 2024 10:51:11 +0100 (CET)", "from CH2PR19CA0025.namprd19.prod.outlook.com (2603:10b6:610:4d::35)\n by DM4PR12MB6352.namprd12.prod.outlook.com (2603:10b6:8:a0::14) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7292.24; Tue, 13 Feb\n 2024 09:51:06 +0000", "from CH2PEPF0000009A.namprd02.prod.outlook.com\n (2603:10b6:610:4d:cafe::e2) by CH2PR19CA0025.outlook.office365.com\n (2603:10b6:610:4d::35) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7270.39 via Frontend\n Transport; Tue, 13 Feb 2024 09:51:06 +0000", "from mail.nvidia.com (216.228.117.160) by\n CH2PEPF0000009A.mail.protection.outlook.com (10.167.244.22) with Microsoft\n SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.20.7292.25 via Frontend Transport; Tue, 13 Feb 2024 09:51:06 +0000", "from rnnvmail203.nvidia.com (10.129.68.9) by mail.nvidia.com\n (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 13 Feb\n 2024 01:50:57 -0800", "from rnnvmail203.nvidia.com (10.129.68.9) by rnnvmail203.nvidia.com\n (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41; Tue, 13 Feb\n 2024 01:50:56 -0800", "from nvidia.com (10.127.8.12) by mail.nvidia.com (10.129.68.9) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.41 via Frontend\n Transport; Tue, 13 Feb 2024 01:50:54 -0800" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=gHug633ixVlN7GYpHhSY3pP2h2CwFPbus5UEt76daguZ9t57Cfh0i2+FxgvDPwE9Eh9dOk6JcxquIYg6B0woeP9drLJQy0GAIOQfbm274VfYo1L3EyN1jEywsV+BjjceDzZ8+qQtTziBzSqBgZexjEESqqcm7AHwTlAbMBK5wKC1rc8ELsRTq5dAttX0aoEKpysAjmNLav2PngQRsgY5p9ovyrwtxSR26afTZr3TmrTufNGCXOIXXgm5+4Eb6keriFpjQcwKtA0skrC/L5+qpcscAkZDVWtSX4Kt3OTCTcGT49rBfL/FMBSpeXifIXz4JJxvITze8ViNqC+kehk3Lw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=h/wMguNV4pFqN3D8PoSbiaHy+NECtGBaW6PqKsgSNSw=;\n b=Su1hlk73yrEwA8vVcs0/e3l96xh2ywzOvqIJpQABzeAX5zY3a8b1l5490DQAPHlCrvqMNRzTbIR3YV936RCAUOWjQEU+2VbH7dIl7Kv7XnaDyR6LLOodY32laMxuwe/5AH7ZYc79N8p45qlgFgaMy7gMIPVjOflQcfAjTIGJeTxzWbBMMMc0rIMxkXF90suKe/h1le8LWjNXfVK2FpRGrraj09RQOrKa3qj0m84oaym+9rxA2HzCLrO50G4ukgjsvv7j3bJIYLvUPQzu3j+gAThwvzNYiJ5kMDn18vge+EFHz8wkV5HSKJHD2sHA/nTTZek6+Gxg1tgU/htw1q4eNA==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.117.160) smtp.rcpttodomain=monjalon.net smtp.mailfrom=nvidia.com;\n dmarc=pass (p=reject sp=reject pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none (0)", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=h/wMguNV4pFqN3D8PoSbiaHy+NECtGBaW6PqKsgSNSw=;\n b=UQ2NA5rXbCrhKs6IcrTMikt23YU57BHGkTYw+5jLLws/e8TvhW9GWyPm1FP+mEZiDladN+mBtizBUwaVaNbSACSGHXZB3+BJWzi6IQwE0T0px24yojKFJXjc6Tm1zi5Zpt4NSx6VYn1R9aB7/jtiSp39e/6uIjT8qSh+HZAzxb12O92N5kY+PEAsBdHoMrelK0pccEOmBzMM/TvnlzUrwpDFyr8HvSlTy8rJkqplJ5gQHVL+MGcRAs8cLws8tiApoSwl1eG8h80SRD4Ce9gSQvysAS0oKI95VfVur3Rw2pi+ab01uPyeZtsXalbwX3pFst4PhnTdIS7rK5VZqm4IeQ==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.117.160)\n smtp.mailfrom=nvidia.com;\n dkim=none (message not signed)\n header.d=none;dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.117.160 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<igozlan@nvidia.com>, <erezsh@nvidia.com>, <hamdani@nvidia.com>,\n <kliteyn@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[PATCH 3/9] net/mlx5/hws: add support for resizable matchers", "Date": "Tue, 13 Feb 2024 11:50:31 +0200", "Message-ID": "<20240213095038.451299-3-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240213095038.451299-1-igozlan@nvidia.com>", "References": "<20240213095038.451299-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CH2PEPF0000009A:EE_|DM4PR12MB6352:EE_", "X-MS-Office365-Filtering-Correlation-Id": "0d913f21-b118-4196-cc6c-08dc2c794c82", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Mq4O0F4AIe/gRiwLHLS8lcFJnw0m6AwawL4ybXzacI6zDoundghr8cOTVTEqoWdlJCTSFgX90yGzLGTK7H61DrZD00pVOtTM8lMzoTEZyPxIIFFleNFDQjAXtyjSvVTiiGpXquAEW3u8wysQjWSaijzBEMp0vcuja027lcIfRBegCNS6jXggGeYRo86VH6Mig3ljP081oA/pcGrx9ZElsHHCCbEmQNANsoKbzSIOtXFbhaybpSA4qrtNTtyqZcZMRbkpSPZB8ZCp7AEiKfoEqM5AoWKGWIRXqKzj90Nol1akutuFXuBhkUgSKb1xDT7lr/DXfy9fbzyFGrRPJtwTuB/YjMVd9y9pjqK8Tpcw8RNXD33O/FNhn9F7VnrXsI4nR3/BB6bqaIMs0lJDDuvBsIcr+AmcOf8xf1U7MYOijk3rr+ChejE7g2ZCfZ/2U1+q8ylg/p238HzvsyaWcrqruxcF7UxGwPlyUcBsrYtKr1UwDnJcNOp4DCi8/1TMfst29j23akCv4u4+h8HOseFko56mrefGLw+IAztStPCZC9XFsO5ylaXMblGJRUHldWc8/hhXOC6xrVLuCZmXqUheUT7wSuNJ+tk+KYxaAGRuoQKKKgBt2si8pgr3i1xxmTFJVR0S0zLqipWd4tdt3atAYQ==", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(346002)(396003)(376002)(136003)(39860400002)(230922051799003)(64100799003)(186009)(82310400011)(1800799012)(451199024)(36840700001)(46966006)(40470700004)(478600001)(41300700001)(55016003)(5660300002)(8936002)(8676002)(4326008)(30864003)(2906002)(70586007)(6636002)(110136005)(6666004)(6286002)(316002)(83380400001)(7696005)(26005)(336012)(426003)(82740400003)(7636003)(356005)(86362001)(70206006)(1076003)(921011)(36756003)(2616005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "13 Feb 2024 09:51:06.4510 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 0d913f21-b118-4196-cc6c-08dc2c794c82", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CH2PEPF0000009A.namprd02.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM4PR12MB6352", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Yevgeny Kliteynik <kliteyn@nvidia.com>\n\nAdd support for matcher resize with the following new API calls:\n - mlx5dr_matcher_resize_set_target\n - mlx5dr_matcher_resize_rule_move\n\nThe first function links two matchers and allows moving rules from src\nmatcher to dst matcher. Both matchers should have the same characteristics\n(e.g. same mt, same at). It is the user's responsibility to make sure that\nthe dst matcher has enough space for the moved rules.\nAfter this function, the user can move rules from src into dst matcher,\nand he is no longer allowed to insert rules to the src matcher.\n\nThe second function is used to move the rule from matcher that is being\nresized to a bigger matcher. Moving a single rule includes creating a new\nrule in the destination matcher, and deleting the rule from the source\nmatcher. This operation creates a single completion.\n\nSigned-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr.h | 39 ++++\n drivers/net/mlx5/hws/mlx5dr_definer.c | 5 +-\n drivers/net/mlx5/hws/mlx5dr_definer.h | 3 +\n drivers/net/mlx5/hws/mlx5dr_matcher.c | 181 +++++++++++++++-\n drivers/net/mlx5/hws/mlx5dr_matcher.h | 21 ++\n drivers/net/mlx5/hws/mlx5dr_rule.c | 290 ++++++++++++++++++++++----\n drivers/net/mlx5/hws/mlx5dr_rule.h | 30 ++-\n drivers/net/mlx5/hws/mlx5dr_send.c | 45 ++++\n 8 files changed, 573 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr.h b/drivers/net/mlx5/hws/mlx5dr.h\nindex d88f73ab57..9d8f8e13dc 100644\n--- a/drivers/net/mlx5/hws/mlx5dr.h\n+++ b/drivers/net/mlx5/hws/mlx5dr.h\n@@ -139,6 +139,8 @@ struct mlx5dr_matcher_attr {\n \t/* Define the insertion and distribution modes for this matcher */\n \tenum mlx5dr_matcher_insert_mode insert_mode;\n \tenum mlx5dr_matcher_distribute_mode distribute_mode;\n+\t/* Define whether the created matcher supports resizing into a bigger matcher */\n+\tbool resizable;\n \tunion {\n \t\tstruct {\n \t\t\tuint8_t sz_row_log;\n@@ -419,6 +421,43 @@ int mlx5dr_matcher_destroy(struct mlx5dr_matcher *matcher);\n int mlx5dr_matcher_attach_at(struct mlx5dr_matcher *matcher,\n \t\t\t struct mlx5dr_action_template *at);\n \n+/* Link two matchers and enable moving rules from src matcher to dst matcher.\n+ * Both matchers must be in the same table type, must be created with 'resizable'\n+ * property, and should have the same characteristics (e.g. same mt, same at).\n+ *\n+ * It is the user's responsibility to make sure that the dst matcher\n+ * was allocated with the appropriate size.\n+ *\n+ * Once the function is completed, the user is:\n+ * - allowed to move rules from src into dst matcher\n+ * - no longer allowed to insert rules to the src matcher\n+ *\n+ * The user is always allowed to insert rules to the dst matcher and\n+ * to delete rules from any matcher.\n+ *\n+ * @param[in] src_matcher\n+ *\tsource matcher for moving rules from\n+ * @param[in] dst_matcher\n+ *\tdestination matcher for moving rules to\n+ * @return zero on successful move, non zero otherwise.\n+ */\n+int mlx5dr_matcher_resize_set_target(struct mlx5dr_matcher *src_matcher,\n+\t\t\t\t struct mlx5dr_matcher *dst_matcher);\n+\n+/* Enqueue moving rule operation: moving rule from src matcher to a dst matcher\n+ *\n+ * @param[in] src_matcher\n+ *\tmatcher that the rule belongs to\n+ * @param[in] rule\n+ *\tthe rule to move\n+ * @param[in] attr\n+ *\trule attributes\n+ * @return zero on success, non zero otherwise.\n+ */\n+int mlx5dr_matcher_resize_rule_move(struct mlx5dr_matcher *src_matcher,\n+\t\t\t\t struct mlx5dr_rule *rule,\n+\t\t\t\t struct mlx5dr_rule_attr *attr);\n+\n /* Get the size of the rule handle (mlx5dr_rule) to be used on rule creation.\n *\n * @return size in bytes of rule handle struct.\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 8b8757ecac..e564062313 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -3296,9 +3296,8 @@ int mlx5dr_definer_get_id(struct mlx5dr_definer *definer)\n \treturn definer->obj->id;\n }\n \n-static int\n-mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,\n-\t\t struct mlx5dr_definer *definer_b)\n+int mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,\n+\t\t\t struct mlx5dr_definer *definer_b)\n {\n \tint i;\n \ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex ced9d9da13..71cc0e94de 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -733,4 +733,7 @@ int mlx5dr_definer_init_cache(struct mlx5dr_definer_cache **cache);\n \n void mlx5dr_definer_uninit_cache(struct mlx5dr_definer_cache *cache);\n \n+int mlx5dr_definer_compare(struct mlx5dr_definer *definer_a,\n+\t\t\t struct mlx5dr_definer *definer_b);\n+\n #endif\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.c b/drivers/net/mlx5/hws/mlx5dr_matcher.c\nindex 4ea161eae6..0d5c462734 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.c\n@@ -704,6 +704,65 @@ static int mlx5dr_matcher_check_and_process_at(struct mlx5dr_matcher *matcher,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_matcher_resize_init(struct mlx5dr_matcher *src_matcher)\n+{\n+\tstruct mlx5dr_matcher_resize_data *resize_data;\n+\n+\tresize_data = simple_calloc(1, sizeof(*resize_data));\n+\tif (!resize_data) {\n+\t\trte_errno = ENOMEM;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tresize_data->stc = src_matcher->action_ste.stc;\n+\tresize_data->action_ste_rtc_0 = src_matcher->action_ste.rtc_0;\n+\tresize_data->action_ste_rtc_1 = src_matcher->action_ste.rtc_1;\n+\tresize_data->action_ste_pool = src_matcher->action_ste.max_stes ?\n+\t\t\t\t src_matcher->action_ste.pool :\n+\t\t\t\t NULL;\n+\n+\t/* Place the new resized matcher on the dst matcher's list */\n+\tLIST_INSERT_HEAD(&src_matcher->resize_dst->resize_data,\n+\t\t\t resize_data, next);\n+\n+\t/* Move all the previous resized matchers to the dst matcher's list */\n+\twhile (!LIST_EMPTY(&src_matcher->resize_data)) {\n+\t\tresize_data = LIST_FIRST(&src_matcher->resize_data);\n+\t\tLIST_REMOVE(resize_data, next);\n+\t\tLIST_INSERT_HEAD(&src_matcher->resize_dst->resize_data,\n+\t\t\t\t resize_data, next);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void\n+mlx5dr_matcher_resize_uninit(struct mlx5dr_matcher *matcher)\n+{\n+\tstruct mlx5dr_matcher_resize_data *resize_data;\n+\n+\tif (!mlx5dr_matcher_is_resizable(matcher) ||\n+\t !matcher->action_ste.max_stes)\n+\t\treturn;\n+\n+\twhile (!LIST_EMPTY(&matcher->resize_data)) {\n+\t\tresize_data = LIST_FIRST(&matcher->resize_data);\n+\t\tLIST_REMOVE(resize_data, next);\n+\n+\t\tmlx5dr_action_free_single_stc(matcher->tbl->ctx,\n+\t\t\t\t\t matcher->tbl->type,\n+\t\t\t\t\t &resize_data->stc);\n+\n+\t\tif (matcher->tbl->type == MLX5DR_TABLE_TYPE_FDB)\n+\t\t\tmlx5dr_cmd_destroy_obj(resize_data->action_ste_rtc_1);\n+\t\tmlx5dr_cmd_destroy_obj(resize_data->action_ste_rtc_0);\n+\t\tif (resize_data->action_ste_pool)\n+\t\t\tmlx5dr_pool_destroy(resize_data->action_ste_pool);\n+\t\tsimple_free(resize_data);\n+\t}\n+}\n+\n static int mlx5dr_matcher_bind_at(struct mlx5dr_matcher *matcher)\n {\n \tbool is_jumbo = mlx5dr_matcher_mt_is_jumbo(matcher->mt);\n@@ -790,7 +849,9 @@ static void mlx5dr_matcher_unbind_at(struct mlx5dr_matcher *matcher)\n {\n \tstruct mlx5dr_table *tbl = matcher->tbl;\n \n-\tif (!matcher->action_ste.max_stes || matcher->flags & MLX5DR_MATCHER_FLAGS_COLLISION)\n+\tif (!matcher->action_ste.max_stes ||\n+\t matcher->flags & MLX5DR_MATCHER_FLAGS_COLLISION ||\n+\t mlx5dr_matcher_is_in_resize(matcher))\n \t\treturn;\n \n \tmlx5dr_action_free_single_stc(tbl->ctx, tbl->type, &matcher->action_ste.stc);\n@@ -947,6 +1008,10 @@ mlx5dr_matcher_process_attr(struct mlx5dr_cmd_query_caps *caps,\n \t\t\tDR_LOG(ERR, \"Root matcher does not support at attaching\");\n \t\t\tgoto not_supported;\n \t\t}\n+\t\tif (attr->resizable) {\n+\t\t\tDR_LOG(ERR, \"Root matcher does not support resizing\");\n+\t\t\tgoto not_supported;\n+\t\t}\n \t\treturn 0;\n \t}\n \n@@ -960,6 +1025,8 @@ mlx5dr_matcher_process_attr(struct mlx5dr_cmd_query_caps *caps,\n \t attr->insert_mode == MLX5DR_MATCHER_INSERT_BY_HASH)\n \t\tattr->table.sz_col_log = mlx5dr_matcher_rules_to_tbl_depth(attr->rule.num_log);\n \n+\tmatcher->flags |= attr->resizable ? MLX5DR_MATCHER_FLAGS_RESIZABLE : 0;\n+\n \treturn mlx5dr_matcher_check_attr_sz(caps, attr);\n \n not_supported:\n@@ -1018,6 +1085,7 @@ static int mlx5dr_matcher_create_and_connect(struct mlx5dr_matcher *matcher)\n \n static void mlx5dr_matcher_destroy_and_disconnect(struct mlx5dr_matcher *matcher)\n {\n+\tmlx5dr_matcher_resize_uninit(matcher);\n \tmlx5dr_matcher_disconnect(matcher);\n \tmlx5dr_matcher_create_uninit_shared(matcher);\n \tmlx5dr_matcher_destroy_rtc(matcher, DR_MATCHER_RTC_TYPE_MATCH);\n@@ -1452,3 +1520,114 @@ int mlx5dr_match_template_destroy(struct mlx5dr_match_template *mt)\n \tsimple_free(mt);\n \treturn 0;\n }\n+\n+static int mlx5dr_matcher_resize_precheck(struct mlx5dr_matcher *src_matcher,\n+\t\t\t\t\t struct mlx5dr_matcher *dst_matcher)\n+{\n+\tint i;\n+\n+\tif (mlx5dr_table_is_root(src_matcher->tbl) ||\n+\t mlx5dr_table_is_root(dst_matcher->tbl)) {\n+\t\tDR_LOG(ERR, \"Src/dst matcher belongs to root table - resize unsupported\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tif (src_matcher->tbl->type != dst_matcher->tbl->type) {\n+\t\tDR_LOG(ERR, \"Table type mismatch for src/dst matchers\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tif (mlx5dr_matcher_req_fw_wqe(src_matcher) ||\n+\t mlx5dr_matcher_req_fw_wqe(dst_matcher)) {\n+\t\tDR_LOG(ERR, \"Matchers require FW WQE - resize unsupported\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tif (!mlx5dr_matcher_is_resizable(src_matcher) ||\n+\t !mlx5dr_matcher_is_resizable(dst_matcher)) {\n+\t\tDR_LOG(ERR, \"Src/dst matcher is not resizable\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tif (mlx5dr_matcher_is_insert_by_idx(src_matcher) !=\n+\t mlx5dr_matcher_is_insert_by_idx(dst_matcher)) {\n+\t\tDR_LOG(ERR, \"Src/dst matchers insert mode mismatch\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tif (mlx5dr_matcher_is_in_resize(src_matcher) ||\n+\t mlx5dr_matcher_is_in_resize(dst_matcher)) {\n+\t\tDR_LOG(ERR, \"Src/dst matcher is already in resize\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\t/* Compare match templates - make sure the definers are equivalent */\n+\tif (src_matcher->num_of_mt != dst_matcher->num_of_mt) {\n+\t\tDR_LOG(ERR, \"Src/dst matcher match templates mismatch\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tif (src_matcher->action_ste.max_stes > dst_matcher->action_ste.max_stes) {\n+\t\tDR_LOG(ERR, \"Src/dst matcher max STEs mismatch\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tfor (i = 0; i < src_matcher->num_of_mt; i++) {\n+\t\tif (mlx5dr_definer_compare(src_matcher->mt[i].definer,\n+\t\t\t\t\t dst_matcher->mt[i].definer)) {\n+\t\t\tDR_LOG(ERR, \"Src/dst matcher definers mismatch\");\n+\t\t\tgoto out_einval;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+\n+out_einval:\n+\trte_errno = EINVAL;\n+\treturn rte_errno;\n+}\n+\n+int mlx5dr_matcher_resize_set_target(struct mlx5dr_matcher *src_matcher,\n+\t\t\t\t struct mlx5dr_matcher *dst_matcher)\n+{\n+\tint ret = 0;\n+\n+\tpthread_spin_lock(&src_matcher->tbl->ctx->ctrl_lock);\n+\n+\tif (mlx5dr_matcher_resize_precheck(src_matcher, dst_matcher)) {\n+\t\tret = -rte_errno;\n+\t\tgoto out;\n+\t}\n+\n+\tsrc_matcher->resize_dst = dst_matcher;\n+\n+\tif (mlx5dr_matcher_resize_init(src_matcher)) {\n+\t\tsrc_matcher->resize_dst = NULL;\n+\t\tret = -rte_errno;\n+\t}\n+\n+out:\n+\tpthread_spin_unlock(&src_matcher->tbl->ctx->ctrl_lock);\n+\treturn ret;\n+}\n+\n+int mlx5dr_matcher_resize_rule_move(struct mlx5dr_matcher *src_matcher,\n+\t\t\t\t struct mlx5dr_rule *rule,\n+\t\t\t\t struct mlx5dr_rule_attr *attr)\n+{\n+\tif (unlikely(!mlx5dr_matcher_is_in_resize(src_matcher))) {\n+\t\tDR_LOG(ERR, \"Matcher is not resizable or not in resize\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\tif (unlikely(src_matcher != rule->matcher)) {\n+\t\tDR_LOG(ERR, \"Rule doesn't belong to src matcher\");\n+\t\tgoto out_einval;\n+\t}\n+\n+\treturn mlx5dr_rule_move_hws_add(rule, attr);\n+\n+out_einval:\n+\trte_errno = EINVAL;\n+\treturn -rte_errno;\n+}\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_matcher.h b/drivers/net/mlx5/hws/mlx5dr_matcher.h\nindex 363a61fd41..0f2bf96e8b 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_matcher.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_matcher.h\n@@ -26,6 +26,7 @@ enum mlx5dr_matcher_flags {\n \tMLX5DR_MATCHER_FLAGS_RANGE_DEFINER\t= 1 << 0,\n \tMLX5DR_MATCHER_FLAGS_HASH_DEFINER\t= 1 << 1,\n \tMLX5DR_MATCHER_FLAGS_COLLISION\t\t= 1 << 2,\n+\tMLX5DR_MATCHER_FLAGS_RESIZABLE\t\t= 1 << 3,\n };\n \n struct mlx5dr_match_template {\n@@ -59,6 +60,14 @@ struct mlx5dr_matcher_action_ste {\n \tuint8_t max_stes;\n };\n \n+struct mlx5dr_matcher_resize_data {\n+\tstruct mlx5dr_pool_chunk stc;\n+\tstruct mlx5dr_devx_obj *action_ste_rtc_0;\n+\tstruct mlx5dr_devx_obj *action_ste_rtc_1;\n+\tstruct mlx5dr_pool *action_ste_pool;\n+\tLIST_ENTRY(mlx5dr_matcher_resize_data) next;\n+};\n+\n struct mlx5dr_matcher {\n \tstruct mlx5dr_table *tbl;\n \tstruct mlx5dr_matcher_attr attr;\n@@ -71,10 +80,12 @@ struct mlx5dr_matcher {\n \tuint8_t flags;\n \tstruct mlx5dr_devx_obj *end_ft;\n \tstruct mlx5dr_matcher *col_matcher;\n+\tstruct mlx5dr_matcher *resize_dst;\n \tstruct mlx5dr_matcher_match_ste match_ste;\n \tstruct mlx5dr_matcher_action_ste action_ste;\n \tstruct mlx5dr_definer *hash_definer;\n \tLIST_ENTRY(mlx5dr_matcher) next;\n+\tLIST_HEAD(resize_data_head, mlx5dr_matcher_resize_data) resize_data;\n };\n \n static inline bool\n@@ -89,6 +100,16 @@ mlx5dr_matcher_mt_is_range(struct mlx5dr_match_template *mt)\n \treturn (!!mt->range_definer);\n }\n \n+static inline bool mlx5dr_matcher_is_resizable(struct mlx5dr_matcher *matcher)\n+{\n+\treturn !!(matcher->flags & MLX5DR_MATCHER_FLAGS_RESIZABLE);\n+}\n+\n+static inline bool mlx5dr_matcher_is_in_resize(struct mlx5dr_matcher *matcher)\n+{\n+\treturn !!matcher->resize_dst;\n+}\n+\n static inline bool mlx5dr_matcher_req_fw_wqe(struct mlx5dr_matcher *matcher)\n {\n \t/* Currently HWS doesn't support hash different from match or range */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_rule.c b/drivers/net/mlx5/hws/mlx5dr_rule.c\nindex e39137a6ee..6bf087e187 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.c\n@@ -114,6 +114,23 @@ static void mlx5dr_rule_init_dep_wqe(struct mlx5dr_send_ring_dep_wqe *dep_wqe,\n \t}\n }\n \n+static void mlx5dr_rule_move_get_rtc(struct mlx5dr_rule *rule,\n+\t\t\t\t struct mlx5dr_send_ste_attr *ste_attr)\n+{\n+\tstruct mlx5dr_matcher *dst_matcher = rule->matcher->resize_dst;\n+\n+\tif (rule->resize_info->rtc_0) {\n+\t\tste_attr->rtc_0 = dst_matcher->match_ste.rtc_0->id;\n+\t\tste_attr->retry_rtc_0 = dst_matcher->col_matcher ?\n+\t\t\t\t\tdst_matcher->col_matcher->match_ste.rtc_0->id : 0;\n+\t}\n+\tif (rule->resize_info->rtc_1) {\n+\t\tste_attr->rtc_1 = dst_matcher->match_ste.rtc_1->id;\n+\t\tste_attr->retry_rtc_1 = dst_matcher->col_matcher ?\n+\t\t\t\t\tdst_matcher->col_matcher->match_ste.rtc_1->id : 0;\n+\t}\n+}\n+\n static void mlx5dr_rule_gen_comp(struct mlx5dr_send_engine *queue,\n \t\t\t\t struct mlx5dr_rule *rule,\n \t\t\t\t bool err,\n@@ -134,6 +151,34 @@ static void mlx5dr_rule_gen_comp(struct mlx5dr_send_engine *queue,\n \tmlx5dr_send_engine_gen_comp(queue, user_data, comp_status);\n }\n \n+static void\n+mlx5dr_rule_save_resize_info(struct mlx5dr_rule *rule,\n+\t\t\t struct mlx5dr_send_ste_attr *ste_attr)\n+{\n+\trule->resize_info = simple_calloc(1, sizeof(*rule->resize_info));\n+\tif (unlikely(!rule->resize_info)) {\n+\t\tassert(rule->resize_info);\n+\t\trte_errno = ENOMEM;\n+\t}\n+\n+\tmemcpy(rule->resize_info->ctrl_seg, ste_attr->wqe_ctrl,\n+\t sizeof(rule->resize_info->ctrl_seg));\n+\tmemcpy(rule->resize_info->data_seg, ste_attr->wqe_data,\n+\t sizeof(rule->resize_info->data_seg));\n+\n+\trule->resize_info->action_ste_pool = rule->matcher->action_ste.max_stes ?\n+\t\t\t\t\t rule->matcher->action_ste.pool :\n+\t\t\t\t\t NULL;\n+}\n+\n+static void mlx5dr_rule_clear_resize_info(struct mlx5dr_rule *rule)\n+{\n+\tif (rule->resize_info) {\n+\t\tsimple_free(rule->resize_info);\n+\t\trule->resize_info = NULL;\n+\t}\n+}\n+\n static void\n mlx5dr_rule_save_delete_info(struct mlx5dr_rule *rule,\n \t\t\t struct mlx5dr_send_ste_attr *ste_attr)\n@@ -161,17 +206,29 @@ mlx5dr_rule_save_delete_info(struct mlx5dr_rule *rule,\n \t\treturn;\n \t}\n \n-\tif (is_jumbo)\n-\t\tmemcpy(rule->tag.jumbo, ste_attr->wqe_data->jumbo, MLX5DR_JUMBO_TAG_SZ);\n-\telse\n-\t\tmemcpy(rule->tag.match, ste_attr->wqe_data->tag, MLX5DR_MATCH_TAG_SZ);\n+\tif (likely(!mlx5dr_matcher_is_resizable(rule->matcher))) {\n+\t\tif (is_jumbo)\n+\t\t\tmemcpy(&rule->tag.jumbo, ste_attr->wqe_data->action, MLX5DR_JUMBO_TAG_SZ);\n+\t\telse\n+\t\t\tmemcpy(&rule->tag.match, ste_attr->wqe_data->tag, MLX5DR_MATCH_TAG_SZ);\n+\t\treturn;\n+\t}\n+\n+\tmlx5dr_rule_save_resize_info(rule, ste_attr);\n }\n \n static void\n mlx5dr_rule_clear_delete_info(struct mlx5dr_rule *rule)\n {\n-\tif (unlikely(mlx5dr_matcher_req_fw_wqe(rule->matcher)))\n+\tif (unlikely(mlx5dr_matcher_req_fw_wqe(rule->matcher))) {\n \t\tsimple_free(rule->tag_ptr);\n+\t\treturn;\n+\t}\n+\n+\tif (unlikely(mlx5dr_matcher_is_resizable(rule->matcher))) {\n+\t\tmlx5dr_rule_clear_resize_info(rule);\n+\t\treturn;\n+\t}\n }\n \n static void\n@@ -188,8 +245,11 @@ mlx5dr_rule_load_delete_info(struct mlx5dr_rule *rule,\n \t\t\tste_attr->range_wqe_tag = &rule->tag_ptr[1];\n \t\t\tste_attr->send_attr.range_definer_id = rule->tag_ptr[1].reserved[1];\n \t\t}\n-\t} else {\n+\t} else if (likely(!mlx5dr_matcher_is_resizable(rule->matcher))) {\n \t\tste_attr->wqe_tag = &rule->tag;\n+\t} else {\n+\t\tste_attr->wqe_tag = (struct mlx5dr_rule_match_tag *)\n+\t\t\t&rule->resize_info->data_seg[MLX5DR_STE_CTRL_SZ];\n \t}\n }\n \n@@ -220,6 +280,7 @@ static int mlx5dr_rule_alloc_action_ste(struct mlx5dr_rule *rule,\n void mlx5dr_rule_free_action_ste_idx(struct mlx5dr_rule *rule)\n {\n \tstruct mlx5dr_matcher *matcher = rule->matcher;\n+\tstruct mlx5dr_pool *pool;\n \n \tif (rule->action_ste_idx > -1 &&\n \t !matcher->attr.optimize_using_rule_idx &&\n@@ -229,7 +290,11 @@ void mlx5dr_rule_free_action_ste_idx(struct mlx5dr_rule *rule)\n \t\t/* This release is safe only when the rule match part was deleted */\n \t\tste.order = rte_log2_u32(matcher->action_ste.max_stes);\n \t\tste.offset = rule->action_ste_idx;\n-\t\tmlx5dr_pool_chunk_free(matcher->action_ste.pool, &ste);\n+\n+\t\t/* Free the original action pool if rule was resized */\n+\t\tpool = mlx5dr_matcher_is_resizable(matcher) ? rule->resize_info->action_ste_pool :\n+\t\t\t\t\t\t\t matcher->action_ste.pool;\n+\t\tmlx5dr_pool_chunk_free(pool, &ste);\n \t}\n }\n \n@@ -266,6 +331,23 @@ static void mlx5dr_rule_create_init(struct mlx5dr_rule *rule,\n \tapply->require_dep = 0;\n }\n \n+static void mlx5dr_rule_move_init(struct mlx5dr_rule *rule,\n+\t\t\t\t struct mlx5dr_rule_attr *attr)\n+{\n+\t/* Save the old RTC IDs to be later used in match STE delete */\n+\trule->resize_info->rtc_0 = rule->rtc_0;\n+\trule->resize_info->rtc_1 = rule->rtc_1;\n+\trule->resize_info->rule_idx = attr->rule_idx;\n+\n+\trule->rtc_0 = 0;\n+\trule->rtc_1 = 0;\n+\n+\trule->pending_wqes = 0;\n+\trule->action_ste_idx = -1;\n+\trule->status = MLX5DR_RULE_STATUS_CREATING;\n+\trule->resize_info->state = MLX5DR_RULE_RESIZE_STATE_WRITING;\n+}\n+\n static int mlx5dr_rule_create_hws_fw_wqe(struct mlx5dr_rule *rule,\n \t\t\t\t\t struct mlx5dr_rule_attr *attr,\n \t\t\t\t\t uint8_t mt_idx,\n@@ -346,7 +428,9 @@ static int mlx5dr_rule_create_hws_fw_wqe(struct mlx5dr_rule *rule,\n \t/* Send WQEs to FW */\n \tmlx5dr_send_stes_fw(queue, &ste_attr);\n \n-\t/* Backup TAG on the rule for deletion */\n+\t/* Backup TAG on the rule for deletion, and save ctrl/data\n+\t * segments to be used when resizing the matcher.\n+\t */\n \tmlx5dr_rule_save_delete_info(rule, &ste_attr);\n \tmlx5dr_send_engine_inc_rule(queue);\n \n@@ -469,7 +553,9 @@ static int mlx5dr_rule_create_hws(struct mlx5dr_rule *rule,\n \t\tmlx5dr_send_ste(queue, &ste_attr);\n \t}\n \n-\t/* Backup TAG on the rule for deletion, only after insertion */\n+\t/* Backup TAG on the rule for deletion and resize info for\n+\t * moving rules to a new matcher, only after insertion.\n+\t */\n \tif (!is_update)\n \t\tmlx5dr_rule_save_delete_info(rule, &ste_attr);\n \n@@ -496,7 +582,7 @@ static void mlx5dr_rule_destroy_failed_hws(struct mlx5dr_rule *rule,\n \t/* Rule failed now we can safely release action STEs */\n \tmlx5dr_rule_free_action_ste_idx(rule);\n \n-\t/* Clear complex tag */\n+\t/* Clear complex tag or info that was saved for matcher resizing */\n \tmlx5dr_rule_clear_delete_info(rule);\n \n \t/* If a rule that was indicated as burst (need to trigger HW) has failed\n@@ -571,12 +657,12 @@ static int mlx5dr_rule_destroy_hws(struct mlx5dr_rule *rule,\n \n \tmlx5dr_rule_load_delete_info(rule, &ste_attr);\n \n-\tif (unlikely(fw_wqe)) {\n+\tif (unlikely(fw_wqe))\n \t\tmlx5dr_send_stes_fw(queue, &ste_attr);\n-\t\tmlx5dr_rule_clear_delete_info(rule);\n-\t} else {\n+\telse\n \t\tmlx5dr_send_ste(queue, &ste_attr);\n-\t}\n+\n+\tmlx5dr_rule_clear_delete_info(rule);\n \n \treturn 0;\n }\n@@ -664,9 +750,11 @@ static int mlx5dr_rule_destroy_root(struct mlx5dr_rule *rule,\n \treturn 0;\n }\n \n-static int mlx5dr_rule_enqueue_precheck(struct mlx5dr_context *ctx,\n+static int mlx5dr_rule_enqueue_precheck(struct mlx5dr_rule *rule,\n \t\t\t\t\tstruct mlx5dr_rule_attr *attr)\n {\n+\tstruct mlx5dr_context *ctx = rule->matcher->tbl->ctx;\n+\n \tif (unlikely(!attr->user_data)) {\n \t\trte_errno = EINVAL;\n \t\treturn rte_errno;\n@@ -681,6 +769,153 @@ static int mlx5dr_rule_enqueue_precheck(struct mlx5dr_context *ctx,\n \treturn 0;\n }\n \n+static int mlx5dr_rule_enqueue_precheck_move(struct mlx5dr_rule *rule,\n+\t\t\t\t\t struct mlx5dr_rule_attr *attr)\n+{\n+\tif (unlikely(rule->status != MLX5DR_RULE_STATUS_CREATED)) {\n+\t\trte_errno = EINVAL;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn mlx5dr_rule_enqueue_precheck(rule, attr);\n+}\n+\n+static int mlx5dr_rule_enqueue_precheck_create(struct mlx5dr_rule *rule,\n+\t\t\t\t\t struct mlx5dr_rule_attr *attr)\n+{\n+\tif (unlikely(mlx5dr_matcher_is_in_resize(rule->matcher))) {\n+\t\t/* Matcher in resize - new rules are not allowed */\n+\t\trte_errno = EAGAIN;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn mlx5dr_rule_enqueue_precheck(rule, attr);\n+}\n+\n+static int mlx5dr_rule_enqueue_precheck_update(struct mlx5dr_rule *rule,\n+\t\t\t\t\t struct mlx5dr_rule_attr *attr)\n+{\n+\tstruct mlx5dr_matcher *matcher = rule->matcher;\n+\n+\tif (unlikely((mlx5dr_table_is_root(matcher->tbl) ||\n+\t\t mlx5dr_matcher_req_fw_wqe(matcher)))) {\n+\t\tDR_LOG(ERR, \"Rule update is not supported on current matcher\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (unlikely(!matcher->attr.optimize_using_rule_idx &&\n+\t\t !mlx5dr_matcher_is_insert_by_idx(matcher))) {\n+\t\tDR_LOG(ERR, \"Rule update requires optimize by idx matcher\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (unlikely(mlx5dr_matcher_is_resizable(rule->matcher))) {\n+\t\tDR_LOG(ERR, \"Rule update is not supported on resizable matcher\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (unlikely(rule->status != MLX5DR_RULE_STATUS_CREATED)) {\n+\t\tDR_LOG(ERR, \"Current rule status does not allow update\");\n+\t\trte_errno = EBUSY;\n+\t\treturn rte_errno;\n+\t}\n+\n+\treturn mlx5dr_rule_enqueue_precheck_create(rule, attr);\n+}\n+\n+int mlx5dr_rule_move_hws_remove(struct mlx5dr_rule *rule,\n+\t\t\t\tvoid *queue_ptr,\n+\t\t\t\tvoid *user_data)\n+{\n+\tbool is_jumbo = mlx5dr_matcher_mt_is_jumbo(rule->matcher->mt);\n+\tstruct mlx5dr_wqe_gta_ctrl_seg empty_wqe_ctrl = {0};\n+\tstruct mlx5dr_matcher *matcher = rule->matcher;\n+\tstruct mlx5dr_send_engine *queue = queue_ptr;\n+\tstruct mlx5dr_send_ste_attr ste_attr = {0};\n+\n+\t/* Send dependent WQEs */\n+\tmlx5dr_send_all_dep_wqe(queue);\n+\n+\trule->resize_info->state = MLX5DR_RULE_RESIZE_STATE_DELETING;\n+\n+\tste_attr.send_attr.fence = 0;\n+\tste_attr.send_attr.opmod = MLX5DR_WQE_GTA_OPMOD_STE;\n+\tste_attr.send_attr.opcode = MLX5DR_WQE_OPCODE_TBL_ACCESS;\n+\tste_attr.send_attr.len = MLX5DR_WQE_SZ_GTA_CTRL + MLX5DR_WQE_SZ_GTA_DATA;\n+\tste_attr.send_attr.rule = rule;\n+\tste_attr.send_attr.notify_hw = 1;\n+\tste_attr.send_attr.user_data = user_data;\n+\tste_attr.rtc_0 = rule->resize_info->rtc_0;\n+\tste_attr.rtc_1 = rule->resize_info->rtc_1;\n+\tste_attr.used_id_rtc_0 = &rule->resize_info->rtc_0;\n+\tste_attr.used_id_rtc_1 = &rule->resize_info->rtc_1;\n+\tste_attr.wqe_ctrl = &empty_wqe_ctrl;\n+\tste_attr.wqe_tag_is_jumbo = is_jumbo;\n+\tste_attr.gta_opcode = MLX5DR_WQE_GTA_OP_DEACTIVATE;\n+\n+\tif (unlikely(mlx5dr_matcher_is_insert_by_idx(matcher)))\n+\t\tste_attr.direct_index = rule->resize_info->rule_idx;\n+\n+\tmlx5dr_rule_load_delete_info(rule, &ste_attr);\n+\tmlx5dr_send_ste(queue, &ste_attr);\n+\n+\treturn 0;\n+}\n+\n+int mlx5dr_rule_move_hws_add(struct mlx5dr_rule *rule,\n+\t\t\t struct mlx5dr_rule_attr *attr)\n+{\n+\tbool is_jumbo = mlx5dr_matcher_mt_is_jumbo(rule->matcher->mt);\n+\tstruct mlx5dr_context *ctx = rule->matcher->tbl->ctx;\n+\tstruct mlx5dr_matcher *matcher = rule->matcher;\n+\tstruct mlx5dr_send_ste_attr ste_attr = {0};\n+\tstruct mlx5dr_send_engine *queue;\n+\n+\tif (unlikely(mlx5dr_rule_enqueue_precheck_move(rule, attr)))\n+\t\treturn -rte_errno;\n+\n+\tqueue = &ctx->send_queue[attr->queue_id];\n+\n+\tif (unlikely(mlx5dr_send_engine_err(queue))) {\n+\t\trte_errno = EIO;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tmlx5dr_rule_move_init(rule, attr);\n+\n+\tmlx5dr_rule_move_get_rtc(rule, &ste_attr);\n+\n+\tste_attr.send_attr.opmod = MLX5DR_WQE_GTA_OPMOD_STE;\n+\tste_attr.send_attr.opcode = MLX5DR_WQE_OPCODE_TBL_ACCESS;\n+\tste_attr.send_attr.len = MLX5DR_WQE_SZ_GTA_CTRL + MLX5DR_WQE_SZ_GTA_DATA;\n+\tste_attr.gta_opcode = MLX5DR_WQE_GTA_OP_ACTIVATE;\n+\tste_attr.wqe_tag_is_jumbo = is_jumbo;\n+\n+\tste_attr.send_attr.rule = rule;\n+\tste_attr.send_attr.fence = 0;\n+\tste_attr.send_attr.notify_hw = !attr->burst;\n+\tste_attr.send_attr.user_data = attr->user_data;\n+\n+\tste_attr.used_id_rtc_0 = &rule->rtc_0;\n+\tste_attr.used_id_rtc_1 = &rule->rtc_1;\n+\tste_attr.wqe_ctrl = (struct mlx5dr_wqe_gta_ctrl_seg *)rule->resize_info->ctrl_seg;\n+\tste_attr.wqe_data = (struct mlx5dr_wqe_gta_data_seg_ste *)rule->resize_info->data_seg;\n+\tste_attr.direct_index = mlx5dr_matcher_is_insert_by_idx(matcher) ?\n+\t\t\t\tattr->rule_idx : 0;\n+\n+\tmlx5dr_send_ste(queue, &ste_attr);\n+\tmlx5dr_send_engine_inc_rule(queue);\n+\n+\t/* Send dependent WQEs */\n+\tif (!attr->burst)\n+\t\tmlx5dr_send_all_dep_wqe(queue);\n+\n+\treturn 0;\n+}\n+\n int mlx5dr_rule_create(struct mlx5dr_matcher *matcher,\n \t\t uint8_t mt_idx,\n \t\t const struct rte_flow_item items[],\n@@ -689,13 +924,11 @@ int mlx5dr_rule_create(struct mlx5dr_matcher *matcher,\n \t\t struct mlx5dr_rule_attr *attr,\n \t\t struct mlx5dr_rule *rule_handle)\n {\n-\tstruct mlx5dr_context *ctx;\n \tint ret;\n \n \trule_handle->matcher = matcher;\n-\tctx = matcher->tbl->ctx;\n \n-\tif (mlx5dr_rule_enqueue_precheck(ctx, attr))\n+\tif (unlikely(mlx5dr_rule_enqueue_precheck_create(rule_handle, attr)))\n \t\treturn -rte_errno;\n \n \tassert(matcher->num_of_mt >= mt_idx);\n@@ -723,7 +956,7 @@ int mlx5dr_rule_destroy(struct mlx5dr_rule *rule,\n {\n \tint ret;\n \n-\tif (mlx5dr_rule_enqueue_precheck(rule->matcher->tbl->ctx, attr))\n+\tif (unlikely(mlx5dr_rule_enqueue_precheck(rule, attr)))\n \t\treturn -rte_errno;\n \n \tif (unlikely(mlx5dr_table_is_root(rule->matcher->tbl)))\n@@ -739,24 +972,9 @@ int mlx5dr_rule_action_update(struct mlx5dr_rule *rule_handle,\n \t\t\t struct mlx5dr_rule_action rule_actions[],\n \t\t\t struct mlx5dr_rule_attr *attr)\n {\n-\tstruct mlx5dr_matcher *matcher = rule_handle->matcher;\n \tint ret;\n \n-\tif (unlikely(mlx5dr_table_is_root(matcher->tbl) ||\n-\t unlikely(mlx5dr_matcher_req_fw_wqe(matcher)))) {\n-\t\tDR_LOG(ERR, \"Rule update not supported on current matcher\");\n-\t\trte_errno = ENOTSUP;\n-\t\treturn -rte_errno;\n-\t}\n-\n-\tif (!matcher->attr.optimize_using_rule_idx &&\n-\t !mlx5dr_matcher_is_insert_by_idx(matcher)) {\n-\t\tDR_LOG(ERR, \"Rule update requires optimize by idx matcher\");\n-\t\trte_errno = ENOTSUP;\n-\t\treturn -rte_errno;\n-\t}\n-\n-\tif (mlx5dr_rule_enqueue_precheck(matcher->tbl->ctx, attr))\n+\tif (unlikely(mlx5dr_rule_enqueue_precheck_update(rule_handle, attr)))\n \t\treturn -rte_errno;\n \n \tret = mlx5dr_rule_create_hws(rule_handle,\n@@ -780,7 +998,7 @@ int mlx5dr_rule_hash_calculate(struct mlx5dr_matcher *matcher,\n \t\t\t enum mlx5dr_rule_hash_calc_mode mode,\n \t\t\t uint32_t *ret_hash)\n {\n-\tuint8_t tag[MLX5DR_STE_SZ] = {0};\n+\tuint8_t tag[MLX5DR_WQE_SZ_GTA_DATA] = {0};\n \tstruct mlx5dr_match_template *mt;\n \n \tif (!matcher || !matcher->mt) {\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_rule.h b/drivers/net/mlx5/hws/mlx5dr_rule.h\nindex f7d97eead5..07adf9c5ad 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_rule.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_rule.h\n@@ -10,7 +10,6 @@ enum {\n \tMLX5DR_ACTIONS_SZ = 12,\n \tMLX5DR_MATCH_TAG_SZ = 32,\n \tMLX5DR_JUMBO_TAG_SZ = 44,\n-\tMLX5DR_STE_SZ = 64,\n };\n \n enum mlx5dr_rule_status {\n@@ -23,6 +22,12 @@ enum mlx5dr_rule_status {\n \tMLX5DR_RULE_STATUS_FAILED,\n };\n \n+enum mlx5dr_rule_move_state {\n+\tMLX5DR_RULE_RESIZE_STATE_IDLE,\n+\tMLX5DR_RULE_RESIZE_STATE_WRITING,\n+\tMLX5DR_RULE_RESIZE_STATE_DELETING,\n+};\n+\n struct mlx5dr_rule_match_tag {\n \tunion {\n \t\tuint8_t jumbo[MLX5DR_JUMBO_TAG_SZ];\n@@ -33,6 +38,16 @@ struct mlx5dr_rule_match_tag {\n \t};\n };\n \n+struct mlx5dr_rule_resize_info {\n+\tuint8_t state;\n+\tuint32_t rtc_0;\n+\tuint32_t rtc_1;\n+\tuint32_t rule_idx;\n+\tstruct mlx5dr_pool *action_ste_pool;\n+\tuint8_t ctrl_seg[MLX5DR_WQE_SZ_GTA_CTRL]; /* Ctrl segment of STE: 48 bytes */\n+\tuint8_t data_seg[MLX5DR_WQE_SZ_GTA_DATA]; /* Data segment of STE: 64 bytes */\n+};\n+\n struct mlx5dr_rule {\n \tstruct mlx5dr_matcher *matcher;\n \tunion {\n@@ -40,6 +55,7 @@ struct mlx5dr_rule {\n \t\t/* Pointer to tag to store more than one tag */\n \t\tstruct mlx5dr_rule_match_tag *tag_ptr;\n \t\tstruct ibv_flow *flow;\n+\t\tstruct mlx5dr_rule_resize_info *resize_info;\n \t};\n \tuint32_t rtc_0; /* The RTC into which the STE was inserted */\n \tuint32_t rtc_1; /* The RTC into which the STE was inserted */\n@@ -50,4 +66,16 @@ struct mlx5dr_rule {\n \n void mlx5dr_rule_free_action_ste_idx(struct mlx5dr_rule *rule);\n \n+int mlx5dr_rule_move_hws_remove(struct mlx5dr_rule *rule,\n+\t\t\t\tvoid *queue, void *user_data);\n+\n+int mlx5dr_rule_move_hws_add(struct mlx5dr_rule *rule,\n+\t\t\t struct mlx5dr_rule_attr *attr);\n+\n+static inline bool mlx5dr_rule_move_in_progress(struct mlx5dr_rule *rule)\n+{\n+\treturn rule->resize_info &&\n+\t rule->resize_info->state != MLX5DR_RULE_RESIZE_STATE_IDLE;\n+}\n+\n #endif /* MLX5DR_RULE_H_ */\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_send.c b/drivers/net/mlx5/hws/mlx5dr_send.c\nindex 622d574bfa..64138279a1 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_send.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_send.c\n@@ -444,6 +444,46 @@ void mlx5dr_send_engine_flush_queue(struct mlx5dr_send_engine *queue)\n \tmlx5dr_send_engine_post_ring(sq, queue->uar, wqe_ctrl);\n }\n \n+static void\n+mlx5dr_send_engine_update_rule_resize(struct mlx5dr_send_engine *queue,\n+\t\t\t\t struct mlx5dr_send_ring_priv *priv,\n+\t\t\t\t enum rte_flow_op_status *status)\n+{\n+\tswitch (priv->rule->resize_info->state) {\n+\tcase MLX5DR_RULE_RESIZE_STATE_WRITING:\n+\t\tif (priv->rule->status == MLX5DR_RULE_STATUS_FAILING) {\n+\t\t\t/* Backup original RTCs */\n+\t\t\tuint32_t orig_rtc_0 = priv->rule->resize_info->rtc_0;\n+\t\t\tuint32_t orig_rtc_1 = priv->rule->resize_info->rtc_1;\n+\n+\t\t\t/* Delete partially failed move rule using resize_info */\n+\t\t\tpriv->rule->resize_info->rtc_0 = priv->rule->rtc_0;\n+\t\t\tpriv->rule->resize_info->rtc_1 = priv->rule->rtc_1;\n+\n+\t\t\t/* Move rule to original RTC for future delete */\n+\t\t\tpriv->rule->rtc_0 = orig_rtc_0;\n+\t\t\tpriv->rule->rtc_1 = orig_rtc_1;\n+\t\t}\n+\t\t/* Clean leftovers */\n+\t\tmlx5dr_rule_move_hws_remove(priv->rule, queue, priv->user_data);\n+\t\tbreak;\n+\n+\tcase MLX5DR_RULE_RESIZE_STATE_DELETING:\n+\t\tif (priv->rule->status == MLX5DR_RULE_STATUS_FAILING) {\n+\t\t\t*status = RTE_FLOW_OP_ERROR;\n+\t\t} else {\n+\t\t\t*status = RTE_FLOW_OP_SUCCESS;\n+\t\t\tpriv->rule->matcher = priv->rule->matcher->resize_dst;\n+\t\t}\n+\t\tpriv->rule->resize_info->state = MLX5DR_RULE_RESIZE_STATE_IDLE;\n+\t\tpriv->rule->status = MLX5DR_RULE_STATUS_CREATED;\n+\t\tbreak;\n+\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n static void mlx5dr_send_engine_update_rule(struct mlx5dr_send_engine *queue,\n \t\t\t\t\t struct mlx5dr_send_ring_priv *priv,\n \t\t\t\t\t uint16_t wqe_cnt,\n@@ -465,6 +505,11 @@ static void mlx5dr_send_engine_update_rule(struct mlx5dr_send_engine *queue,\n \n \t/* Update rule status for the last completion */\n \tif (!priv->rule->pending_wqes) {\n+\t\tif (unlikely(mlx5dr_rule_move_in_progress(priv->rule))) {\n+\t\t\tmlx5dr_send_engine_update_rule_resize(queue, priv, status);\n+\t\t\treturn;\n+\t\t}\n+\n \t\tif (unlikely(priv->rule->status == MLX5DR_RULE_STATUS_FAILING)) {\n \t\t\t/* Rule completely failed and doesn't require cleanup */\n \t\t\tif (!priv->rule->rtc_0 && !priv->rule->rtc_1)\n", "prefixes": [ "3/9" ] }