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GET /api/patches/136859/?format=api
{ "id": 136859, "url": "http://patchwork.dpdk.org/api/patches/136859/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240218051125.717011-4-igozlan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240218051125.717011-4-igozlan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240218051125.717011-4-igozlan@nvidia.com", "date": "2024-02-18T05:11:18", "name": "[v2,04/10] net/mlx5/hws: reordering the STE fields to improve hash", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "ae3a8fd190c2948dd9fa4d02328d628c3108e9ff", "submitter": { "id": 3118, "url": "http://patchwork.dpdk.org/api/people/3118/?format=api", "name": "Itamar Gozlan", "email": "igozlan@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240218051125.717011-4-igozlan@nvidia.com/mbox/", "series": [ { "id": 31133, "url": "http://patchwork.dpdk.org/api/series/31133/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31133", "date": "2024-02-18T05:11:16", "name": "[v2,01/10] net/mlx5/hws: skip RTE item when inserting rules by index", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31133/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/136859/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/136859/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 030FC43AFD;\n\tSun, 18 Feb 2024 06:12:04 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 64CAF40DCD;\n\tSun, 18 Feb 2024 06:11:57 +0100 (CET)", "from NAM02-BN1-obe.outbound.protection.outlook.com\n (mail-bn1nam02on2082.outbound.protection.outlook.com [40.107.212.82])\n by mails.dpdk.org (Postfix) with ESMTP id 6020940A8A\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Itamar Gozlan <igozlan@nvidia.com>", "To": "<igozlan@nvidia.com>, <erezsh@nvidia.com>, <hamdani@nvidia.com>,\n <kliteyn@nvidia.com>, <viacheslavo@nvidia.com>, <thomas@monjalon.net>,\n <suanmingm@nvidia.com>, Dariusz Sosnowski <dsosnowski@nvidia.com>, Ori Kam\n <orika@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>", "Subject": "[v2 04/10] net/mlx5/hws: reordering the STE fields to improve hash", "Date": "Sun, 18 Feb 2024 07:11:18 +0200", "Message-ID": "<20240218051125.717011-4-igozlan@nvidia.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20240218051125.717011-1-igozlan@nvidia.com>", "References": "<20240213095038.451299-9-igozlan@nvidia.com>\n <20240218051125.717011-1-igozlan@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DS2PEPF00003445:EE_|MN0PR12MB5930:EE_", "X-MS-Office365-Filtering-Correlation-Id": "f772939d-fa25-4b8d-9344-08dc30401e8d", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n vDrQZO4fHaG0ClzZ/kRQa+y3n79AZtA8vvqV+3oQchmnmJyXKfGZf+8II5gU7+ob59D8zVa+t1Hny8DxHuqBQh+ghTgY+m/JSL1QXoUwJgF6Pm48DbI58wzdJ0xuDciwN5KSTZxDxdF0+IoXyBtKQuTkB84YO8Iks0Bqax6tQsCOoTQq/Kjo8URaDTBkZg1tmwbYBZacgb7r1+Za+7/c39Z9nJwVd6j0SEnRHLDOhEbIV9bukZm7WIy8W56kcw84yKG+6BRci+QfgWgYNQk+MW3zY8MPYdr6QY5bxuSpOJCsYT4iX6+2+3sXvdkoU8mxhEe/G+1xk8Z7mS7GqQOYX56Pa6cxYMldVs3K4C1en7a8ZiFV6OJaWJDJ6gxx7T+AAxJB1i2G7hwa3oUSA0/B9wF3f5+jiE42SVWWuiWRi1iedpLLzjWfvZkNTeoMPSmjRkMURfR8k/J6F6gW0Fu9YFp6kw3uHvqs742iIeo6oL5w4qVHTl2eooFpXejKsTzopL5NCMySKm4xF4We6GOFy1xNRUGsqUG3X6FnyIC0tob6irlwgvSXgc0LuEpeTNtz1ZQ4wVLWE94zeG4iwriwS5CP1sSE+LynG+IhvVZZvYRkETWUDr2tgWpcpczMi5hF+FwyomBWTxjt/k4zUmC/z+MZn2aY3b0CHP1O1o9XYtQ=", "X-Forefront-Antispam-Report": "CIP:216.228.118.232; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(4636009)(136003)(346002)(396003)(39860400002)(376002)(230922051799003)(451199024)(1800799012)(36860700004)(64100799003)(186009)(82310400011)(40470700004)(46966006)(2616005)(921011)(36756003)(426003)(336012)(6286002)(83380400001)(26005)(1076003)(70206006)(8676002)(4326008)(8936002)(70586007)(41300700001)(478600001)(6666004)(7696005)(110136005)(316002)(86362001)(356005)(7636003)(6636002)(82740400003)(5660300002)(55016003)(2906002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Feb 2024 05:11:52.7152 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n f772939d-fa25-4b8d-9344-08dc30401e8d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.232];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DS2PEPF00003445.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN0PR12MB5930", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Inserting two rules with the same hash calculation result into the same\nmatcher will cause collisions, which can cause degradation in PPS.\nChanging the order of some fields in the STE can change the hash result,\nand doing this for every value would give us a different hash distribution\nfor the inputs. By using precomputed optimal DW locations, we can change\nthe STE order for a limited set of the most common values to reduce the\nnumber of hash collisions and improve latency.\n\nSigned-off-by: Itamar Gozlan <igozlan@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/hws/mlx5dr_definer.c | 64 +++++++++++++++++++++++++++\n 1 file changed, 64 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex e564062313..eb788a772a 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -100,6 +100,33 @@\n \t__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \\\n \t__mlx5_mask(typ, fld))\n \n+#define MAX_ROW_LOG 31\n+\n+enum header_layout {\n+\tMLX5DR_HL_IPV4_SRC = 64,\n+\tMLX5DR_HL_IPV4_DST = 65,\n+\tMAX_HL_PRIO,\n+};\n+\n+/* Each row (i) indicates a different matcher size, and each column (j)\n+ * represents {DW5, DW4, DW3, DW2, DW1, DW0}.\n+ * For values 0,..,2^i, and j (DW) 0,..,5: optimal_dist_dw[i][j] is 1 if the\n+ * number of different hash results on these values equals 2^i, meaning this\n+ * DW hash distribution is complete.\n+ */\n+int optimal_dist_dw[MAX_ROW_LOG][DW_SELECTORS_MATCH] = {\n+\t{1, 1, 1, 1, 1, 1}, {0, 1, 1, 0, 1, 0}, {0, 1, 1, 0, 1, 0},\n+\t{1, 0, 1, 0, 1, 0}, {0, 0, 0, 1, 1, 0}, {0, 1, 1, 0, 1, 0},\n+\t{0, 0, 0, 0, 1, 0}, {0, 1, 1, 0, 1, 0}, {0, 0, 0, 0, 0, 0},\n+\t{1, 0, 1, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 1, 0, 1, 0, 0},\n+\t{1, 0, 0, 0, 0, 0}, {0, 0, 1, 0, 0, 1}, {1, 1, 1, 0, 0, 0},\n+\t{1, 1, 1, 0, 1, 0}, {0, 0, 1, 1, 0, 0}, {0, 1, 1, 0, 0, 1},\n+\t{0, 0, 1, 0, 0, 1}, {0, 0, 1, 0, 0, 0}, {1, 0, 1, 1, 0, 0},\n+\t{1, 0, 1, 0, 0, 1}, {0, 0, 1, 1, 0, 1}, {1, 1, 1, 0, 0, 0},\n+\t{0, 1, 0, 1, 0, 1}, {0, 0, 0, 0, 0, 1}, {0, 0, 0, 1, 1, 1},\n+\t{0, 0, 1, 0, 0, 1}, {1, 1, 0, 1, 1, 0}, {0, 0, 0, 0, 1, 0},\n+\t{0, 0, 0, 1, 1, 0}};\n+\n struct mlx5dr_definer_sel_ctrl {\n \tuint8_t allowed_full_dw; /* Full DW selectors cover all offsets */\n \tuint8_t allowed_lim_dw; /* Limited DW selectors cover offset < 64 */\n@@ -3185,6 +3212,37 @@ mlx5dr_definer_find_best_range_fit(struct mlx5dr_definer *definer,\n \treturn rte_errno;\n }\n \n+static void mlx5dr_definer_optimize_order(struct mlx5dr_definer *definer, int num_log)\n+{\n+\tuint8_t hl_prio[MAX_HL_PRIO - 1] = {MLX5DR_HL_IPV4_SRC,\n+\t\t\t\t\t MLX5DR_HL_IPV4_DST,\n+\t\t\t\t\t MAX_HL_PRIO};\n+\tint dw = 0, i = 0, j;\n+\tint *dw_flag;\n+\tuint8_t tmp;\n+\n+\tdw_flag = optimal_dist_dw[num_log];\n+\n+\twhile (hl_prio[i] != MAX_HL_PRIO) {\n+\t\tj = 0;\n+\t\t/* Finding a candidate to improve its hash distribution */\n+\t\twhile (j < DW_SELECTORS_MATCH && (hl_prio[i] != definer->dw_selector[j]))\n+\t\t\tj++;\n+\n+\t\t/* Finding a DW location with good hash distribution */\n+\t\twhile (dw < DW_SELECTORS_MATCH && dw_flag[dw] == 0)\n+\t\t\tdw++;\n+\n+\t\tif (dw < DW_SELECTORS_MATCH && j < DW_SELECTORS_MATCH) {\n+\t\t\ttmp = definer->dw_selector[dw];\n+\t\t\tdefiner->dw_selector[dw] = definer->dw_selector[j];\n+\t\t\tdefiner->dw_selector[j] = tmp;\n+\t\t\tdw++;\n+\t\t}\n+\t\ti++;\n+\t}\n+}\n+\n static int\n mlx5dr_definer_find_best_match_fit(struct mlx5dr_context *ctx,\n \t\t\t\t struct mlx5dr_definer *definer,\n@@ -3355,6 +3413,12 @@ mlx5dr_definer_calc_layout(struct mlx5dr_matcher *matcher,\n \t\tgoto free_fc;\n \t}\n \n+\tif (!mlx5dr_definer_is_jumbo(match_definer) &&\n+\t !mlx5dr_matcher_req_fw_wqe(matcher) &&\n+\t !mlx5dr_matcher_is_resizable(matcher) &&\n+\t !mlx5dr_matcher_is_insert_by_idx(matcher))\n+\t\tmlx5dr_definer_optimize_order(match_definer, matcher->attr.rule.num_log);\n+\n \t/* Find the range definer layout for match templates fcrs */\n \tret = mlx5dr_definer_find_best_range_fit(range_definer, matcher);\n \tif (ret) {\n", "prefixes": [ "v2", "04/10" ] }