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GET /api/patches/137344/?format=api
{ "id": 137344, "url": "http://patchwork.dpdk.org/api/patches/137344/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240227113345.863082-2-nishikanta.nayak@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240227113345.863082-2-nishikanta.nayak@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240227113345.863082-2-nishikanta.nayak@intel.com", "date": "2024-02-27T11:33:42", "name": "[v5,1/4] common/qat: add files specific to GEN LCE", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "118a4b40c113351a5721286167ead131692b7f2b", "submitter": { "id": 3253, "url": "http://patchwork.dpdk.org/api/people/3253/?format=api", "name": "Nayak, Nishikanta", "email": "nishikanta.nayak@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240227113345.863082-2-nishikanta.nayak@intel.com/mbox/", "series": [ { "id": 31244, "url": "http://patchwork.dpdk.org/api/series/31244/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31244", "date": "2024-02-27T11:33:41", "name": "add QAT GEN LCE device", "version": 5, "mbox": "http://patchwork.dpdk.org/series/31244/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/137344/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/137344/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1AC5943C0C;\n\tTue, 27 Feb 2024 12:34:18 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 4F68A40DC9;\n\tTue, 27 Feb 2024 12:34:16 +0100 (CET)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.14])\n by mails.dpdk.org (Postfix) with ESMTP id D7E0440267\n for <dev@dpdk.org>; Tue, 27 Feb 2024 12:34:11 +0100 (CET)", "from orviesa009.jf.intel.com ([10.64.159.149])\n by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Feb 2024 03:33:53 -0800", "from silpixa00401797.ir.intel.com (HELO\n silpixa00400355.ger.corp.intel.com) ([10.237.222.113])\n by orviesa009.jf.intel.com with ESMTP; 27 Feb 2024 03:33:51 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1709033652; x=1740569652;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=c1EbL8Sd0WSH8aLXdxrMEW9ocrYCTuAXxMl4UG1kJKo=;\n b=K6STQtzwLgs5LIqPM/gny4blwGLNMLkA0o4Jtxd4zxpFgpgWfR48OTI4\n lyFgYN+zSCVkqr/dLxGlgA0B6cL/RyoL996dHT55wycMT5kiq4uYqroFD\n yFIPokG4CO+0JzzGieiJs4Qe46Tbdd/fK6QUjl87tcfjSoGeT13AAXrUj\n /3Fp7ESUQ7fAUAjKxgLSY/Yvjm39tp0PETdZW0aC5hr2ahCkeT+7pT1lz\n 1P4jcPhPpaN3Rvn/Vd0HHRrthkhYRJtHHNlgTotmUP42xwoLJ9SoLt0gX\n qLcYGIehp7fsCBGs4FSekHiZVukAf2vHq/Pz3uNtUihjdWCMey5UeAdeV w==;", "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,10996\"; a=\"3527960\"", "E=Sophos;i=\"6.06,187,1705392000\";\n d=\"scan'208\";a=\"3527960\"", "E=Sophos;i=\"6.06,187,1705392000\";\n d=\"scan'208\";a=\"7044726\"" ], "X-ExtLoop1": "1", "From": "Nishikant Nayak <nishikanta.nayak@intel.com>", "To": "dev@dpdk.org", "Cc": "ciara.power@intel.com, kai.ji@intel.com, arkadiuszx.kusztal@intel.com,\n rakesh.s.joshi@intel.com, Nishikant Nayak <nishikanta.nayak@intel.com>,\n Thomas Monjalon <thomas@monjalon.net>,\n Anatoly Burakov <anatoly.burakov@intel.com>", "Subject": "[PATCH v5 1/4] common/qat: add files specific to GEN LCE", "Date": "Tue, 27 Feb 2024 11:33:42 +0000", "Message-Id": "<20240227113345.863082-2-nishikanta.nayak@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240227113345.863082-1-nishikanta.nayak@intel.com>", "References": "<20231220132616.318983-1-nishikanta.nayak@intel.com>\n <20240227113345.863082-1-nishikanta.nayak@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Adding GEN5 files for handling GEN LCE specific operations.\nThese files are inherited from the existing files/APIs\nwhich has some changes specific GEN5 requirements\nAlso updated the mailmap file.\n\nSigned-off-by: Nishikant Nayak <nishikanta.nayak@intel.com>\nAcked-by: Ciara Power <ciara.power@intel.com>\n---\nv5:\n - Replaced usage of __u8 with uint8_t.\nv3:\n - Removed use of linux/kernel.h macro to fix ARM compilation.\n - Fixed typo in commit body and code comment.\nv2:\n - Renamed device from GEN 5 to GEN LCE.\n - Removed unused code.\n - Updated macro names.\n---\n---\n .mailmap | 1 +\n drivers/common/qat/dev/qat_dev_gen_lce.c | 306 ++++++++++++++++\n drivers/common/qat/meson.build | 2 +\n .../adf_transport_access_macros_gen_lce.h | 51 +++\n .../adf_transport_access_macros_gen_lcevf.h | 48 +++\n drivers/common/qat/qat_adf/icp_qat_fw_la.h | 14 +\n drivers/common/qat/qat_common.h | 1 +\n .../crypto/qat/dev/qat_crypto_pmd_gen_lce.c | 329 ++++++++++++++++++\n drivers/crypto/qat/qat_sym.h | 6 +\n 9 files changed, 758 insertions(+)\n create mode 100644 drivers/common/qat/dev/qat_dev_gen_lce.c\n create mode 100644 drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lce.h\n create mode 100644 drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lcevf.h\n create mode 100644 drivers/crypto/qat/dev/qat_crypto_pmd_gen_lce.c", "diff": "diff --git a/.mailmap b/.mailmap\nindex 58cca13ef6..8008e5a899 100644\n--- a/.mailmap\n+++ b/.mailmap\n@@ -1036,6 +1036,7 @@ Ning Li <muziding001@163.com> <lining18@jd.com>\n Nipun Gupta <nipun.gupta@amd.com> <nipun.gupta@nxp.com>\n Nir Efrati <nir.efrati@intel.com>\n Nirmoy Das <ndas@suse.de>\n+Nishikant Nayak <nishikanta.nayak@intel.com>\n Nithin Dabilpuram <ndabilpuram@marvell.com> <nithin.dabilpuram@caviumnetworks.com>\n Nitin Saxena <nitin.saxena@caviumnetworks.com>\n Nitzan Weller <nitzanwe@mellanox.com>\ndiff --git a/drivers/common/qat/dev/qat_dev_gen_lce.c b/drivers/common/qat/dev/qat_dev_gen_lce.c\nnew file mode 100644\nindex 0000000000..5faaefc2d8\n--- /dev/null\n+++ b/drivers/common/qat/dev/qat_dev_gen_lce.c\n@@ -0,0 +1,306 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#include <rte_pci.h>\n+#include <rte_vfio.h>\n+\n+#include \"qat_device.h\"\n+#include \"qat_qp.h\"\n+#include \"adf_transport_access_macros_gen_lcevf.h\"\n+#include \"adf_pf2vf_msg.h\"\n+#include \"qat_pf2vf.h\"\n+\n+#include <stdint.h>\n+#include <sys/ioctl.h>\n+#include <unistd.h>\n+\n+#define BITS_PER_ULONG\t\t(sizeof(unsigned long) * 8)\n+\n+#define VFIO_PCI_LCE_DEVICE_CFG_REGION_INDEX\tVFIO_PCI_NUM_REGIONS\n+#define VFIO_PCI_LCE_CY_CFG_REGION_INDEX\t(VFIO_PCI_NUM_REGIONS + 2)\n+#define VFIO_PCI_LCE_RING_CFG_REGION_INDEX\t(VFIO_PCI_NUM_REGIONS + 4)\n+#define LCE_DEVICE_NAME_SIZE\t\t\t64\n+#define LCE_DEVICE_MAX_BANKS\t\t\t2080\n+#define LCE_DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))\n+#define LCE_DEVICE_BITMAP_SIZE \\\n+\tLCE_DIV_ROUND_UP(LCE_DEVICE_MAX_BANKS, BITS_PER_ULONG)\n+\n+/* QAT GEN_LCE specific macros */\n+#define QAT_GEN_LCE_BUNDLE_NUM\t\tLCE_DEVICE_MAX_BANKS\n+#define QAT_GEN4_QPS_PER_BUNDLE_NUM\t1\n+\n+/**\n+ * struct lce_vfio_dev_cap - LCE device capabilities\n+ *\n+ * Device level capabilities and service level capabilities\n+ */\n+struct lce_vfio_dev_cap {\n+\tuint16_t device_num;\n+\tuint16_t device_type;\n+\tuint32_t capability_mask;\n+\tuint32_t extended_capabilities;\n+\tuint16_t max_banks;\n+\tuint16_t max_rings_per_bank;\n+\tuint16_t arb_mask;\n+\tuint16_t services;\n+\tuint16_t pkg_id;\n+\tuint16_t node_id;\n+\tuint8_t device_name[LCE_DEVICE_NAME_SIZE];\n+};\n+\n+/* struct lce_vfio_dev_cy_cap - CY capabilities of LCE device */\n+struct lce_vfio_dev_cy_cap {\n+\tuint32_t nr_banks;\n+\tunsigned long bitmap[LCE_DEVICE_BITMAP_SIZE];\n+};\n+\n+struct lce_qat_domain {\n+\tuint32_t nid :3;\n+\tuint32_t fid :7;\n+\tuint32_t ftype :2;\n+\tuint32_t vfid :13;\n+\tuint32_t rid :4;\n+\tuint32_t vld :1;\n+\tuint32_t desc_over :1;\n+\tuint32_t pasid_vld :1;\n+\tuint32_t pasid :20;\n+};\n+\n+struct lce_qat_buf_domain {\n+\tuint32_t bank_id: 20;\n+\tuint32_t type: 4;\n+\tuint32_t resv: 8;\n+\tstruct lce_qat_domain dom;\n+};\n+\n+struct qat_dev_gen_lce_extra {\n+\tstruct qat_qp_hw_data\n+\t qp_gen_lce_data[QAT_GEN_LCE_BUNDLE_NUM][QAT_GEN4_QPS_PER_BUNDLE_NUM];\n+};\n+\n+static struct qat_pf2vf_dev qat_pf2vf_gen_lce = {\n+\t.pf2vf_offset = ADF_4XXXIOV_PF2VM_OFFSET,\n+\t.vf2pf_offset = ADF_4XXXIOV_VM2PF_OFFSET,\n+\t.pf2vf_type_shift = ADF_PFVF_2X_MSGTYPE_SHIFT,\n+\t.pf2vf_type_mask = ADF_PFVF_2X_MSGTYPE_MASK,\n+\t.pf2vf_data_shift = ADF_PFVF_2X_MSGDATA_SHIFT,\n+\t.pf2vf_data_mask = ADF_PFVF_2X_MSGDATA_MASK,\n+};\n+\n+static int\n+qat_select_valid_queue_gen_lce(struct qat_pci_device *qat_dev, int qp_id,\n+\t\t\t enum qat_service_type service_type)\n+{\n+\tint i = 0, valid_qps = 0;\n+\tstruct qat_dev_gen_lce_extra *dev_extra = qat_dev->dev_private;\n+\n+\tfor (; i < QAT_GEN_LCE_BUNDLE_NUM; i++) {\n+\t\tif (dev_extra->qp_gen_lce_data[i][0].service_type ==\n+\t\t\t\tservice_type) {\n+\t\t\tif (valid_qps == qp_id)\n+\t\t\t\treturn i;\n+\t\t\t++valid_qps;\n+\t\t}\n+\t}\n+\treturn -1;\n+}\n+\n+static const struct qat_qp_hw_data *\n+qat_qp_get_hw_data_gen_lce(struct qat_pci_device *qat_dev,\n+\t\t\tenum qat_service_type service_type, uint16_t qp_id)\n+{\n+\tstruct qat_dev_gen_lce_extra *dev_extra = qat_dev->dev_private;\n+\tint ring_pair = qat_select_valid_queue_gen_lce(qat_dev, qp_id,\n+\t\t\t\t\t\t\t\tservice_type);\n+\n+\tif (ring_pair < 0)\n+\t\treturn NULL;\n+\n+\treturn &dev_extra->qp_gen_lce_data[ring_pair][0];\n+}\n+\n+static int\n+qat_qp_rings_per_service_gen_lce(struct qat_pci_device *qat_dev,\n+\t\t\t enum qat_service_type service)\n+{\n+\tint i = 0, count = 0, max_ops_per_srv = 0;\n+\tstruct qat_dev_gen_lce_extra *dev_extra = qat_dev->dev_private;\n+\n+\tmax_ops_per_srv = QAT_GEN_LCE_BUNDLE_NUM;\n+\tfor (i = 0, count = 0; i < max_ops_per_srv; i++)\n+\t\tif (dev_extra->qp_gen_lce_data[i][0].service_type == service)\n+\t\t\tcount++;\n+\treturn count;\n+}\n+\n+static int qat_dev_read_config_gen_lce(struct qat_pci_device *qat_dev)\n+{\n+\tstruct qat_dev_gen_lce_extra *dev_extra = qat_dev->dev_private;\n+\tstruct qat_qp_hw_data *hw_data;\n+\n+\t/** Enable only crypto ring: RP-0 */\n+\thw_data = &dev_extra->qp_gen_lce_data[0][0];\n+\tmemset(hw_data, 0, sizeof(*hw_data));\n+\n+\thw_data->service_type = QAT_SERVICE_SYMMETRIC;\n+\thw_data->tx_msg_size = 128;\n+\thw_data->rx_msg_size = 32;\n+\n+\thw_data->tx_ring_num = 0;\n+\thw_data->rx_ring_num = 1;\n+\n+\thw_data->hw_bundle_num = 0;\n+\n+\treturn 0;\n+}\n+\n+static void qat_qp_build_ring_base_gen_lce(void *io_addr, struct qat_queue *queue)\n+{\n+\tuint64_t queue_base;\n+\n+\tqueue_base = BUILD_RING_BASE_ADDR_GEN_LCE(queue->base_phys_addr,\n+\t\t\t\t\t queue->queue_size);\n+\tWRITE_CSR_RING_BASE_GEN_LCEVF(io_addr, queue->hw_bundle_number,\n+\t\t\t\t queue->hw_queue_number, queue_base);\n+}\n+\n+static void\n+qat_qp_adf_arb_enable_gen_lce(const struct qat_queue *txq,\n+\t\t\t void *base_addr, rte_spinlock_t *lock)\n+{\n+\tuint32_t arb_csr_offset = 0, value;\n+\n+\trte_spinlock_lock(lock);\n+\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET +\n+\t (ADF_RING_BUNDLE_SIZE_GEN_LCE *\n+\t txq->hw_bundle_number);\n+\tvalue = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF,\n+\t\t\t arb_csr_offset);\n+\tvalue |= 0x01;\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n+}\n+\n+static void\n+qat_qp_adf_arb_disable_gen_lce(const struct qat_queue *txq,\n+\t\t\t void *base_addr, rte_spinlock_t *lock)\n+{\n+\tuint32_t arb_csr_offset = 0, value;\n+\n+\trte_spinlock_lock(lock);\n+\tarb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_RING_BUNDLE_SIZE_GEN_LCE *\n+\t\t\t\t\t\t\ttxq->hw_bundle_number);\n+\tvalue = ADF_CSR_RD(base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF,\n+\t\t\t arb_csr_offset);\n+\tvalue &= ~(0x01);\n+\tADF_CSR_WR(base_addr, arb_csr_offset, value);\n+\trte_spinlock_unlock(lock);\n+}\n+\n+static void\n+qat_qp_adf_configure_queues_gen_lce(struct qat_qp *qp)\n+{\n+\tuint32_t q_tx_config, q_resp_config;\n+\tstruct qat_queue *q_tx = &qp->tx_q, *q_rx = &qp->rx_q;\n+\n+\t/* q_tx/rx->queue_size is initialized as per bundle config register */\n+\tq_tx_config = BUILD_RING_CONFIG(q_tx->queue_size);\n+\n+\tq_resp_config = BUILD_RESP_RING_CONFIG(q_rx->queue_size,\n+\t\t\t\t\t ADF_RING_NEAR_WATERMARK_512,\n+\t\t\t\t\t ADF_RING_NEAR_WATERMARK_0);\n+\n+\tWRITE_CSR_RING_CONFIG_GEN_LCEVF(qp->mmap_bar_addr, q_tx->hw_bundle_number,\n+\t\t\t\t q_tx->hw_queue_number, q_tx_config);\n+\tWRITE_CSR_RING_CONFIG_GEN_LCEVF(qp->mmap_bar_addr, q_rx->hw_bundle_number,\n+\t\t\t\t q_rx->hw_queue_number, q_resp_config);\n+}\n+\n+static void\n+qat_qp_csr_write_tail_gen_lce(struct qat_qp *qp, struct qat_queue *q)\n+{\n+\tWRITE_CSR_RING_TAIL_GEN_LCEVF(qp->mmap_bar_addr, q->hw_bundle_number,\n+\t\t\t\t q->hw_queue_number, q->tail);\n+}\n+\n+static void\n+qat_qp_csr_write_head_gen_lce(struct qat_qp *qp, struct qat_queue *q,\n+\t\t\t uint32_t new_head)\n+{\n+\tWRITE_CSR_RING_HEAD_GEN_LCEVF(qp->mmap_bar_addr, q->hw_bundle_number,\n+\t\t\t\t q->hw_queue_number, new_head);\n+}\n+\n+static void\n+qat_qp_csr_setup_gen_lce(struct qat_pci_device *qat_dev, void *io_addr,\n+\t\t struct qat_qp *qp)\n+{\n+\tqat_qp_build_ring_base_gen_lce(io_addr, &qp->tx_q);\n+\tqat_qp_build_ring_base_gen_lce(io_addr, &qp->rx_q);\n+\tqat_qp_adf_configure_queues_gen_lce(qp);\n+\tqat_qp_adf_arb_enable_gen_lce(&qp->tx_q, qp->mmap_bar_addr,\n+\t\t\t\t &qat_dev->arb_csr_lock);\n+}\n+\n+static struct qat_qp_hw_spec_funcs qat_qp_hw_spec_gen_lce = {\n+\t.qat_qp_rings_per_service = qat_qp_rings_per_service_gen_lce,\n+\t.qat_qp_build_ring_base = qat_qp_build_ring_base_gen_lce,\n+\t.qat_qp_adf_arb_enable = qat_qp_adf_arb_enable_gen_lce,\n+\t.qat_qp_adf_arb_disable = qat_qp_adf_arb_disable_gen_lce,\n+\t.qat_qp_adf_configure_queues = qat_qp_adf_configure_queues_gen_lce,\n+\t.qat_qp_csr_write_tail = qat_qp_csr_write_tail_gen_lce,\n+\t.qat_qp_csr_write_head = qat_qp_csr_write_head_gen_lce,\n+\t.qat_qp_csr_setup = qat_qp_csr_setup_gen_lce,\n+\t.qat_qp_get_hw_data = qat_qp_get_hw_data_gen_lce,\n+};\n+\n+static int\n+qat_reset_ring_pairs_gen_lce(struct qat_pci_device *qat_pci_dev __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+static const struct rte_mem_resource*\n+qat_dev_get_transport_bar_gen_lce(struct rte_pci_device *pci_dev)\n+{\n+\treturn &pci_dev->mem_resource[0];\n+}\n+\n+static int\n+qat_dev_get_misc_bar_gen_lce(struct rte_mem_resource **mem_resource,\n+\t\t\t struct rte_pci_device *pci_dev)\n+{\n+\t*mem_resource = &pci_dev->mem_resource[2];\n+\treturn 0;\n+}\n+\n+static int\n+qat_dev_get_extra_size_gen_lce(void)\n+{\n+\treturn sizeof(struct qat_dev_gen_lce_extra);\n+}\n+\n+static int\n+qat_dev_get_slice_map_gen_lce(uint32_t *map __rte_unused,\n+\tconst struct rte_pci_device *pci_dev __rte_unused)\n+{\n+\treturn 0;\n+}\n+\n+static struct qat_dev_hw_spec_funcs qat_dev_hw_spec_gen_lce = {\n+\t.qat_dev_reset_ring_pairs = qat_reset_ring_pairs_gen_lce,\n+\t.qat_dev_get_transport_bar = qat_dev_get_transport_bar_gen_lce,\n+\t.qat_dev_get_misc_bar = qat_dev_get_misc_bar_gen_lce,\n+\t.qat_dev_read_config = qat_dev_read_config_gen_lce,\n+\t.qat_dev_get_extra_size = qat_dev_get_extra_size_gen_lce,\n+\t.qat_dev_get_slice_map = qat_dev_get_slice_map_gen_lce,\n+};\n+\n+RTE_INIT(qat_dev_gen_lce_init)\n+{\n+\tqat_qp_hw_spec[QAT_GEN_LCE] = &qat_qp_hw_spec_gen_lce;\n+\tqat_dev_hw_spec[QAT_GEN_LCE] = &qat_dev_hw_spec_gen_lce;\n+\tqat_gen_config[QAT_GEN_LCE].dev_gen = QAT_GEN_LCE;\n+\tqat_gen_config[QAT_GEN_LCE].pf2vf_dev = &qat_pf2vf_gen_lce;\n+}\ndiff --git a/drivers/common/qat/meson.build b/drivers/common/qat/meson.build\nindex 62abcb6fe3..bc7c3e5b85 100644\n--- a/drivers/common/qat/meson.build\n+++ b/drivers/common/qat/meson.build\n@@ -82,6 +82,7 @@ sources += files(\n 'dev/qat_dev_gen2.c',\n 'dev/qat_dev_gen3.c',\n 'dev/qat_dev_gen4.c',\n+ 'dev/qat_dev_gen_lce.c',\n )\n includes += include_directories(\n 'qat_adf',\n@@ -108,6 +109,7 @@ if qat_crypto\n 'dev/qat_crypto_pmd_gen2.c',\n 'dev/qat_crypto_pmd_gen3.c',\n 'dev/qat_crypto_pmd_gen4.c',\n+ 'dev/qat_crypto_pmd_gen_lce.c',\n ]\n sources += files(join_paths(qat_crypto_relpath, f))\n endforeach\ndiff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lce.h b/drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lce.h\nnew file mode 100644\nindex 0000000000..c9df8f5dd2\n--- /dev/null\n+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lce.h\n@@ -0,0 +1,51 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#ifndef ADF_TRANSPORT_ACCESS_MACROS_GEN_LCE_H\n+#define ADF_TRANSPORT_ACCESS_MACROS_GEN_LCE_H\n+\n+#include \"adf_transport_access_macros.h\"\n+\n+#define ADF_RINGS_PER_INT_SRCSEL_GEN4 2\n+#define ADF_BANK_INT_SRC_SEL_MASK_GEN4 0x44UL\n+#define ADF_BANK_INT_FLAG_CLEAR_MASK_GEN4 0x3\n+#define ADF_RING_BUNDLE_SIZE_GEN_LCE 0x2000\n+#define ADF_RING_CSR_RING_CONFIG_GEN_LCE 0x1000\n+#define ADF_RING_CSR_RING_LBASE_GEN_LCE 0x1040\n+#define ADF_RING_CSR_RING_UBASE_GEN_LCE 0x1080\n+\n+#define BUILD_RING_BASE_ADDR_GEN_LCE(addr, size) \\\n+\t((((addr) >> 6) & (0xFFFFFFFFFFFFFFFFULL << (size))) << 6)\n+\n+#define WRITE_CSR_RING_BASE_GEN_LCE(csr_base_addr, bank, ring, value) \\\n+do { \\\n+\tuint32_t l_base = 0, u_base = 0; \\\n+\tl_base = (uint32_t)(value & 0xFFFFFFFF); \\\n+\tu_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32);\t\\\n+\tADF_CSR_WR(csr_base_addr,\t\\\n+\t\t(ADF_RING_BUNDLE_SIZE_GEN_LCE * bank) +\t\t\t\\\n+\t\tADF_RING_CSR_RING_LBASE_GEN_LCE + (ring << 2),\t\t\\\n+\t\tl_base);\t\t\t\t\t\t\\\n+\tADF_CSR_WR(csr_base_addr,\t\\\n+\t\t (ADF_RING_BUNDLE_SIZE_GEN_LCE * bank) +\t\t\t\\\n+\t\tADF_RING_CSR_RING_UBASE_GEN_LCE + (ring << 2),\t\t\\\n+\t\tu_base);\t\\\n+} while (0)\n+\n+#define WRITE_CSR_RING_CONFIG_GEN_LCE(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR(csr_base_addr,\t\\\n+\t\t (ADF_RING_BUNDLE_SIZE_GEN_LCE * bank) + \\\n+\t\tADF_RING_CSR_RING_CONFIG_GEN_LCE + (ring << 2), value)\n+\n+#define WRITE_CSR_RING_TAIL_GEN_LCE(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR((u8 *)(csr_base_addr), \\\n+\t\t(ADF_RING_BUNDLE_SIZE_GEN_LCE * (bank)) + \\\n+\t\tADF_RING_CSR_RING_TAIL + ((ring) << 2), value)\n+\n+#define WRITE_CSR_RING_HEAD_GEN_LCE(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR((u8 *)(csr_base_addr), \\\n+\t\t(ADF_RING_BUNDLE_SIZE_GEN_LCE * (bank)) + \\\n+\t\tADF_RING_CSR_RING_HEAD + ((ring) << 2), value)\n+\n+#endif\ndiff --git a/drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lcevf.h b/drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lcevf.h\nnew file mode 100644\nindex 0000000000..3c7232de12\n--- /dev/null\n+++ b/drivers/common/qat/qat_adf/adf_transport_access_macros_gen_lcevf.h\n@@ -0,0 +1,48 @@\n+/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0)\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#ifndef ADF_TRANSPORT_ACCESS_MACROS_GEN_LCEVF_H\n+#define ADF_TRANSPORT_ACCESS_MACROS_GEN_LCEVF_H\n+\n+#include \"adf_transport_access_macros.h\"\n+#include \"adf_transport_access_macros_gen_lce.h\"\n+\n+#define ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF 0x0\n+\n+#define WRITE_CSR_RING_BASE_GEN_LCEVF(csr_base_addr, bank, ring, value) \\\n+do { \\\n+\tuint32_t l_base = 0, u_base = 0; \\\n+\tl_base = (uint32_t)(value & 0xFFFFFFFF); \\\n+\tu_base = (uint32_t)((value & 0xFFFFFFFF00000000ULL) >> 32); \\\n+\tADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_GEN_LCE * bank) + \\\n+\t\tADF_RING_CSR_RING_LBASE_GEN_LCE + (ring << 2),\t\\\n+\t\tl_base);\t\\\n+\tADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF,\t\\\n+\t\t (ADF_RING_BUNDLE_SIZE_GEN_LCE * bank) + \\\n+\t\tADF_RING_CSR_RING_UBASE_GEN_LCE + (ring << 2),\t\t\\\n+\t\tu_base);\t\\\n+} while (0)\n+\n+#define WRITE_CSR_RING_CONFIG_GEN_LCEVF(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR(csr_base_addr + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF,\t\\\n+\t\t (ADF_RING_BUNDLE_SIZE_GEN_LCE * bank) + \\\n+\t\tADF_RING_CSR_RING_CONFIG_GEN_LCE + (ring << 2), value)\n+\n+#define WRITE_CSR_RING_TAIL_GEN_LCEVF(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_GEN_LCE * (bank)) + \\\n+\t\tADF_RING_CSR_RING_TAIL + ((ring) << 2), (value))\n+\n+#define WRITE_CSR_RING_HEAD_GEN_LCEVF(csr_base_addr, bank, ring, value) \\\n+\tADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_GEN_LCE * (bank)) + \\\n+\t\tADF_RING_CSR_RING_HEAD + ((ring) << 2), (value))\n+\n+#define WRITE_CSR_RING_SRV_ARB_EN_GEN_LCEVF(csr_base_addr, bank, value) \\\n+\tADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET_GEN_LCEVF, \\\n+\t\t(ADF_RING_BUNDLE_SIZE_GEN_LCE * (bank)) + \\\n+\t\tADF_RING_CSR_RING_SRV_ARB_EN, (value))\n+\n+#endif\ndiff --git a/drivers/common/qat/qat_adf/icp_qat_fw_la.h b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\nindex 70f0effa62..215b291b74 100644\n--- a/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n+++ b/drivers/common/qat/qat_adf/icp_qat_fw_la.h\n@@ -410,4 +410,18 @@ struct icp_qat_fw_la_cipher_20_req_params {\n \tuint8_t spc_auth_res_sz;\n };\n \n+struct icp_qat_fw_la_cipher_30_req_params {\n+\t\tuint32_t spc_aad_sz;\n+\t\tuint8_t cipher_length;\n+\t\tuint8_t reserved[2];\n+\t\tuint8_t spc_auth_res_sz;\n+\t\tunion {\n+\t\t\t\tuint32_t cipher_IV_array[ICP_QAT_FW_NUM_LONGWORDS_4];\n+\t\t\t\tstruct {\n+\t\t\t\t\t\tuint64_t cipher_IV_ptr;\n+\t\t\t\t\t\tuint64_t resrvd1;\n+\t\t\t} s;\n+\n+\t\t} u;\n+};\n #endif\ndiff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex 9411a79301..642e009f28 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -21,6 +21,7 @@ enum qat_device_gen {\n \tQAT_GEN2,\n \tQAT_GEN3,\n \tQAT_GEN4,\n+\tQAT_GEN_LCE,\n \tQAT_N_GENS\n };\n \ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen_lce.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen_lce.c\nnew file mode 100644\nindex 0000000000..3f1668b3d3\n--- /dev/null\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen_lce.c\n@@ -0,0 +1,329 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2024 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev.h>\n+#include <cryptodev_pmd.h>\n+#include \"qat_sym_session.h\"\n+#include \"qat_sym.h\"\n+#include \"qat_asym.h\"\n+#include \"qat_crypto.h\"\n+#include \"qat_crypto_pmd_gens.h\"\n+\n+static struct rte_cryptodev_capabilities qat_sym_crypto_caps_gen_lce[] = {\n+\tQAT_SYM_AEAD_CAP(AES_GCM,\n+\t\tCAP_SET(block_size, 16),\n+\t\tCAP_RNG(key_size, 32, 32, 0), CAP_RNG(digest_size, 16, 16, 0),\n+\t\tCAP_RNG(aad_size, 0, 240, 1), CAP_RNG(iv_size, 12, 12, 0)),\n+\tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n+};\n+\n+static int\n+qat_sgl_add_buffer_gen_lce(void *list_in, uint64_t addr, uint32_t len)\n+{\n+\tstruct qat_sgl *list = (struct qat_sgl *)list_in;\n+\tuint32_t nr;\n+\n+\tnr = list->num_bufs;\n+\n+\tif (nr >= QAT_SYM_SGL_MAX_NUMBER) {\n+\t\tQAT_DP_LOG(ERR, \"Adding %d entry failed, no empty SGL buffer\", nr);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tlist->buffers[nr].len = len;\n+\tlist->buffers[nr].resrvd = 0;\n+\tlist->buffers[nr].addr = addr;\n+\n+\tlist->num_bufs++;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tQAT_DP_LOG(INFO, \"SGL with %d buffers:\", list->num_bufs);\n+\tQAT_DP_LOG(INFO, \"QAT SGL buf %d, len = %d, iova = 0x%012\"PRIx64,\n+\t\tnr, list->buffers[nr].len, list->buffers[nr].addr);\n+#endif\n+\treturn 0;\n+}\n+\n+static int\n+qat_sgl_fill_array_with_mbuf(struct rte_mbuf *buf, int64_t offset,\n+\tvoid *list_in, uint32_t data_len)\n+{\n+\tstruct qat_sgl *list = (struct qat_sgl *)list_in;\n+\tuint32_t nr, buf_len;\n+\tint res = -EINVAL;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tuint32_t start_idx;\n+\tstart_idx = list->num_bufs;\n+#endif\n+\n+\t/* Append to the existing list */\n+\tnr = list->num_bufs;\n+\n+\tfor (buf_len = 0; buf && nr < QAT_SYM_SGL_MAX_NUMBER; buf = buf->next) {\n+\t\tif (offset >= rte_pktmbuf_data_len(buf)) {\n+\t\t\toffset -= rte_pktmbuf_data_len(buf);\n+\t\t\t/* Jump to next mbuf */\n+\t\t\tcontinue;\n+\t\t}\n+\n+\t\tlist->buffers[nr].len = rte_pktmbuf_data_len(buf) - offset;\n+\t\tlist->buffers[nr].resrvd = 0;\n+\t\tlist->buffers[nr].addr = rte_pktmbuf_iova_offset(buf, offset);\n+\n+\t\toffset = 0;\n+\t\tbuf_len += list->buffers[nr].len;\n+\n+\t\tif (buf_len >= data_len) {\n+\t\t\tlist->buffers[nr].len -= buf_len - data_len;\n+\t\t\tres = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t\t++nr;\n+\t}\n+\n+\tif (unlikely(res != 0)) {\n+\t\tif (nr == QAT_SYM_SGL_MAX_NUMBER)\n+\t\t\tQAT_DP_LOG(ERR, \"Exceeded max segments in QAT SGL (%u)\",\n+\t\t\t\tQAT_SYM_SGL_MAX_NUMBER);\n+\t\telse\n+\t\t\tQAT_DP_LOG(ERR, \"Mbuf chain is too short\");\n+\t} else {\n+\n+\t\tlist->num_bufs = ++nr;\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\t\tQAT_DP_LOG(INFO, \"SGL with %d buffers:\", list->num_bufs);\n+\t\tfor (nr = start_idx; nr < list->num_bufs; nr++) {\n+\t\t\tQAT_DP_LOG(INFO, \"QAT SGL buf %d, len = %d, iova = 0x%012\"PRIx64,\n+\t\t\t\tnr, list->buffers[nr].len,\n+\t\t\t\tlist->buffers[nr].addr);\n+\t\t}\n+#endif\n+\t}\n+\n+\treturn res;\n+}\n+\n+static int\n+qat_sym_build_op_aead_gen_lce(void *in_op, struct qat_sym_session *ctx,\n+\tuint8_t *out_msg, void *op_cookie)\n+{\n+\tstruct qat_sym_op_cookie *cookie = op_cookie;\n+\tstruct rte_crypto_op *op = in_op;\n+\tuint64_t digest_phys_addr, aad_phys_addr;\n+\tuint16_t iv_len, aad_len, digest_len, key_len;\n+\tuint32_t cipher_ofs, iv_offset, cipher_len;\n+\tregister struct icp_qat_fw_la_bulk_req *qat_req;\n+\tstruct icp_qat_fw_la_cipher_30_req_params *cipher_param;\n+\tenum icp_qat_hw_cipher_dir dir;\n+\tbool is_digest_adjacent = false;\n+\n+\tif (ctx->qat_cmd != ICP_QAT_FW_LA_CMD_CIPHER ||\n+\t\tctx->qat_cipher_alg != ICP_QAT_HW_CIPHER_ALGO_AES256 ||\n+\t\tctx->qat_mode != ICP_QAT_HW_CIPHER_AEAD_MODE) {\n+\n+\t\tQAT_DP_LOG(ERR, \"Not supported (cmd: %d, alg: %d, mode: %d). \"\n+\t\t\t\"GEN_LCE PMD only supports AES-256 AEAD mode\",\n+\t\t\tctx->qat_cmd, ctx->qat_cipher_alg, ctx->qat_mode);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tqat_req = (struct icp_qat_fw_la_bulk_req *)out_msg;\n+\trte_mov128((uint8_t *)qat_req, (const uint8_t *)&(ctx->fw_req));\n+\tqat_req->comn_mid.opaque_data = (uint64_t)(uintptr_t)op;\n+\tcipher_param = (void *)&qat_req->serv_specif_rqpars;\n+\n+\tdir = ctx->qat_dir;\n+\n+\taad_phys_addr = op->sym->aead.aad.phys_addr;\n+\taad_len = ctx->aad_len;\n+\n+\tiv_offset = ctx->cipher_iv.offset;\n+\tiv_len = ctx->cipher_iv.length;\n+\n+\tcipher_ofs = op->sym->aead.data.offset;\n+\tcipher_len = op->sym->aead.data.length;\n+\n+\tdigest_phys_addr = op->sym->aead.digest.phys_addr;\n+\tdigest_len = ctx->digest_length;\n+\n+\t/* Up to 16B IV can be directly embedded in descriptor.\n+\t * GCM supports only 12B IV for GEN LCE\n+\t */\n+\tif (iv_len != GCM_IV_LENGTH_GEN_LCE) {\n+\t\tQAT_DP_LOG(ERR, \"iv_len: %d not supported. Must be 12B.\",\n+\t\t\tiv_len);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\trte_memcpy(cipher_param->u.cipher_IV_array,\n+\t\trte_crypto_op_ctod_offset(op, uint8_t*, iv_offset),\n+\t\tiv_len);\n+\n+\t/* Always SGL */\n+\tRTE_ASSERT((qat_req->comn_hdr.comn_req_flags &\n+\t\tICP_QAT_FW_SYM_COMM_ADDR_SGL) == 1);\n+\t/* Always inplace */\n+\tRTE_ASSERT(op->sym->m_dst == NULL);\n+\n+\t/* Key buffer address is already programmed by reusing the\n+\t * content-descriptor buffer\n+\t */\n+\tkey_len = ctx->auth_key_length;\n+\n+\tcipher_param->spc_aad_sz = aad_len;\n+\tcipher_param->cipher_length = key_len;\n+\tcipher_param->spc_auth_res_sz = digest_len;\n+\n+\t/* Knowing digest is contiguous to cipher-text helps optimizing SGL */\n+\tif (rte_pktmbuf_iova_offset(op->sym->m_src, cipher_ofs + cipher_len)\n+\t\t== digest_phys_addr)\n+\t\tis_digest_adjacent = true;\n+\n+\t/* SRC-SGL: 3 entries:\n+\t * a) AAD\n+\t * b) cipher\n+\t * c) digest (only for decrypt and buffer is_NOT_adjacent)\n+\t *\n+\t */\n+\tcookie->qat_sgl_src.num_bufs = 0;\n+\tif (aad_len)\n+\t\tqat_sgl_add_buffer_gen_lce(&cookie->qat_sgl_src, aad_phys_addr,\n+\t\t\taad_len);\n+\n+\tif (is_digest_adjacent && dir == ICP_QAT_HW_CIPHER_DECRYPT) {\n+\t\tqat_sgl_fill_array_with_mbuf(op->sym->m_src, cipher_ofs,\n+\t\t\t&cookie->qat_sgl_src,\n+\t\t\tcipher_len + digest_len);\n+\t} else {\n+\t\tqat_sgl_fill_array_with_mbuf(op->sym->m_src, cipher_ofs,\n+\t\t\t&cookie->qat_sgl_src,\n+\t\t\tcipher_len);\n+\n+\t\t/* Digest buffer in decrypt job */\n+\t\tif (dir == ICP_QAT_HW_CIPHER_DECRYPT)\n+\t\t\tqat_sgl_add_buffer_gen_lce(&cookie->qat_sgl_src,\n+\t\t\t\tdigest_phys_addr, digest_len);\n+\t}\n+\n+\t/* (in-place) DST-SGL: 2 entries:\n+\t * a) cipher\n+\t * b) digest (only for encrypt and buffer is_NOT_adjacent)\n+\t */\n+\tcookie->qat_sgl_dst.num_bufs = 0;\n+\n+\tif (is_digest_adjacent && dir == ICP_QAT_HW_CIPHER_ENCRYPT) {\n+\t\tqat_sgl_fill_array_with_mbuf(op->sym->m_src, cipher_ofs,\n+\t\t\t&cookie->qat_sgl_dst,\n+\t\t\tcipher_len + digest_len);\n+\t} else {\n+\t\tqat_sgl_fill_array_with_mbuf(op->sym->m_src, cipher_ofs,\n+\t\t\t&cookie->qat_sgl_dst,\n+\t\t\tcipher_len);\n+\n+\t\t/* Digest buffer in Encrypt job */\n+\t\tif (dir == ICP_QAT_HW_CIPHER_ENCRYPT)\n+\t\t\tqat_sgl_add_buffer_gen_lce(&cookie->qat_sgl_dst,\n+\t\t\t\tdigest_phys_addr, digest_len);\n+\t}\n+\n+\t/* Length values in 128B descriptor */\n+\tqat_req->comn_mid.src_length = cipher_len;\n+\tqat_req->comn_mid.dst_length = cipher_len;\n+\n+\tif (dir == ICP_QAT_HW_CIPHER_ENCRYPT) /* Digest buffer in Encrypt job */\n+\t\tqat_req->comn_mid.dst_length += GCM_256_DIGEST_LEN;\n+\n+\t/* src & dst SGL addresses in 128B descriptor */\n+\tqat_req->comn_mid.src_data_addr = cookie->qat_sgl_src_phys_addr;\n+\tqat_req->comn_mid.dest_data_addr = cookie->qat_sgl_dst_phys_addr;\n+\n+#if RTE_LOG_DP_LEVEL >= RTE_LOG_DEBUG\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"qat_req:\", qat_req,\n+\t\tsizeof(struct icp_qat_fw_la_bulk_req));\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"src_data:\",\n+\t\trte_pktmbuf_mtod(op->sym->m_src, uint8_t*),\n+\t\trte_pktmbuf_data_len(op->sym->m_src));\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"digest:\", op->sym->aead.digest.data,\n+\t\tdigest_len);\n+\tQAT_DP_HEXDUMP_LOG(DEBUG, \"aad:\", op->sym->aead.aad.data, aad_len);\n+#endif\n+\treturn 0;\n+}\n+\n+static int\n+qat_sym_crypto_set_session_gen_lce(void *cdev __rte_unused, void *session)\n+{\n+\tstruct qat_sym_session *ctx = session;\n+\tqat_sym_build_request_t build_request = NULL;\n+\tenum rte_proc_type_t proc_type = rte_eal_process_type();\n+\n+\tif (proc_type == RTE_PROC_AUTO || proc_type == RTE_PROC_INVALID)\n+\t\treturn -EINVAL;\n+\n+\t/* build request for aead */\n+\tif (ctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_AES256 &&\n+\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_GALOIS_128) {\n+\t\tbuild_request = qat_sym_build_op_aead_gen_lce;\n+\t\tctx->build_request[proc_type] = build_request;\n+\t}\n+\treturn 0;\n+}\n+\n+\n+static int\n+qat_sym_crypto_cap_get_gen_lce(struct qat_cryptodev_private *internals,\n+\tconst char *capa_memz_name,\n+\tconst uint16_t __rte_unused slice_map)\n+{\n+\tconst uint32_t size = sizeof(qat_sym_crypto_caps_gen_lce);\n+\tuint32_t i;\n+\n+\tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n+\tif (internals->capa_mz == NULL) {\n+\t\tinternals->capa_mz = rte_memzone_reserve(capa_memz_name,\n+\t\t\tsize, rte_socket_id(), 0);\n+\t\tif (internals->capa_mz == NULL) {\n+\t\t\tQAT_LOG(DEBUG,\n+\t\t\t\t\"Error allocating memzone for capabilities\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tstruct rte_cryptodev_capabilities *addr =\n+\t\t(struct rte_cryptodev_capabilities *)\n+\t\tinternals->capa_mz->addr;\n+\tconst struct rte_cryptodev_capabilities *capabilities =\n+\t\tqat_sym_crypto_caps_gen_lce;\n+\tconst uint32_t capa_num =\n+\t\tsize / sizeof(struct rte_cryptodev_capabilities);\n+\tuint32_t curr_capa = 0;\n+\n+\tfor (i = 0; i < capa_num; i++) {\n+\t\tmemcpy(addr + curr_capa, capabilities + i,\n+\t\t\tsizeof(struct rte_cryptodev_capabilities));\n+\t\tcurr_capa++;\n+\t}\n+\tinternals->qat_dev_capabilities = internals->capa_mz->addr;\n+\n+\treturn 0;\n+}\n+\n+RTE_INIT(qat_sym_crypto_gen_lce_init)\n+{\n+\tqat_sym_gen_dev_ops[QAT_GEN_LCE].cryptodev_ops = &qat_sym_crypto_ops_gen1;\n+\tqat_sym_gen_dev_ops[QAT_GEN_LCE].get_capabilities =\n+\t\t\tqat_sym_crypto_cap_get_gen_lce;\n+\tqat_sym_gen_dev_ops[QAT_GEN_LCE].set_session =\n+\t\t\tqat_sym_crypto_set_session_gen_lce;\n+\tqat_sym_gen_dev_ops[QAT_GEN_LCE].set_raw_dp_ctx = NULL;\n+\tqat_sym_gen_dev_ops[QAT_GEN_LCE].get_feature_flags =\n+\t\t\tqat_sym_crypto_feature_flags_get_gen1;\n+}\n+\n+RTE_INIT(qat_asym_crypto_gen_lce_init)\n+{\n+\tqat_asym_gen_dev_ops[QAT_GEN_LCE].cryptodev_ops = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN_LCE].get_capabilities = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN_LCE].get_feature_flags = NULL;\n+\tqat_asym_gen_dev_ops[QAT_GEN_LCE].set_session = NULL;\n+}\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex f976009bf2..f2f197d050 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -95,6 +95,12 @@\n /* Maximum data length for single pass GMAC: 2^14-1 */\n #define QAT_AES_GMAC_SPC_MAX_SIZE 16383\n \n+/* Digest length for GCM Algo is 16 bytes */\n+#define GCM_256_DIGEST_LEN 16\n+\n+/* IV length for GCM algo is 12 bytes */\n+#define GCM_IV_LENGTH_GEN_LCE 12\n+\n struct qat_sym_session;\n \n struct qat_sym_sgl {\n", "prefixes": [ "v5", "1/4" ] }