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GET /api/patches/137451/?format=api
{ "id": 137451, "url": "http://patchwork.dpdk.org/api/patches/137451/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240228170046.176600-11-dsosnowski@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240228170046.176600-11-dsosnowski@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240228170046.176600-11-dsosnowski@nvidia.com", "date": "2024-02-28T17:00:45", "name": "[10/11] net/mlx5: reuse flow fields", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "b973f5f3f768b6a1279baebce67cbc1f7afc91be", "submitter": { "id": 2386, "url": "http://patchwork.dpdk.org/api/people/2386/?format=api", "name": "Dariusz Sosnowski", "email": "dsosnowski@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240228170046.176600-11-dsosnowski@nvidia.com/mbox/", "series": [ { "id": 31278, "url": "http://patchwork.dpdk.org/api/series/31278/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31278", "date": "2024-02-28T17:00:35", "name": "net/mlx5: flow insertion performance improvements", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31278/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/137451/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/137451/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 8A93743C2C;\n\tWed, 28 Feb 2024 18:03:25 +0100 (CET)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id DAE4A42FC1;\n\tWed, 28 Feb 2024 18:02:06 +0100 (CET)", "from NAM12-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam12on2072.outbound.protection.outlook.com [40.107.243.72])\n by mails.dpdk.org (Postfix) with ESMTP id 3840F42FF1\n for <dev@dpdk.org>; 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helo=mail.nvidia.com; pr=C", "From": "Dariusz Sosnowski <dsosnowski@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>, Ori Kam <orika@nvidia.com>,\n Suanming Mou <suanmingm@nvidia.com>, Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, Raslan Darawsheh <rasland@nvidia.com>, Bing Zhao\n <bingz@nvidia.com>", "Subject": "[PATCH 10/11] net/mlx5: reuse flow fields", "Date": "Wed, 28 Feb 2024 18:00:45 +0100", "Message-ID": "<20240228170046.176600-11-dsosnowski@nvidia.com>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240228170046.176600-1-dsosnowski@nvidia.com>", "References": "<20240228170046.176600-1-dsosnowski@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.230.35]", "X-ClientProxiedBy": "rnnvmail202.nvidia.com (10.129.68.7) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL02EPF0001A103:EE_|MW3PR12MB4587:EE_", "X-MS-Office365-Filtering-Correlation-Id": "cd5368da-fcb0-47de-f9ba-08dc387efb66", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n nRoIt3vOJKUeN5XWUG9/74Tu4DSnqNnx02qIgk4lbbExwjj1WT+tnVQSMyHje+Z7QWgsiyEDJ4PKO3l5yee98FM3D3DpTzsjWf4myHOlHEE7vbth4PIMAUNH+as+rDDMoHj5vHcFRGALJRZ6MFYQ/6QIznw8Nmkpr/RmpBQC0wdzvkxWLpih9IbKL16UQlPTnBIPq/Ut8A+z2OYMF0PRw2KcYqGaE/XF+XBAy5epil3FEHI9OvRmCXHBK7w27shR0rSuNdZLBnSLqyaq9OrYKjeLBq8v2JlFBeObn7FMrgqc0kvJKS6B1aaxyUcgnyIEZPXxAAoSCoFQpy0Oey+UAHC1fXJLECnDjWwEiPa9n19ZnCksFtTrgGh8iExIZje3t6IFPYYARI8xziKKkXhokmc40yRx0B+VOlRx91JdwBoSNA+UHm7h5MqPZelLTxEjAGoqhAnhAHSKtYqGjKzaeO6WDb9bpglNn5G+GlYM+EH+IffeOVNmYPnRbnFZ+su+FaqrFdl9vVP+Z1FtPBmSGtG2x7kzX89mgL5GnbvnvJEewn4FeHp9bxDxXDv+sg5Z4nhKlyHX2lB5MKGjyAU6o8PxDmNAVvetK+CErWMwLqNIxiMECEESR9GBmVvphKK6cC0fRmI9udE52IJMI7LjtFEs/5BZM0ykcQZAdjOHnx3ujJSEw+P/zMUZRdaKHcT4ikKXPijeqbdRM27q6KbvfRQ6Y/mq38RYU3/KKzjRGMa8STG1S7QqRUorr2Jd4pdz", "X-Forefront-Antispam-Report": "CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE;\n SFS:(13230031)(36860700004)(82310400014); DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "28 Feb 2024 17:02:01.1507 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cd5368da-fcb0-47de-f9ba-08dc387efb66", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BL02EPF0001A103.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW3PR12MB4587", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Each time a flow is allocated in mlx5 PMD the whole buffer,\nboth rte_flow_hw and mlx5dr_rule parts, are zeroed.\nThis introduces some wasted work because:\n\n- mlx5dr layer does not assume that mlx5dr_rule must be initialized,\n- flow action translation in mlx5 PMD does not need most of the fields\n of rte_flow_hw to be zeroed.\n\nTo reduce this wasted work, this patch introduces flags field to\nflow definition. Each flow field which is not always initialized\nduring flow creation, will have a correspondent flag set if value is\nvalid (in other words - it was set during flow creation).\nUtilizing this mechanism allows PMD to:\n\n- remove zeroing from flow allocation,\n- access some fields (especially from rte_flow_hw_aux) if and only if\n corresponding flag is set.\n\nSigned-off-by: Dariusz Sosnowski <dsosnowski@nvidia.com>\n---\n drivers/net/mlx5/mlx5_flow.h | 24 ++++++++-\n drivers/net/mlx5/mlx5_flow_hw.c | 93 +++++++++++++++++++++------------\n 2 files changed, 83 insertions(+), 34 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 1c67d8dd35..a01e970d04 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1267,6 +1267,26 @@ enum {\n \tMLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_MOVE,\n };\n \n+enum {\n+\tMLX5_FLOW_HW_FLOW_FLAG_CNT_ID = RTE_BIT32(0),\n+\tMLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP = RTE_BIT32(1),\n+\tMLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ = RTE_BIT32(2),\n+\tMLX5_FLOW_HW_FLOW_FLAG_AGE_IDX = RTE_BIT32(3),\n+\tMLX5_FLOW_HW_FLOW_FLAG_MTR_ID = RTE_BIT32(4),\n+\tMLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR = RTE_BIT32(5),\n+\tMLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW = RTE_BIT32(6),\n+};\n+\n+#define MLX5_FLOW_HW_FLOW_FLAGS_ALL ( \\\n+\t\tMLX5_FLOW_HW_FLOW_FLAG_CNT_ID | \\\n+\t\tMLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP | \\\n+\t\tMLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ | \\\n+\t\tMLX5_FLOW_HW_FLOW_FLAG_AGE_IDX | \\\n+\t\tMLX5_FLOW_HW_FLOW_FLAG_MTR_ID | \\\n+\t\tMLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR | \\\n+\t\tMLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW \\\n+\t)\n+\n #ifdef PEDANTIC\n #pragma GCC diagnostic ignored \"-Wpedantic\"\n #endif\n@@ -1283,8 +1303,8 @@ struct rte_flow_hw {\n \tuint32_t res_idx;\n \t/** HWS flow rule index passed to mlx5dr. */\n \tuint32_t rule_idx;\n-\t/** Fate action type. */\n-\tuint32_t fate_type;\n+\t/** Which flow fields (inline or in auxiliary struct) are used. */\n+\tuint32_t flags;\n \t/** Ongoing flow operation type. */\n \tuint8_t operation_type;\n \t/** Index of pattern template this flow is based on. */\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 3252f76e64..4e4beb4428 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -2832,6 +2832,7 @@ flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,\n \t\t\t\t&rule_act->action,\n \t\t\t\t&rule_act->counter.offset))\n \t\t\treturn -1;\n+\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;\n \t\tflow->cnt_id = act_idx;\n \t\tbreak;\n \tcase MLX5_INDIRECT_ACTION_TYPE_AGE:\n@@ -2841,6 +2842,7 @@ flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,\n \t\t * it in flow destroy.\n \t\t */\n \t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, act_idx);\n+\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;\n \t\tif (action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)\n \t\t\t/*\n \t\t\t * The mutual update for idirect AGE & COUNT will be\n@@ -2856,6 +2858,7 @@ flow_hw_shared_action_construct(struct rte_eth_dev *dev, uint32_t queue,\n \t\t\t\t\t\t ¶m->queue_id, &age_cnt,\n \t\t\t\t\t\t idx) < 0)\n \t\t\t\treturn -1;\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;\n \t\t\tflow->cnt_id = age_cnt;\n \t\t\tparam->nb_cnts++;\n \t\t} else {\n@@ -3160,7 +3163,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\trule_acts[act_data->action_dst].action =\n \t\t\t(!!attr.group) ? jump->hws_action : jump->root_action;\n \t\t\tflow->jump = jump;\n-\t\t\tflow->fate_type = MLX5_FLOW_FATE_JUMP;\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_RSS:\n \t\tcase RTE_FLOW_ACTION_TYPE_QUEUE:\n@@ -3171,7 +3174,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\treturn -1;\n \t\t\trule_acts[act_data->action_dst].action = hrxq->action;\n \t\t\tflow->hrxq = hrxq;\n-\t\t\tflow->fate_type = MLX5_FLOW_FATE_QUEUE;\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ACTION_TYPE_RSS:\n \t\t\titem_flags = table->its[it_idx]->item_flags;\n@@ -3250,7 +3253,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\t\t(!!attr.group) ? jump->hws_action :\n \t\t\t\t\t\t\t jump->root_action;\n \t\t\tflow->jump = jump;\n-\t\t\tflow->fate_type = MLX5_FLOW_FATE_JUMP;\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP;\n \t\t\tif (mlx5_aso_mtr_wait(priv->sh, MLX5_HW_INV_QUEUE, aso_mtr))\n \t\t\t\treturn -1;\n \t\t\tbreak;\n@@ -3270,6 +3273,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\tif (age_idx == 0)\n \t\t\t\treturn -rte_errno;\n \t\t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX;\n \t\t\tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT)\n \t\t\t\t/*\n \t\t\t\t * When AGE uses indirect counter, no need to\n@@ -3292,6 +3296,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\t );\n \t\t\tif (ret != 0)\n \t\t\t\treturn ret;\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;\n \t\t\tflow->cnt_id = cnt_id;\n \t\t\tbreak;\n \t\tcase MLX5_RTE_FLOW_ACTION_TYPE_COUNT:\n@@ -3303,6 +3308,7 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\t );\n \t\t\tif (ret != 0)\n \t\t\t\treturn ret;\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;\n \t\t\tflow->cnt_id = act_data->shared_counter.id;\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_CONNTRACK:\n@@ -3335,13 +3341,18 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\treturn ret;\n \t\t\taux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t\t\tmlx5_flow_hw_aux_set_mtr_id(flow, aux, mtr_idx);\n+\t\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MTR_ID;\n \t\t\tbreak;\n \t\tdefault:\n \t\t\tbreak;\n \t\t}\n \t}\n \tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_COUNT) {\n+\t\t/* If indirect count is used, then CNT_ID flag should be set. */\n+\t\tMLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);\n \t\tif (at->action_flags & MLX5_FLOW_ACTION_INDIRECT_AGE) {\n+\t\t\t/* If indirect AGE is used, then AGE_IDX flag should be set. */\n+\t\t\tMLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX);\n \t\t\taux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t\t\tage_idx = mlx5_flow_hw_aux_get_age_idx(flow, aux) &\n \t\t\t\t MLX5_HWS_AGE_IDX_MASK;\n@@ -3379,8 +3390,10 @@ flow_hw_actions_construct(struct rte_eth_dev *dev,\n \t\t\t\tflow->res_idx - 1;\n \t\trule_acts[hw_acts->push_remove_pos].ipv6_ext.header = ap->ipv6_push_data;\n \t}\n-\tif (mlx5_hws_cnt_id_valid(hw_acts->cnt_id))\n+\tif (mlx5_hws_cnt_id_valid(hw_acts->cnt_id)) {\n+\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_CNT_ID;\n \t\tflow->cnt_id = hw_acts->cnt_id;\n+\t}\n \treturn 0;\n }\n \n@@ -3493,7 +3506,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t\t \"Port must be started before enqueueing flow operations\");\n \t\treturn NULL;\n \t}\n-\tflow = mlx5_ipool_zmalloc(table->flow, &flow_idx);\n+\tflow = mlx5_ipool_malloc(table->flow, &flow_idx);\n \tif (!flow)\n \t\tgoto error;\n \trule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);\n@@ -3512,6 +3525,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t} else {\n \t\tflow->res_idx = flow_idx;\n \t}\n+\tflow->flags = 0;\n \t/*\n \t * Set the flow operation type here in order to know if the flow memory\n \t * should be freed or not when get the result from dequeue.\n@@ -3563,6 +3577,7 @@ flow_hw_async_flow_create(struct rte_eth_dev *dev,\n \t\t\t\t\t (struct mlx5dr_rule *)flow->rule);\n \t\trte_rwlock_read_unlock(&table->matcher_replace_rwlk);\n \t\taux->matcher_selector = selector;\n+\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;\n \t}\n \tif (likely(!ret)) {\n \t\tflow_hw_q_inc_flow_ops(priv, queue);\n@@ -3636,7 +3651,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,\n \t\t\t\t \"Flow rule index exceeds table size\");\n \t\treturn NULL;\n \t}\n-\tflow = mlx5_ipool_zmalloc(table->flow, &flow_idx);\n+\tflow = mlx5_ipool_malloc(table->flow, &flow_idx);\n \tif (!flow)\n \t\tgoto error;\n \trule_acts = flow_hw_get_dr_action_buffer(priv, table, action_template_index, queue);\n@@ -3655,6 +3670,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,\n \t} else {\n \t\tflow->res_idx = flow_idx;\n \t}\n+\tflow->flags = 0;\n \t/*\n \t * Set the flow operation type here in order to know if the flow memory\n \t * should be freed or not when get the result from dequeue.\n@@ -3696,6 +3712,7 @@ flow_hw_async_flow_create_by_index(struct rte_eth_dev *dev,\n \t\t\t\t\t (struct mlx5dr_rule *)flow->rule);\n \t\trte_rwlock_read_unlock(&table->matcher_replace_rwlk);\n \t\taux->matcher_selector = selector;\n+\t\tflow->flags |= MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR;\n \t}\n \tif (likely(!ret)) {\n \t\tflow_hw_q_inc_flow_ops(priv, queue);\n@@ -3783,6 +3800,7 @@ flow_hw_async_flow_update(struct rte_eth_dev *dev,\n \t} else {\n \t\tnf->res_idx = of->res_idx;\n \t}\n+\tnf->flags = 0;\n \t/* Indicate the construction function to set the proper fields. */\n \tnf->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;\n \t/*\n@@ -3812,6 +3830,7 @@ flow_hw_async_flow_update(struct rte_eth_dev *dev,\n \t */\n \tof->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE;\n \tof->user_data = user_data;\n+\tof->flags |= MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW;\n \trule_attr.user_data = of;\n \tret = mlx5dr_rule_action_update((struct mlx5dr_rule *)of->rule,\n \t\t\t\t\taction_template_index, rule_acts, &rule_attr);\n@@ -3906,13 +3925,14 @@ flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,\n \tuint32_t *cnt_queue;\n \tuint32_t age_idx = aux->orig.age_idx;\n \n+\tMLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID);\n \tif (mlx5_hws_cnt_is_shared(priv->hws_cpool, flow->cnt_id)) {\n-\t\tif (age_idx && !mlx5_hws_age_is_indirect(age_idx)) {\n+\t\tif ((flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) &&\n+\t\t !mlx5_hws_age_is_indirect(age_idx)) {\n \t\t\t/* Remove this AGE parameter from indirect counter. */\n \t\t\tmlx5_hws_cnt_age_set(priv->hws_cpool, flow->cnt_id, 0);\n \t\t\t/* Release the AGE parameter. */\n \t\t\tmlx5_hws_age_action_destroy(priv, age_idx, error);\n-\t\t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, 0);\n \t\t}\n \t\treturn;\n \t}\n@@ -3920,8 +3940,7 @@ flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,\n \tcnt_queue = mlx5_hws_cnt_is_pool_shared(priv) ? NULL : &queue;\n \t/* Put the counter first to reduce the race risk in BG thread. */\n \tmlx5_hws_cnt_pool_put(priv->hws_cpool, cnt_queue, &flow->cnt_id);\n-\tflow->cnt_id = 0;\n-\tif (age_idx) {\n+\tif (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX) {\n \t\tif (mlx5_hws_age_is_indirect(age_idx)) {\n \t\t\tuint32_t idx = age_idx & MLX5_HWS_AGE_IDX_MASK;\n \n@@ -3930,7 +3949,6 @@ flow_hw_age_count_release(struct mlx5_priv *priv, uint32_t queue,\n \t\t\t/* Release the AGE parameter. */\n \t\t\tmlx5_hws_age_action_destroy(priv, age_idx, error);\n \t\t}\n-\t\tmlx5_flow_hw_aux_set_age_idx(flow, aux, age_idx);\n \t}\n }\n \n@@ -4060,34 +4078,35 @@ hw_cmpl_flow_update_or_destroy(struct rte_eth_dev *dev,\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct mlx5_aso_mtr_pool *pool = priv->hws_mpool;\n \tstruct rte_flow_template_table *table = flow->table;\n-\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n \t/* Release the original resource index in case of update. */\n \tuint32_t res_idx = flow->res_idx;\n \n-\tif (flow->fate_type == MLX5_FLOW_FATE_JUMP)\n-\t\tflow_hw_jump_release(dev, flow->jump);\n-\telse if (flow->fate_type == MLX5_FLOW_FATE_QUEUE)\n-\t\tmlx5_hrxq_obj_release(dev, flow->hrxq);\n-\tif (mlx5_hws_cnt_id_valid(flow->cnt_id))\n-\t\tflow_hw_age_count_release(priv, queue,\n-\t\t\t\t\t flow, error);\n-\tif (aux->orig.mtr_id) {\n-\t\tmlx5_ipool_free(pool->idx_pool,\taux->orig.mtr_id);\n-\t\taux->orig.mtr_id = 0;\n-\t}\n-\tif (flow->operation_type != MLX5_FLOW_HW_FLOW_OP_TYPE_UPDATE) {\n-\t\tif (table->resource)\n-\t\t\tmlx5_ipool_free(table->resource, res_idx);\n-\t\tmlx5_ipool_free(table->flow, flow->idx);\n-\t} else {\n+\tif (flow->flags & MLX5_FLOW_HW_FLOW_FLAGS_ALL) {\n \t\tstruct rte_flow_hw_aux *aux = mlx5_flow_hw_aux(dev->data->port_id, flow);\n-\t\tstruct rte_flow_hw *upd_flow = &aux->upd_flow;\n \n-\t\trte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));\n-\t\taux->orig = aux->upd;\n-\t\tflow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;\n+\t\tif (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_JUMP)\n+\t\t\tflow_hw_jump_release(dev, flow->jump);\n+\t\telse if (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_FATE_HRXQ)\n+\t\t\tmlx5_hrxq_obj_release(dev, flow->hrxq);\n+\t\tif (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID)\n+\t\t\tflow_hw_age_count_release(priv, queue, flow, error);\n+\t\tif (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MTR_ID)\n+\t\t\tmlx5_ipool_free(pool->idx_pool, aux->orig.mtr_id);\n+\t\tif (flow->flags & MLX5_FLOW_HW_FLOW_FLAG_UPD_FLOW) {\n+\t\t\tstruct rte_flow_hw *upd_flow = &aux->upd_flow;\n+\n+\t\t\trte_memcpy(flow, upd_flow, offsetof(struct rte_flow_hw, rule));\n+\t\t\taux->orig = aux->upd;\n+\t\t\tflow->operation_type = MLX5_FLOW_HW_FLOW_OP_TYPE_CREATE;\n+\t\t\tif (table->resource)\n+\t\t\t\tmlx5_ipool_free(table->resource, res_idx);\n+\t\t}\n+\t}\n+\tif (flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_DESTROY ||\n+\t flow->operation_type == MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_DESTROY) {\n \t\tif (table->resource)\n \t\t\tmlx5_ipool_free(table->resource, res_idx);\n+\t\tmlx5_ipool_free(table->flow, flow->idx);\n \t}\n }\n \n@@ -4102,6 +4121,7 @@ hw_cmpl_resizable_tbl(struct rte_eth_dev *dev,\n \tuint32_t selector = aux->matcher_selector;\n \tuint32_t other_selector = (selector + 1) & 1;\n \n+\tMLX5_ASSERT(flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);\n \tswitch (flow->operation_type) {\n \tcase MLX5_FLOW_HW_FLOW_OP_TYPE_RSZ_TBL_CREATE:\n \t\trte_atomic_fetch_add_explicit\n@@ -11275,10 +11295,18 @@ flow_hw_query(struct rte_eth_dev *dev, struct rte_flow *flow,\n \t\tcase RTE_FLOW_ACTION_TYPE_VOID:\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_COUNT:\n+\t\t\tif (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_CNT_ID))\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\t\t\t \"counter not defined in the rule\");\n \t\t\tret = flow_hw_query_counter(dev, hw_flow->cnt_id, data,\n \t\t\t\t\t\t error);\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ACTION_TYPE_AGE:\n+\t\t\tif (!(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_AGE_IDX))\n+\t\t\t\treturn rte_flow_error_set(error, EINVAL,\n+\t\t\t\t\t\t\t RTE_FLOW_ERROR_TYPE_UNSPECIFIED, NULL,\n+\t\t\t\t\t\t\t \"age data not available\");\n \t\t\taux = mlx5_flow_hw_aux(dev->data->port_id, hw_flow);\n \t\t\tret = flow_hw_query_age(dev, mlx5_flow_hw_aux_get_age_idx(hw_flow, aux),\n \t\t\t\t\t\tdata, error);\n@@ -12571,6 +12599,7 @@ flow_hw_update_resized(struct rte_eth_dev *dev, uint32_t queue,\n \t\t.burst = attr->postpone,\n \t};\n \n+\tMLX5_ASSERT(hw_flow->flags & MLX5_FLOW_HW_FLOW_FLAG_MATCHER_SELECTOR);\n \t/**\n \t * mlx5dr_matcher_resize_rule_move() accepts original table matcher -\n \t * the one that was used BEFORE table resize.\n", "prefixes": [ "10/11" ] }