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GET /api/patches/139650/?format=api
{ "id": 139650, "url": "http://patchwork.dpdk.org/api/patches/139650/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/27bc50509a27b3a9e9a31aa5d25c388c8b14bbd5.1713964708.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<27bc50509a27b3a9e9a31aa5d25c388c8b14bbd5.1713964708.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/27bc50509a27b3a9e9a31aa5d25c388c8b14bbd5.1713964708.git.anatoly.burakov@intel.com", "date": "2024-04-24T13:21:39", "name": "[v1,05/22] net/ixgbe/base: correct registers names to match datasheet", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "2642b09c25123d6dacb0541bfd152cc6de8cc1dd", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Anatoly Burakov", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 10, "url": "http://patchwork.dpdk.org/api/users/10/?format=api", "username": "bruce", "first_name": "Bruce", "last_name": "Richardson", "email": "bruce.richardson@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/27bc50509a27b3a9e9a31aa5d25c388c8b14bbd5.1713964708.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 31814, "url": "http://patchwork.dpdk.org/api/series/31814/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31814", "date": "2024-04-24T13:21:34", "name": "Update IXGBE base driver", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31814/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139650/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/139650/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1B31143EAD;\n\tWed, 24 Apr 2024 15:22:53 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 1D48A43491;\n\tWed, 24 Apr 2024 15:22:27 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.9])\n by mails.dpdk.org (Postfix) with ESMTP id 615FA4348A\n for <dev@dpdk.org>; Wed, 24 Apr 2024 15:22:25 +0200 (CEST)", "from fmviesa006.fm.intel.com ([10.60.135.146])\n by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 24 Apr 2024 06:22:25 -0700", "from silpixa00401119.ir.intel.com ([10.55.129.167])\n by fmviesa006.fm.intel.com with ESMTP; 24 Apr 2024 06:22:22 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1713964946; x=1745500946;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=BaBny1Z8ptqio0BlU3BiQ92uVV0ZoBM8AzX759r7Y3g=;\n b=OCc3ufJ6PdJ49WTeB8PQxM8mkjfAde/If79fjuHtK6MOl2HjbQMlW+B/\n MxLEvxU4kI4uAGZhxVIvBTRFAHCxU0kzCPwX4/WrK8YZjaoI6ihK+XntL\n ahLdVuWltWt/OFtnSlC/KKFRlYzsb59G0CvO4q1hVNrOKiCi2N9N28YOP\n 5QeQ6076u3PpJtC5J5Ffri8iVAfrjiGEuR0jx5bh6diN24+JB9CvB2/ll\n jR7M4YpABzJWvdO5Jyjjck5dZckl0CighMP+x1UKQ/X1y0sfzPg+tawLJ\n 75EeQJ1iOpIGvguuTBp2dOfRhXVohv6U/DHa+9OQoMxPZc6tDSDx1QQ00 w==;", "X-CSE-ConnectionGUID": [ "C4+Tkx9IQIuFujuGYHulxw==", "/qHScdwcSNKuI+YTHeqsig==" ], "X-CSE-MsgGUID": [ "HVa3UXgXSAujzPON2VPHKg==", "OOUGbir6SjueG7z+5FQ1yg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11054\"; a=\"20289252\"", "E=Sophos;i=\"6.07,226,1708416000\"; d=\"scan'208\";a=\"20289252\"", "E=Sophos;i=\"6.07,226,1708416000\"; d=\"scan'208\";a=\"24749328\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Jakub Chylkowski <jakubx.chylkowski@intel.com>,\n\tvladimir.medvedkin@intel.com, bruce.richardson@intel.com,\n\tZalfresso-jundzillo@dpdk.org,\n\tMarekX <marekx.zalfresso-jundzillo@intel.com>, Michael@dpdk.org,\n\tAlice <alice.michael@intel.com>, Skajewski@dpdk.org,\n\tPiotrX <piotrx.skajewski@intel.com>, Mrozowicz@dpdk.org,\n\tSlawomirX <slawomirx.mrozowicz@intel.com>", "Subject": "[PATCH v1 05/22] net/ixgbe/base: correct registers names to match\n datasheet", "Date": "Wed, 24 Apr 2024 14:21:39 +0100", "Message-ID": "\n <27bc50509a27b3a9e9a31aa5d25c388c8b14bbd5.1713964708.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1713964707.git.anatoly.burakov@intel.com>", "References": "<cover.1713964707.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Jakub Chylkowski <jakubx.chylkowski@intel.com>\n\nSome of mailbox-related registers have different names than it is\nspecified in datasheet. Correct these names to correspond to their\ndatasheet counterparts. Additionally, several calculations are changed\nto no longer use magic numbers but dedicated macros instead.\n\nSigned-off-by: Jakub Chylkowski <jakubx.chylkowski@intel.com>\nReviewed-by: Zalfresso-jundzillo, MarekX <marekx.zalfresso-jundzillo@intel.com>\nReviewed-by: Michael, Alice <alice.michael@intel.com>\nReviewed-by: Skajewski, PiotrX <piotrx.skajewski@intel.com>\nTested-by: Skajewski, PiotrX <piotrx.skajewski@intel.com>\nReviewed-by: Mrozowicz, SlawomirX <slawomirx.mrozowicz@intel.com>\nTested-by: Michael, Alice <alice.michael@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_mbx.c | 30 ++++++++++++++---------------\n drivers/net/ixgbe/base/ixgbe_mbx.h | 8 ++++----\n drivers/net/ixgbe/base/ixgbe_type.h | 12 ++++++------\n 3 files changed, 25 insertions(+), 25 deletions(-)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_mbx.c b/drivers/net/ixgbe/base/ixgbe_mbx.c\nindex 4dddff2c58..d645dcf827 100644\n--- a/drivers/net/ixgbe/base/ixgbe_mbx.c\n+++ b/drivers/net/ixgbe/base/ixgbe_mbx.c\n@@ -496,12 +496,12 @@ void ixgbe_init_mbx_params_vf(struct ixgbe_hw *hw)\n \n STATIC s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)\n {\n-\tu32 mbvficr = IXGBE_READ_REG(hw, IXGBE_MBVFICR(index));\n+\tu32 pfmbicr = IXGBE_READ_REG(hw, IXGBE_PFMBICR(index));\n \ts32 ret_val = IXGBE_ERR_MBX;\n \n-\tif (mbvficr & mask) {\n+\tif (pfmbicr & mask) {\n \t\tret_val = IXGBE_SUCCESS;\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_MBVFICR(index), mask);\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_PFMBICR(index), mask);\n \t}\n \n \treturn ret_val;\n@@ -516,13 +516,13 @@ STATIC s32 ixgbe_check_for_bit_pf(struct ixgbe_hw *hw, u32 mask, s32 index)\n **/\n STATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n+\tu32 vf_shift = IXGBE_PFMBICR_SHIFT(vf_number);\n+\ts32 index = IXGBE_PFMBICR_INDEX(vf_number);\n \ts32 ret_val = IXGBE_ERR_MBX;\n-\ts32 index = IXGBE_MBVFICR_INDEX(vf_number);\n-\tu32 vf_bit = vf_number % 16;\n \n \tDEBUGFUNC(\"ixgbe_check_for_msg_pf\");\n \n-\tif (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFREQ_VF1 << vf_bit,\n+\tif (!ixgbe_check_for_bit_pf(hw, IXGBE_PFMBICR_VFREQ_VF1 << vf_shift,\n \t\t\t\t index)) {\n \t\tret_val = IXGBE_SUCCESS;\n \t\thw->mbx.stats.reqs++;\n@@ -540,13 +540,13 @@ STATIC s32 ixgbe_check_for_msg_pf(struct ixgbe_hw *hw, u16 vf_number)\n **/\n STATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n+\tu32 vf_shift = IXGBE_PFMBICR_SHIFT(vf_number);\n+\ts32 index = IXGBE_PFMBICR_INDEX(vf_number);\n \ts32 ret_val = IXGBE_ERR_MBX;\n-\ts32 index = IXGBE_MBVFICR_INDEX(vf_number);\n-\tu32 vf_bit = vf_number % 16;\n \n \tDEBUGFUNC(\"ixgbe_check_for_ack_pf\");\n \n-\tif (!ixgbe_check_for_bit_pf(hw, IXGBE_MBVFICR_VFACK_VF1 << vf_bit,\n+\tif (!ixgbe_check_for_bit_pf(hw, IXGBE_PFMBICR_VFACK_VF1 << vf_shift,\n \t\t\t\t index)) {\n \t\tret_val = IXGBE_SUCCESS;\n \t\thw->mbx.stats.acks++;\n@@ -564,22 +564,22 @@ STATIC s32 ixgbe_check_for_ack_pf(struct ixgbe_hw *hw, u16 vf_number)\n **/\n STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)\n {\n-\tu32 reg_offset = (vf_number < 32) ? 0 : 1;\n-\tu32 vf_shift = vf_number % 32;\n+\tu32 vf_shift = IXGBE_PFVFLRE_SHIFT(vf_number);\n+\tu32 index = IXGBE_PFVFLRE_INDEX(vf_number);\n+\ts32 ret_val = IXGBE_ERR_MBX;\n \tu32 vflre = 0;\n-\ts32 ret_val = IXGBE_ERR_MBX;\n \n \tDEBUGFUNC(\"ixgbe_check_for_rst_pf\");\n \n \tswitch (hw->mac.type) {\n \tcase ixgbe_mac_82599EB:\n-\t\tvflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset));\n+\t\tvflre = IXGBE_READ_REG(hw, IXGBE_PFVFLRE(index));\n \t\tbreak;\n \tcase ixgbe_mac_X550:\n \tcase ixgbe_mac_X550EM_x:\n \tcase ixgbe_mac_X550EM_a:\n \tcase ixgbe_mac_X540:\n-\t\tvflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset));\n+\t\tvflre = IXGBE_READ_REG(hw, IXGBE_PFVFLREC(index));\n \t\tbreak;\n \tdefault:\n \t\tbreak;\n@@ -587,7 +587,7 @@ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_number)\n \n \tif (vflre & (1 << vf_shift)) {\n \t\tret_val = IXGBE_SUCCESS;\n-\t\tIXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift));\n+\t\tIXGBE_WRITE_REG(hw, IXGBE_PFVFLREC(index), (1 << vf_shift));\n \t\thw->mbx.stats.rsts++;\n \t}\n \ndiff --git a/drivers/net/ixgbe/base/ixgbe_mbx.h b/drivers/net/ixgbe/base/ixgbe_mbx.h\nindex 28a2d94d02..f7861e6bde 100644\n--- a/drivers/net/ixgbe/base/ixgbe_mbx.h\n+++ b/drivers/net/ixgbe/base/ixgbe_mbx.h\n@@ -30,10 +30,10 @@\n #define IXGBE_PFMAILBOX_PFU\t0x00000008 /* PF owns the mailbox buffer */\n #define IXGBE_PFMAILBOX_RVFU\t0x00000010 /* Reset VFU - used when VF stuck */\n \n-#define IXGBE_MBVFICR_VFREQ_MASK\t0x0000FFFF /* bits for VF messages */\n-#define IXGBE_MBVFICR_VFREQ_VF1\t\t0x00000001 /* bit for VF 1 message */\n-#define IXGBE_MBVFICR_VFACK_MASK\t0xFFFF0000 /* bits for VF acks */\n-#define IXGBE_MBVFICR_VFACK_VF1\t\t0x00010000 /* bit for VF 1 ack */\n+#define IXGBE_PFMBICR_VFREQ_MASK\t0x0000FFFF /* bits for VF messages */\n+#define IXGBE_PFMBICR_VFREQ_VF1\t\t0x00000001 /* bit for VF 1 message */\n+#define IXGBE_PFMBICR_VFACK_MASK\t0xFFFF0000 /* bits for VF acks */\n+#define IXGBE_PFMBICR_VFACK_VF1\t\t0x00010000 /* bit for VF 1 ack */\n \n \n /* If it's a IXGBE_VF_* msg then it originates in the VF and is sent to the\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex f709681df2..5036b2a907 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -451,8 +451,14 @@ struct ixgbe_nvm_version {\n #define IXGBE_PFMAILBOX(_i)\t(0x04B00 + (4 * (_i))) /* 64 total */\n /* 64 Mailboxes, 16 DW each */\n #define IXGBE_PFMBMEM(_i)\t(0x13000 + (64 * (_i)))\n+#define IXGBE_PFMBICR_INDEX(_i)\t((_i) >> 4)\n+#define IXGBE_PFMBICR_SHIFT(_i)\t((_i) % 16)\n #define IXGBE_PFMBICR(_i)\t(0x00710 + (4 * (_i))) /* 4 total */\n #define IXGBE_PFMBIMR(_i)\t(0x00720 + (4 * (_i))) /* 4 total */\n+#define IXGBE_PFVFLRE(_i)\t((((_i) & 1) ? 0x001C0 : 0x00600))\n+#define IXGBE_PFVFLREC(_i)\t(0x00700 + ((_i) * 4))\n+#define IXGBE_PFVFLRE_INDEX(_i)\t((_i) >> 5)\n+#define IXGBE_PFVFLRE_SHIFT(_i)\t((_i) % 32)\n #define IXGBE_VFRE(_i)\t\t(0x051E0 + ((_i) * 4))\n #define IXGBE_VFTE(_i)\t\t(0x08110 + ((_i) * 4))\n #define IXGBE_VMECM(_i)\t\t(0x08790 + ((_i) * 4))\n@@ -2866,12 +2872,6 @@ enum {\n #define IXGBE_RX_DESC_SPECIAL_PRI_MASK\t0xE000 /* Priority in upper 3 bits */\n #define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT\t0x000D /* Priority in upper 3 of 16 */\n #define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT\tIXGBE_RX_DESC_SPECIAL_PRI_SHIFT\n-\n-/* SR-IOV specific macros */\n-#define IXGBE_MBVFICR_INDEX(vf_number)\t(vf_number >> 4)\n-#define IXGBE_MBVFICR(_i)\t\t(0x00710 + ((_i) * 4))\n-#define IXGBE_VFLRE(_i)\t\t\t(((_i & 1) ? 0x001C0 : 0x00600))\n-#define IXGBE_VFLREC(_i)\t\t (0x00700 + ((_i) * 4))\n /* Translated register #defines */\n #define IXGBE_PVFCTRL(P)\t(0x00300 + (4 * (P)))\n #define IXGBE_PVFSTATUS(P)\t(0x00008 + (0 * (P)))\n", "prefixes": [ "v1", "05/22" ] }