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{
    "id": 139667,
    "url": "http://patchwork.dpdk.org/api/patches/139667/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/9dc7b80e7c3542323ab1d0d22ab96a882abb7fff.1713964708.git.anatoly.burakov@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<9dc7b80e7c3542323ab1d0d22ab96a882abb7fff.1713964708.git.anatoly.burakov@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/9dc7b80e7c3542323ab1d0d22ab96a882abb7fff.1713964708.git.anatoly.burakov@intel.com",
    "date": "2024-04-24T13:21:56",
    "name": "[v1,22/22] net/ixgbe/base: add support for E610 device",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": false,
    "hash": "e84851013aafcd0b228cfc077100c53c51bad86b",
    "submitter": {
        "id": 4,
        "url": "http://patchwork.dpdk.org/api/people/4/?format=api",
        "name": "Anatoly Burakov",
        "email": "anatoly.burakov@intel.com"
    },
    "delegate": {
        "id": 10,
        "url": "http://patchwork.dpdk.org/api/users/10/?format=api",
        "username": "bruce",
        "first_name": "Bruce",
        "last_name": "Richardson",
        "email": "bruce.richardson@intel.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/9dc7b80e7c3542323ab1d0d22ab96a882abb7fff.1713964708.git.anatoly.burakov@intel.com/mbox/",
    "series": [
        {
            "id": 31814,
            "url": "http://patchwork.dpdk.org/api/series/31814/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31814",
            "date": "2024-04-24T13:21:34",
            "name": "Update IXGBE base driver",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/31814/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/139667/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/139667/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "X-ExtLoop1": "1",
        "From": "Anatoly Burakov <anatoly.burakov@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Stefan Wegrzyn <stefan.wegrzyn@intel.com>,\n\tvladimir.medvedkin@intel.com, bruce.richardson@intel.com,\n\tAndrii Staikov <andrii.staikov@intel.com>,\n\tAndrzej Komor <andrzejx.komor@intel.com>,\n\tArtur Tyminski <arturx.tyminski@intel.com>,\n\tBartosz Jakub Rosadzinski <bartosz.jakub.rosadzinski@intel.com>,\n\tBrzezinski@dpdk.org, Filip <filip.brzezinski@intel.com>,\n\tCarolyn Wyborny <carolyn.wyborny@intel.com>,\n\tChinh Cao <chinh.t.cao@intel.com>,\n\tDawid Zielinski <dawid.zielinski@intel.com>,\n\tEryk Rybak <eryk.roch.rybak@intel.com>,\n\tFabio Pricoco <fabio.pricoco@intel.com>,\n\tJedrzej Jagielski <jedrzej.jagielski@intel.com>,\n\tJulian Grajkowski <julianx.grajkowski@intel.com>,\n\tKrzysztof Galazka <krzysztof.galazka@intel.com>,\n\tLeszek Zygo <leszek.zygo@intel.com>,\n\tMical MarekX <marekx.mical@intel.com>,\n\tMilosz Szymonek <milosz.szymonek@intel.com>,\n\tPawel Malinowski <pawel.malinowski@intel.com>,\n\tPiotr Kubaj <piotrx.kubaj@intel.com>,\n\tPiotr Skajewski <piotrx.skajewski@intel.com>,\n\tSlawomir Mrozowicz <slawomirx.mrozowicz@intel.com>,\n\tYogesh Bhosale <yogesh.bhosale@intel.com>",
        "Subject": "[PATCH v1 22/22] net/ixgbe/base: add support for E610 device",
        "Date": "Wed, 24 Apr 2024 14:21:56 +0100",
        "Message-ID": "\n <9dc7b80e7c3542323ab1d0d22ab96a882abb7fff.1713964708.git.anatoly.burakov@intel.com>",
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    },
    "content": "From: Stefan Wegrzyn <stefan.wegrzyn@intel.com>\n\nThis patch adds support for E610 device to the ixgbe driver. This is a\nsquashed commit from internal development tree.\n\nSigned-off-by: Andrii Staikov <andrii.staikov@intel.com>\nSigned-off-by: Andrzej Komor <andrzejx.komor@intel.com>\nSigned-off-by: Artur Tyminski <arturx.tyminski@intel.com>\nSigned-off-by: Bartosz Jakub Rosadzinski <bartosz.jakub.rosadzinski@intel.com>\nSigned-off-by: Brzezinski, Filip <filip.brzezinski@intel.com>\nSigned-off-by: Carolyn Wyborny <carolyn.wyborny@intel.com>\nSigned-off-by: Chinh Cao <chinh.t.cao@intel.com>\nSigned-off-by: Dawid Zielinski <dawid.zielinski@intel.com>\nSigned-off-by: Eryk Rybak <eryk.roch.rybak@intel.com>\nSigned-off-by: Fabio Pricoco <fabio.pricoco@intel.com>\nSigned-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>\nSigned-off-by: Julian Grajkowski <julianx.grajkowski@intel.com>\nSigned-off-by: Krzysztof Galazka <krzysztof.galazka@intel.com>\nSigned-off-by: Leszek Zygo <leszek.zygo@intel.com>\nSigned-off-by: Mical MarekX <marekx.mical@intel.com>\nSigned-off-by: Milosz Szymonek <milosz.szymonek@intel.com>\nSigned-off-by: Pawel Malinowski <pawel.malinowski@intel.com>\nSigned-off-by: Piotr Kubaj <piotrx.kubaj@intel.com>\nSigned-off-by: Piotr Skajewski <piotrx.skajewski@intel.com>\nSigned-off-by: Slawomir Mrozowicz <slawomirx.mrozowicz@intel.com>\nSigned-off-by: Stefan Wegrzyn <stefan.wegrzyn@intel.com>\nSigned-off-by: Yogesh Bhosale <yogesh.bhosale@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n drivers/net/ixgbe/base/README            |    6 +-\n drivers/net/ixgbe/base/ixgbe_82599.c     |    5 +-\n drivers/net/ixgbe/base/ixgbe_api.c       |   58 +-\n drivers/net/ixgbe/base/ixgbe_api.h       |    5 +-\n drivers/net/ixgbe/base/ixgbe_common.c    |   29 +-\n drivers/net/ixgbe/base/ixgbe_e610.c      | 4982 ++++++++++++++++++++++\n drivers/net/ixgbe/base/ixgbe_e610.h      |  163 +\n drivers/net/ixgbe/base/ixgbe_hv_vf.c     |    3 +-\n drivers/net/ixgbe/base/ixgbe_mbx.c       |    3 +\n drivers/net/ixgbe/base/ixgbe_osdep.c     |   43 +\n drivers/net/ixgbe/base/ixgbe_osdep.h     |   17 +\n drivers/net/ixgbe/base/ixgbe_phy.c       |    4 +-\n drivers/net/ixgbe/base/ixgbe_type.h      |   65 +-\n drivers/net/ixgbe/base/ixgbe_type_e610.h | 2181 ++++++++++\n drivers/net/ixgbe/base/meson.build       |    2 +\n 15 files changed, 7547 insertions(+), 19 deletions(-)\n create mode 100644 drivers/net/ixgbe/base/ixgbe_e610.c\n create mode 100644 drivers/net/ixgbe/base/ixgbe_e610.h\n create mode 100644 drivers/net/ixgbe/base/ixgbe_osdep.c\n create mode 100644 drivers/net/ixgbe/base/ixgbe_type_e610.h",
    "diff": "diff --git a/drivers/net/ixgbe/base/README b/drivers/net/ixgbe/base/README\nindex 2c74693924..98353ba26f 100644\n--- a/drivers/net/ixgbe/base/README\n+++ b/drivers/net/ixgbe/base/README\n@@ -1,12 +1,12 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2010-2020 Intel Corporation\n+ * Copyright(c) 2010-2024 Intel Corporation\n  */\n \n Intel® IXGBE driver\n ===================\n \n This directory contains source code of FreeBSD ixgbe driver of version\n-not-released-cid-ixgbe.2020.06.09.tar.gz released by the team which develop\n+not-released-cid-ixgbe.2024.04.24.tar.gz released by the team which develop\n basic drivers for any ixgbe NIC. The sub-directory of base/\n contains the original source package.\n This driver is valid for the product(s) listed below\n@@ -24,6 +24,7 @@ This driver is valid for the product(s) listed below\n * Intel® Ethernet Server Adapter X520 Series\n * Intel® Ethernet Server Adapter X520-T2\n * Intel® Ethernet Controller X550 Series\n+* Intel® Ethernet Controller E610 Series\n \n Updating the driver\n ===================\n@@ -32,3 +33,4 @@ NOTE: The source code in this directory should not be modified apart from\n the following file(s):\n \n     ixgbe_osdep.h\n+    ixgbe_osdep.c\ndiff --git a/drivers/net/ixgbe/base/ixgbe_82599.c b/drivers/net/ixgbe/base/ixgbe_82599.c\nindex 562034b242..419fec689e 100644\n--- a/drivers/net/ixgbe/base/ixgbe_82599.c\n+++ b/drivers/net/ixgbe/base/ixgbe_82599.c\n@@ -1389,7 +1389,8 @@ void ixgbe_set_fdir_drop_queue_82599(struct ixgbe_hw *hw, u8 dropqueue)\n \tfdirctrl |= (dropqueue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);\n \tif ((hw->mac.type == ixgbe_mac_X550) ||\n \t    (hw->mac.type == ixgbe_mac_X550EM_x) ||\n-\t    (hw->mac.type == ixgbe_mac_X550EM_a))\n+\t    (hw->mac.type == ixgbe_mac_X550EM_a) ||\n+\t    (hw->mac.type == ixgbe_mac_E610))\n \t\tfdirctrl |= IXGBE_FDIRCTRL_DROP_NO_MATCH;\n \n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,\n@@ -1804,6 +1805,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \t\tcase ixgbe_mac_X550:\n \t\tcase ixgbe_mac_X550EM_x:\n \t\tcase ixgbe_mac_X550EM_a:\n+\t\tcase ixgbe_mac_E610:\n \t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, 0xFFFFFFFF);\n \t\t\tbreak;\n \t\tdefault:\n@@ -1827,6 +1829,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \t\tcase ixgbe_mac_X550:\n \t\tcase ixgbe_mac_X550EM_x:\n \t\tcase ixgbe_mac_X550EM_a:\n+\t\tcase ixgbe_mac_E610:\n \t\t\tIXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);\n \t\t\tbreak;\n \t\tdefault:\ndiff --git a/drivers/net/ixgbe/base/ixgbe_api.c b/drivers/net/ixgbe/base/ixgbe_api.c\nindex d2b74cdffc..d348a81a88 100644\n--- a/drivers/net/ixgbe/base/ixgbe_api.c\n+++ b/drivers/net/ixgbe/base/ixgbe_api.c\n@@ -89,6 +89,9 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n \tcase ixgbe_mac_X550EM_a_vf:\n \t\tstatus = ixgbe_init_ops_vf(hw);\n \t\tbreak;\n+\tcase ixgbe_mac_E610:\n+\t\tstatus = ixgbe_init_ops_E610(hw);\n+\t\tbreak;\n \tdefault:\n \t\tstatus = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n \t\tbreak;\n@@ -208,6 +211,14 @@ s32 ixgbe_set_mac_type(struct ixgbe_hw *hw)\n \t\thw->mac.type = ixgbe_mac_X550EM_a_vf;\n \t\thw->mvals = ixgbe_mvals_X550EM_a;\n \t\tbreak;\n+\tcase IXGBE_DEV_ID_E610_BACKPLANE:\n+\tcase IXGBE_DEV_ID_E610_SFP:\n+\tcase IXGBE_DEV_ID_E610_10G_T:\n+\tcase IXGBE_DEV_ID_E610_2_5G_T:\n+\tcase IXGBE_DEV_ID_E610_SGMII:\n+\t\thw->mac.type = ixgbe_mac_E610;\n+\t\thw->mvals = ixgbe_mvals_X550EM_a;\n+\t\tbreak;\n \tdefault:\n \t\tret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED;\n \t\tERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,\n@@ -445,7 +456,8 @@ s32 ixgbe_stop_adapter(struct ixgbe_hw *hw)\n  **/\n s32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size)\n {\n-\treturn ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size);\n+\treturn ixgbe_call_func(hw, hw->eeprom.ops.read_pba_string, (hw, pba_num,\n+\t\t\t       pba_num_size), IXGBE_NOT_IMPLEMENTED);\n }\n \n /**\n@@ -1141,6 +1153,19 @@ s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n \t\t\t       IXGBE_NOT_IMPLEMENTED);\n }\n \n+/**\n+ * ixgbe_get_fw_tsam_mode - Returns information whether TSAM is enabled\n+ * @hw: pointer to hardware structure\n+ *\n+ * Checks Thermal Sensor Autonomous Mode by reading the value of the\n+ * dedicated register.\n+ * Returns True if TSAM is enabled, False if TSAM is disabled.\n+ */\n+bool ixgbe_get_fw_tsam_mode(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.get_fw_tsam_mode, (hw),\n+\t\t\t       IXGBE_NOT_IMPLEMENTED);\n+}\n \n /**\n  * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data\n@@ -1684,3 +1709,34 @@ void ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed)\n \tif (hw->mac.ops.set_rate_select_speed)\n \t\thw->mac.ops.set_rate_select_speed(hw, speed);\n }\n+\n+/**\n+ * ixgbe_get_fw_version - get FW version\n+ * @hw: pointer to hardware structure\n+ *\n+ * Get the current FW version.\n+ *\n+ * Return: the exit code of the operation or IXGBE_NOT_IMPLEMENTED\n+ * if the function is not implemented.\n+ */\n+s32 ixgbe_get_fw_version(struct ixgbe_hw *hw)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.get_fw_version,\n+\t\t\t       (hw), IXGBE_NOT_IMPLEMENTED);\n+}\n+\n+/**\n+ * ixgbe_get_nvm_ver - get NVM version\n+ * @hw: pointer to hardware structure\n+ * @nvm: pointer to NVM info structure\n+ *\n+ * Get the current NVM version.\n+ *\n+ * Return: the exit code of the operation or IXGBE_NOT_IMPLEMENTED\n+ * if the function is not implemented.\n+ */\n+s32 ixgbe_get_nvm_ver(struct ixgbe_hw* hw, struct ixgbe_nvm_info *nvm)\n+{\n+\treturn ixgbe_call_func(hw, hw->mac.ops.get_nvm_version,\n+\t\t\t       (hw, nvm), IXGBE_NOT_IMPLEMENTED);\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_api.h b/drivers/net/ixgbe/base/ixgbe_api.h\nindex 51decc5fae..cb572a337d 100644\n--- a/drivers/net/ixgbe/base/ixgbe_api.h\n+++ b/drivers/net/ixgbe/base/ixgbe_api.h\n@@ -18,6 +18,7 @@ extern s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_X550EM_x(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_X550EM_a(struct ixgbe_hw *hw);\n+extern s32 ixgbe_init_ops_E610(struct ixgbe_hw *hw);\n extern s32 ixgbe_init_ops_vf(struct ixgbe_hw *hw);\n \n s32 ixgbe_set_mac_type(struct ixgbe_hw *hw);\n@@ -105,6 +106,7 @@ s32 ixgbe_fc_enable(struct ixgbe_hw *hw);\n s32 ixgbe_setup_fc(struct ixgbe_hw *hw);\n s32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n \t\t\t u8 ver, u16 len, char *driver_ver);\n+bool ixgbe_get_fw_tsam_mode(struct ixgbe_hw *hw);\n s32 ixgbe_get_thermal_sensor_data(struct ixgbe_hw *hw);\n s32 ixgbe_init_thermal_sensor_thresh(struct ixgbe_hw *hw);\n void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr);\n@@ -192,5 +194,6 @@ void ixgbe_disable_rx(struct ixgbe_hw *hw);\n void ixgbe_enable_rx(struct ixgbe_hw *hw);\n s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,\n \t\t\tu32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm);\n-\n+s32 ixgbe_get_fw_version(struct ixgbe_hw *hw);\n+s32 ixgbe_get_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n #endif /* _IXGBE_API_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c\nindex 73b5935d88..51fb4050c6 100644\n--- a/drivers/net/ixgbe/base/ixgbe_common.c\n+++ b/drivers/net/ixgbe/base/ixgbe_common.c\n@@ -61,6 +61,7 @@ s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)\n \t\t\t\t      ixgbe_validate_eeprom_checksum_generic;\n \teeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;\n \teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;\n+\teeprom->ops.read_pba_string = ixgbe_read_pba_string_generic;\n \n \t/* MAC */\n \tmac->ops.init_hw = ixgbe_init_hw_generic;\n@@ -146,6 +147,7 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n \t\tcase IXGBE_DEV_ID_X550EM_A_SFP_N:\n \t\tcase IXGBE_DEV_ID_X550EM_A_QSFP:\n \t\tcase IXGBE_DEV_ID_X550EM_A_QSFP_N:\n+\t\tcase IXGBE_DEV_ID_E610_SFP:\n \t\t\tsupported = false;\n \t\t\tbreak;\n \t\tdefault:\n@@ -177,6 +179,8 @@ bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)\n \t\tcase IXGBE_DEV_ID_X550EM_A_10G_T:\n \t\tcase IXGBE_DEV_ID_X550EM_A_1G_T:\n \t\tcase IXGBE_DEV_ID_X550EM_A_1G_T_L:\n+\t\tcase IXGBE_DEV_ID_E610_10G_T:\n+\t\tcase IXGBE_DEV_ID_E610_2_5G_T:\n \t\t\tsupported = true;\n \t\t\tbreak;\n \t\tdefault:\n@@ -577,17 +581,11 @@ s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)\n \t\t}\n \t}\n \n-\tif (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {\n+\tif (hw->mac.type == ixgbe_mac_X540 ||\n+\t    hw->mac.type == ixgbe_mac_X550 ||\n+\t    hw->mac.type == ixgbe_mac_E610) {\n \t\tif (hw->phy.id == 0)\n \t\t\tixgbe_identify_phy(hw);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,\n-\t\t\t\t     IXGBE_MDIO_PCS_DEV_TYPE, &i);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,\n-\t\t\t\t     IXGBE_MDIO_PCS_DEV_TYPE, &i);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECL,\n-\t\t\t\t     IXGBE_MDIO_PCS_DEV_TYPE, &i);\n-\t\thw->phy.ops.read_reg(hw, IXGBE_LDPCECH,\n-\t\t\t\t     IXGBE_MDIO_PCS_DEV_TYPE, &i);\n \t}\n \n \treturn IXGBE_SUCCESS;\n@@ -998,6 +996,9 @@ void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)\n \tcase IXGBE_PCI_LINK_SPEED_8000:\n \t\thw->bus.speed = ixgbe_bus_speed_8000;\n \t\tbreak;\n+\tcase IXGBE_PCI_LINK_SPEED_16000:\n+\t\thw->bus.speed = ixgbe_bus_speed_16000;\n+\t\tbreak;\n \tdefault:\n \t\thw->bus.speed = ixgbe_bus_speed_unknown;\n \t\tbreak;\n@@ -1020,7 +1021,9 @@ s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)\n \tDEBUGFUNC(\"ixgbe_get_bus_info_generic\");\n \n \t/* Get the negotiated link width and speed from PCI config space */\n-\tlink_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);\n+\tlink_status = IXGBE_READ_PCIE_WORD(hw, hw->mac.type == ixgbe_mac_E610 ?\n+\t\t\t\t\t   IXGBE_PCI_LINK_STATUS_E610 :\n+\t\t\t\t\t   IXGBE_PCI_LINK_STATUS);\n \n \tixgbe_set_pci_config_data_generic(hw, link_status);\n \n@@ -3653,6 +3656,10 @@ u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)\n \t\tpcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;\n \t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;\n \t\tbreak;\n+\tcase ixgbe_mac_E610:\n+\t\tpcie_offset = IXGBE_PCIE_MSIX_LKV_CAPS;\n+\t\tmax_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;\n+\t\tbreak;\n \tdefault:\n \t\treturn msix_count;\n \t}\n@@ -4228,7 +4235,7 @@ s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n \t\tbreak;\n \tcase IXGBE_LINKS_SPEED_100_82599:\n \t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n-\t\tif (hw->mac.type == ixgbe_mac_X550) {\n+\t\tif (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_E610) {\n \t\t\tif (links_reg & IXGBE_LINKS_SPEED_NON_STD)\n \t\t\t\t*speed = IXGBE_LINK_SPEED_5GB_FULL;\n \t\t}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.c b/drivers/net/ixgbe/base/ixgbe_e610.c\nnew file mode 100644\nindex 0000000000..37e0acf81c\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.c\n@@ -0,0 +1,4982 @@\n+#include \"ixgbe_type.h\"\n+#include \"ixgbe_e610.h\"\n+#include \"ixgbe_x550.h\"\n+#include \"ixgbe_common.h\"\n+#include \"ixgbe_phy.h\"\n+#include \"ixgbe_api.h\"\n+\n+/**\n+ * ixgbe_init_aci - initialization routine for Admin Command Interface\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Initialize the ACI lock.\n+ */\n+void ixgbe_init_aci(struct ixgbe_hw *hw)\n+{\n+\tixgbe_init_lock(&hw->aci.lock);\n+}\n+\n+/**\n+ * ixgbe_shutdown_aci - shutdown routine for Admin Command Interface\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Destroy the ACI lock.\n+ */\n+void ixgbe_shutdown_aci(struct ixgbe_hw *hw)\n+{\n+\tixgbe_destroy_lock(&hw->aci.lock);\n+}\n+\n+/**\n+ * ixgbe_should_retry_aci_send_cmd_execute - decide if ACI command should\n+ * be resent\n+ * @opcode: ACI opcode\n+ *\n+ * Check if ACI command should be sent again depending on the provided opcode.\n+ *\n+ * Return: true if the sending command routine should be repeated,\n+ * otherwise false.\n+ */\n+STATIC bool ixgbe_should_retry_aci_send_cmd_execute(u16 opcode)\n+{\n+\n+\tswitch (opcode) {\n+\tcase ixgbe_aci_opc_disable_rxen:\n+\tcase ixgbe_aci_opc_get_phy_caps:\n+\tcase ixgbe_aci_opc_get_link_status:\n+\tcase ixgbe_aci_opc_get_link_topo:\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+/**\n+ * ixgbe_aci_send_cmd_execute - execute sending FW Admin Command to FW Admin\n+ * Command Interface\n+ * @hw: pointer to the HW struct\n+ * @desc: descriptor describing the command\n+ * @buf: buffer to use for indirect commands (NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (0 for direct commands)\n+ *\n+ * Admin Command is sent using CSR by setting descriptor and buffer in specific\n+ * registers.\n+ *\n+ * Return: the exit code of the operation.\n+ * * - IXGBE_SUCCESS - success.\n+ * * - IXGBE_ERR_ACI_DISABLED - CSR mechanism is not enabled.\n+ * * - IXGBE_ERR_ACI_BUSY - CSR mechanism is busy.\n+ * * - IXGBE_ERR_PARAM - buf_size is too big or\n+ * invalid argument buf or buf_size.\n+ * * - IXGBE_ERR_ACI_TIMEOUT - Admin Command X command timeout.\n+ * * - IXGBE_ERR_ACI_ERROR - Admin Command X invalid state of HICR register or\n+ * Admin Command failed because of bad opcode was returned or\n+ * Admin Command failed with error Y.\n+ */\n+STATIC s32\n+ixgbe_aci_send_cmd_execute(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,\n+\t\t\t   void *buf, u16 buf_size)\n+{\n+\tu32 hicr = 0, tmp_buf_size = 0, i = 0;\n+\tu32 *raw_desc = (u32 *)desc;\n+\ts32 status = IXGBE_SUCCESS;\n+\tbool valid_buf = false;\n+\tu32 *tmp_buf = NULL;\n+\tu16 opcode = 0;\n+\n+\tdo {\n+\t\thw->aci.last_status = IXGBE_ACI_RC_OK;\n+\n+\t\t/* It's necessary to check if mechanism is enabled */\n+\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\tif (!(hicr & PF_HICR_EN)) {\n+\t\t\tstatus = IXGBE_ERR_ACI_DISABLED;\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (hicr & PF_HICR_C) {\n+\t\t\thw->aci.last_status = IXGBE_ACI_RC_EBUSY;\n+\t\t\tstatus = IXGBE_ERR_ACI_BUSY;\n+\t\t\tbreak;\n+\t\t}\n+\t\topcode = desc->opcode;\n+\n+\t\tif (buf_size > IXGBE_ACI_MAX_BUFFER_SIZE) {\n+\t\t\tstatus = IXGBE_ERR_PARAM;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (buf)\n+\t\t\tdesc->flags |= IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_BUF);\n+\n+\t\t/* Check if buf and buf_size are proper params */\n+\t\tif (desc->flags & IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_BUF)) {\n+\t\t\tif ((buf && buf_size == 0) ||\n+\t\t\t    (buf == NULL && buf_size)) {\n+\t\t\t\tstatus = IXGBE_ERR_PARAM;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tif (buf && buf_size)\n+\t\t\t\tvalid_buf = true;\n+\t\t}\n+\n+\t\tif (valid_buf == true) {\n+\t\t\tif (buf_size % 4 == 0)\n+\t\t\t\ttmp_buf_size = buf_size;\n+\t\t\telse\n+\t\t\t\ttmp_buf_size = (buf_size & (u16)(~0x03)) + 4;\n+\n+\t\t\ttmp_buf = (u32*)ixgbe_malloc(hw, tmp_buf_size);\n+\t\t\tif (!tmp_buf)\n+\t\t\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\n+\t\t\t/* tmp_buf will be firstly filled with 0xFF and after\n+\t\t\t * that the content of buf will be written into it.\n+\t\t\t * This approach lets us use valid buf_size and\n+\t\t\t * prevents us from reading past buf area\n+\t\t\t * when buf_size mod 4 not equal to 0.\n+\t\t\t */\n+\t\t\tmemset(tmp_buf, 0xFF, tmp_buf_size);\n+\t\t\tmemcpy(tmp_buf, buf, buf_size);\n+\n+\t\t\tif (tmp_buf_size > IXGBE_ACI_LG_BUF)\n+\t\t\t\tdesc->flags |=\n+\t\t\t\tIXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_LB);\n+\n+\t\t\tdesc->datalen = IXGBE_CPU_TO_LE16(buf_size);\n+\n+\t\t\tif (desc->flags & IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_RD)) {\n+\t\t\t\tfor (i = 0; i < tmp_buf_size / 4; i++) {\n+\t\t\t\t\tIXGBE_WRITE_REG(hw, PF_HIBA(i),\n+\t\t\t\t\t\tIXGBE_LE32_TO_CPU(tmp_buf[i]));\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Descriptor is written to specific registers */\n+\t\tfor (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++)\n+\t\t\tIXGBE_WRITE_REG(hw, PF_HIDA(i),\n+\t\t\t\t\tIXGBE_LE32_TO_CPU(raw_desc[i]));\n+\n+\t\t/* SW has to set PF_HICR.C bit and clear PF_HICR.SV and\n+\t\t * PF_HICR_EV\n+\t\t */\n+\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\thicr = (hicr | PF_HICR_C) & ~(PF_HICR_SV | PF_HICR_EV);\n+\t\tIXGBE_WRITE_REG(hw, PF_HICR, hicr);\n+\n+\t\t/* Wait for sync Admin Command response */\n+\t\tfor (i = 0; i < IXGBE_ACI_SYNC_RESPONSE_TIMEOUT; i += 1) {\n+\t\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\t\tif ((hicr & PF_HICR_SV) || !(hicr & PF_HICR_C))\n+\t\t\t\tbreak;\n+\n+\t\t\tmsec_delay(1);\n+\t\t}\n+\n+\t\t/* Wait for async Admin Command response */\n+\t\tif ((hicr & PF_HICR_SV) && (hicr & PF_HICR_C)) {\n+\t\t\tfor (i = 0; i < IXGBE_ACI_ASYNC_RESPONSE_TIMEOUT;\n+\t\t\t     i += 1) {\n+\t\t\t\thicr = IXGBE_READ_REG(hw, PF_HICR);\n+\t\t\t\tif ((hicr & PF_HICR_EV) || !(hicr & PF_HICR_C))\n+\t\t\t\t\tbreak;\n+\n+\t\t\t\tmsec_delay(1);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Read sync Admin Command response */\n+\t\tif ((hicr & PF_HICR_SV)) {\n+\t\t\tfor (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) {\n+\t\t\t\traw_desc[i] = IXGBE_READ_REG(hw, PF_HIDA(i));\n+\t\t\t\traw_desc[i] = IXGBE_CPU_TO_LE32(raw_desc[i]);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Read async Admin Command response */\n+\t\tif ((hicr & PF_HICR_EV) && !(hicr & PF_HICR_C)) {\n+\t\t\tfor (i = 0; i < IXGBE_ACI_DESC_SIZE_IN_DWORDS; i++) {\n+\t\t\t\traw_desc[i] = IXGBE_READ_REG(hw, PF_HIDA_2(i));\n+\t\t\t\traw_desc[i] = IXGBE_CPU_TO_LE32(raw_desc[i]);\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Handle timeout and invalid state of HICR register */\n+\t\tif (hicr & PF_HICR_C) {\n+\t\t\tstatus = IXGBE_ERR_ACI_TIMEOUT;\n+\t\t\tbreak;\n+\t\t} else if (!(hicr & PF_HICR_SV) && !(hicr & PF_HICR_EV)) {\n+\t\t\tstatus = IXGBE_ERR_ACI_ERROR;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* For every command other than 0x0014 treat opcode mismatch\n+\t\t * as an error. Response to 0x0014 command read from HIDA_2\n+\t\t * is a descriptor of an event which is expected to contain\n+\t\t * different opcode than the command.\n+\t\t */\n+\t\tif (desc->opcode != opcode &&\n+\t\t    opcode != IXGBE_CPU_TO_LE16(ixgbe_aci_opc_get_fw_event)) {\n+\t\t\tstatus = IXGBE_ERR_ACI_ERROR;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tif (desc->retval != IXGBE_ACI_RC_OK) {\n+\t\t\thw->aci.last_status = (enum ixgbe_aci_err)desc->retval;\n+\t\t\tstatus = IXGBE_ERR_ACI_ERROR;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* Write a response values to a buf */\n+\t\tif (valid_buf && (desc->flags &\n+\t\t\t\t  IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_BUF))) {\n+\t\t\tfor (i = 0; i < tmp_buf_size / 4; i++) {\n+\t\t\t\ttmp_buf[i] = IXGBE_READ_REG(hw, PF_HIBA(i));\n+\t\t\t\ttmp_buf[i] = IXGBE_CPU_TO_LE32(tmp_buf[i]);\n+\t\t\t}\n+\t\t\tmemcpy(buf, tmp_buf, buf_size);\n+\t\t}\n+\t} while (0);\n+\n+\tif (tmp_buf)\n+\t\tixgbe_free(hw, tmp_buf);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_send_cmd - send FW Admin Command to FW Admin Command Interface\n+ * @hw: pointer to the HW struct\n+ * @desc: descriptor describing the command\n+ * @buf: buffer to use for indirect commands (NULL for direct commands)\n+ * @buf_size: size of buffer for indirect commands (0 for direct commands)\n+ *\n+ * Helper function to send FW Admin Commands to the FW Admin Command Interface.\n+ *\n+ * Retry sending the FW Admin Command multiple times to the FW ACI\n+ * if the EBUSY Admin Command error is returned.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,\n+\t\t       void *buf, u16 buf_size)\n+{\n+\tstruct ixgbe_aci_desc desc_cpy;\n+\tenum ixgbe_aci_err last_status;\n+\tbool is_cmd_for_retry;\n+\tu8 *buf_cpy = NULL;\n+\ts32 status;\n+\tu16 opcode;\n+\tu8 idx = 0;\n+\n+\topcode = IXGBE_LE16_TO_CPU(desc->opcode);\n+\tis_cmd_for_retry = ixgbe_should_retry_aci_send_cmd_execute(opcode);\n+\tmemset(&desc_cpy, 0, sizeof(desc_cpy));\n+\n+\tif (is_cmd_for_retry) {\n+\t\tif (buf) {\n+\t\t\tbuf_cpy = (u8 *)ixgbe_malloc(hw, buf_size);\n+\t\t\tif (!buf_cpy)\n+\t\t\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\t\t}\n+\t\tmemcpy(&desc_cpy, desc, sizeof(desc_cpy));\n+\t}\n+\n+\tdo {\n+\t\tixgbe_acquire_lock(&hw->aci.lock);\n+\t\tstatus = ixgbe_aci_send_cmd_execute(hw, desc, buf, buf_size);\n+\t\tlast_status = hw->aci.last_status;\n+\t\tixgbe_release_lock(&hw->aci.lock);\n+\n+\t\tif (!is_cmd_for_retry || status == IXGBE_SUCCESS ||\n+\t\t    last_status != IXGBE_ACI_RC_EBUSY)\n+\t\t\tbreak;\n+\n+\t\tif (buf)\n+\t\t\tmemcpy(buf, buf_cpy, buf_size);\n+\t\tmemcpy(desc, &desc_cpy, sizeof(desc_cpy));\n+\n+\t\tmsec_delay(IXGBE_ACI_SEND_DELAY_TIME_MS);\n+\t} while (++idx < IXGBE_ACI_SEND_MAX_EXECUTE);\n+\n+\tif (buf_cpy)\n+\t\tixgbe_free(hw, buf_cpy);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_check_event_pending - check if there are any pending events\n+ * @hw: pointer to the HW struct\n+ *\n+ * Determine if there are any pending events.\n+ *\n+ * Return: true if there are any currently pending events\n+ * otherwise false.\n+ */\n+bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw)\n+{\n+\tu32 ep_bit_mask;\n+\tu32 fwsts;\n+\n+\tep_bit_mask = hw->bus.func ? GL_FWSTS_EP_PF1 : GL_FWSTS_EP_PF0;\n+\n+\t/* Check state of Event Pending (EP) bit */\n+\tfwsts = IXGBE_READ_REG(hw, GL_FWSTS);\n+\treturn (fwsts & ep_bit_mask) ? true : false;\n+}\n+\n+/**\n+ * ixgbe_aci_get_event - get an event from ACI\n+ * @hw: pointer to the HW struct\n+ * @e: event information structure\n+ * @pending: optional flag signaling that there are more pending events\n+ *\n+ * Obtain an event from ACI and return its content\n+ * through 'e' using ACI command (0x0014).\n+ * Provide information if there are more events\n+ * to retrieve through 'pending'.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,\n+\t\t\tbool *pending)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tif (!e || (!e->msg_buf && e->buf_len) || (e->msg_buf && !e->buf_len))\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_acquire_lock(&hw->aci.lock);\n+\n+\t/* Check if there are any events pending */\n+\tif (!ixgbe_aci_check_event_pending(hw)) {\n+\t\tstatus = IXGBE_ERR_ACI_NO_EVENTS;\n+\t\tgoto aci_get_event_exit;\n+\t}\n+\n+\t/* Obtain pending event */\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_fw_event);\n+\tstatus = ixgbe_aci_send_cmd_execute(hw, &desc, e->msg_buf, e->buf_len);\n+\tif (status)\n+\t\tgoto aci_get_event_exit;\n+\n+\t/* Returned 0x0014 opcode indicates that no event was obtained */\n+\tif (desc.opcode == IXGBE_CPU_TO_LE16(ixgbe_aci_opc_get_fw_event)) {\n+\t\tstatus = IXGBE_ERR_ACI_NO_EVENTS;\n+\t\tgoto aci_get_event_exit;\n+\t}\n+\n+\t/* Determine size of event data */\n+\te->msg_len = MIN_T(u16, IXGBE_LE16_TO_CPU(desc.datalen), e->buf_len);\n+\t/* Write event descriptor to event info structure */\n+\tmemcpy(&e->desc, &desc, sizeof(e->desc));\n+\n+\t/* Check if there are any further events pending */\n+\tif (pending) {\n+\t\t*pending = ixgbe_aci_check_event_pending(hw);\n+\t}\n+\n+aci_get_event_exit:\n+\tixgbe_release_lock(&hw->aci.lock);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_fill_dflt_direct_cmd_desc - fill ACI descriptor with default values.\n+ * @desc: pointer to the temp descriptor (non DMA mem)\n+ * @opcode: the opcode can be used to decide which flags to turn off or on\n+ *\n+ * Helper function to fill the descriptor desc with default values\n+ * and the provided opcode.\n+ */\n+void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode)\n+{\n+\t/* zero out the desc */\n+\tmemset(desc, 0, sizeof(*desc));\n+\tdesc->opcode = IXGBE_CPU_TO_LE16(opcode);\n+\tdesc->flags = IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_SI);\n+}\n+\n+/**\n+ * ixgbe_aci_get_fw_ver - get the firmware version\n+ * @hw: pointer to the HW struct\n+ *\n+ * Get the firmware version using ACI command (0x0001).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_ver *resp;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tresp = &desc.params.get_ver;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_ver);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tif (!status) {\n+\t\thw->fw_branch = resp->fw_branch;\n+\t\thw->fw_maj_ver = resp->fw_major;\n+\t\thw->fw_min_ver = resp->fw_minor;\n+\t\thw->fw_patch = resp->fw_patch;\n+\t\thw->fw_build = IXGBE_LE32_TO_CPU(resp->fw_build);\n+\t\thw->api_branch = resp->api_branch;\n+\t\thw->api_maj_ver = resp->api_major;\n+\t\thw->api_min_ver = resp->api_minor;\n+\t\thw->api_patch = resp->api_patch;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_send_driver_ver - send the driver version to firmware\n+ * @hw: pointer to the HW struct\n+ * @dv: driver's major, minor version\n+ *\n+ * Send the driver version to the firmware\n+ * using the ACI command (0x0002).\n+ *\n+ * Return: the exit code of the operation.\n+ * Returns IXGBE_ERR_PARAM, if dv is NULL.\n+ */\n+s32 ixgbe_aci_send_driver_ver(struct ixgbe_hw *hw, struct ixgbe_driver_ver *dv)\n+{\n+\tstruct ixgbe_aci_cmd_driver_ver *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\tu16 len;\n+\n+\tcmd = &desc.params.driver_ver;\n+\n+\tif (!dv)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_driver_ver);\n+\n+\tdesc.flags |= IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_RD);\n+\tcmd->major_ver = dv->major_ver;\n+\tcmd->minor_ver = dv->minor_ver;\n+\tcmd->build_ver = dv->build_ver;\n+\tcmd->subbuild_ver = dv->subbuild_ver;\n+\n+\tlen = 0;\n+\twhile (len < sizeof(dv->driver_string) &&\n+\t       IS_ASCII(dv->driver_string[len]) && dv->driver_string[len])\n+\t\tlen++;\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, dv->driver_string, len);\n+}\n+\n+/**\n+ * ixgbe_aci_req_res - request a common resource\n+ * @hw: pointer to the HW struct\n+ * @res: resource ID\n+ * @access: access type\n+ * @sdp_number: resource number\n+ * @timeout: the maximum time in ms that the driver may hold the resource\n+ *\n+ * Requests a common resource using the ACI command (0x0008).\n+ * Specifies the maximum time the driver may hold the resource.\n+ * If the requested resource is currently occupied by some other driver,\n+ * a busy return value is returned and the timeout field value indicates the\n+ * maximum time the current owner has to free it.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32\n+ixgbe_aci_req_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t  enum ixgbe_aci_res_access_type access, u8 sdp_number,\n+\t\t  u32 *timeout)\n+{\n+\tstruct ixgbe_aci_cmd_req_res *cmd_resp;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd_resp = &desc.params.res_owner;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_req_res);\n+\n+\tcmd_resp->res_id = IXGBE_CPU_TO_LE16(res);\n+\tcmd_resp->access_type = IXGBE_CPU_TO_LE16(access);\n+\tcmd_resp->res_number = IXGBE_CPU_TO_LE32(sdp_number);\n+\tcmd_resp->timeout = IXGBE_CPU_TO_LE32(*timeout);\n+\t*timeout = 0;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\t/* The completion specifies the maximum time in ms that the driver\n+\t * may hold the resource in the Timeout field.\n+\t */\n+\n+\t/* If the resource is held by some other driver, the command completes\n+\t * with a busy return value and the timeout field indicates the maximum\n+\t * time the current owner of the resource has to free it.\n+\t */\n+\tif (!status || hw->aci.last_status == IXGBE_ACI_RC_EBUSY)\n+\t\t*timeout = IXGBE_LE32_TO_CPU(cmd_resp->timeout);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_release_res - release a common resource using ACI\n+ * @hw: pointer to the HW struct\n+ * @res: resource ID\n+ * @sdp_number: resource number\n+ *\n+ * Release a common resource using ACI command (0x0009).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32\n+ixgbe_aci_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t      u8 sdp_number)\n+{\n+\tstruct ixgbe_aci_cmd_req_res *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tcmd = &desc.params.res_owner;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_release_res);\n+\n+\tcmd->res_id = IXGBE_CPU_TO_LE16(res);\n+\tcmd->res_number = IXGBE_CPU_TO_LE32(sdp_number);\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_acquire_res - acquire the ownership of a resource\n+ * @hw: pointer to the HW structure\n+ * @res: resource ID\n+ * @access: access type (read or write)\n+ * @timeout: timeout in milliseconds\n+ *\n+ * Make an attempt to acquire the ownership of a resource using\n+ * the ixgbe_aci_req_res to utilize ACI.\n+ * In case if some other driver has previously acquired the resource and\n+ * performed any necessary updates, the IXGBE_ERR_ACI_NO_WORK is returned,\n+ * and the caller does not obtain the resource and has no further work to do.\n+ * If needed, the function will poll until the current lock owner timeouts.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t      enum ixgbe_aci_res_access_type access, u32 timeout)\n+{\n+#define IXGBE_RES_POLLING_DELAY_MS\t10\n+\tu32 delay = IXGBE_RES_POLLING_DELAY_MS;\n+\tu32 res_timeout = timeout;\n+\tu32 retry_timeout = 0;\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout);\n+\n+\t/* A return code of IXGBE_ERR_ACI_NO_WORK means that another driver has\n+\t * previously acquired the resource and performed any necessary updates;\n+\t * in this case the caller does not obtain the resource and has no\n+\t * further work to do.\n+\t */\n+\tif (status == IXGBE_ERR_ACI_NO_WORK)\n+\t\tgoto ixgbe_acquire_res_exit;\n+\n+\t/* If necessary, poll until the current lock owner timeouts.\n+\t * Set retry_timeout to the timeout value reported by the FW in the\n+\t * response to the \"Request Resource Ownership\" (0x0008) Admin Command\n+\t * as it indicates the maximum time the current owner of the resource\n+\t * is allowed to hold it.\n+\t */\n+\tretry_timeout = res_timeout;\n+\twhile (status && retry_timeout && res_timeout) {\n+\t\tmsec_delay(delay);\n+\t\tretry_timeout = (retry_timeout > delay) ?\n+\t\t\tretry_timeout - delay : 0;\n+\t\tstatus = ixgbe_aci_req_res(hw, res, access, 0, &res_timeout);\n+\n+\t\tif (status == IXGBE_ERR_ACI_NO_WORK)\n+\t\t\t/* lock free, but no work to do */\n+\t\t\tbreak;\n+\n+\t\tif (!status)\n+\t\t\t/* lock acquired */\n+\t\t\tbreak;\n+\t}\n+\n+ixgbe_acquire_res_exit:\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_release_res - release a common resource\n+ * @hw: pointer to the HW structure\n+ * @res: resource ID\n+ *\n+ * Release a common resource using ixgbe_aci_release_res.\n+ */\n+void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res)\n+{\n+\tu32 total_delay = 0;\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_release_res(hw, res, 0);\n+\n+\t/* There are some rare cases when trying to release the resource\n+\t * results in an admin command timeout, so handle them correctly.\n+\t */\n+\twhile ((status == IXGBE_ERR_ACI_TIMEOUT) &&\n+\t       (total_delay < IXGBE_ACI_RELEASE_RES_TIMEOUT)) {\n+\t\tmsec_delay(1);\n+\t\tstatus = ixgbe_aci_release_res(hw, res, 0);\n+\t\ttotal_delay++;\n+\t}\n+}\n+\n+/**\n+ * ixgbe_parse_common_caps - Parse common device/function capabilities\n+ * @hw: pointer to the HW struct\n+ * @caps: pointer to common capabilities structure\n+ * @elem: the capability element to parse\n+ * @prefix: message prefix for tracing capabilities\n+ *\n+ * Given a capability element, extract relevant details into the common\n+ * capability structure.\n+ *\n+ * Return: true if the capability matches one of the common capability ids,\n+ * false otherwise.\n+ */\n+static bool\n+ixgbe_parse_common_caps(struct ixgbe_hw *hw, struct ixgbe_hw_common_caps *caps,\n+\t\t\tstruct ixgbe_aci_cmd_list_caps_elem *elem,\n+\t\t\tconst char *prefix)\n+{\n+\tu32 logical_id = IXGBE_LE32_TO_CPU(elem->logical_id);\n+\tu32 phys_id = IXGBE_LE32_TO_CPU(elem->phys_id);\n+\tu32 number = IXGBE_LE32_TO_CPU(elem->number);\n+\tu16 cap = IXGBE_LE16_TO_CPU(elem->cap);\n+\tbool found = true;\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tswitch (cap) {\n+\tcase IXGBE_ACI_CAPS_VALID_FUNCTIONS:\n+\t\tcaps->valid_functions = number;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_VMDQ:\n+\t\tcaps->vmdq = (number == 1);\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_DCB:\n+\t\tcaps->dcb = (number == 1);\n+\t\tcaps->active_tc_bitmap = logical_id;\n+\t\tcaps->maxtc = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_RSS:\n+\t\tcaps->rss_table_size = number;\n+\t\tcaps->rss_table_entry_width = logical_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_RXQS:\n+\t\tcaps->num_rxq = number;\n+\t\tcaps->rxq_first_id = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_TXQS:\n+\t\tcaps->num_txq = number;\n+\t\tcaps->txq_first_id = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_MSIX:\n+\t\tcaps->num_msix_vectors = number;\n+\t\tcaps->msix_vector_first_id = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_NVM_VER:\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_NVM_MGMT:\n+\t\tcaps->sec_rev_disabled =\n+\t\t\t(number & IXGBE_NVM_MGMT_SEC_REV_DISABLED) ?\n+\t\t\ttrue : false;\n+\t\tcaps->update_disabled =\n+\t\t\t(number & IXGBE_NVM_MGMT_UPDATE_DISABLED) ?\n+\t\t\ttrue : false;\n+\t\tcaps->nvm_unified_update =\n+\t\t\t(number & IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?\n+\t\t\ttrue : false;\n+\t\tcaps->netlist_auth =\n+\t\t\t(number & IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT) ?\n+\t\t\ttrue : false;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_MAX_MTU:\n+\t\tcaps->max_mtu = number;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE:\n+\t\tcaps->pcie_reset_avoidance = (number > 0);\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT:\n+\t\tcaps->reset_restrict_support = (number == 1);\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0:\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1:\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2:\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3:\n+\t{\n+\t\tu8 index = cap - IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0;\n+\n+\t\tcaps->ext_topo_dev_img_ver_high[index] = number;\n+\t\tcaps->ext_topo_dev_img_ver_low[index] = logical_id;\n+\t\tcaps->ext_topo_dev_img_part_num[index] =\n+\t\t\t(phys_id & IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M) >>\n+\t\t\tIXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S;\n+\t\tcaps->ext_topo_dev_img_load_en[index] =\n+\t\t\t(phys_id & IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0;\n+\t\tcaps->ext_topo_dev_img_prog_en[index] =\n+\t\t\t(phys_id & IXGBE_EXT_TOPO_DEV_IMG_PROG_EN) != 0;\n+\t\tbreak;\n+\t}\n+\n+\tcase IXGBE_ACI_CAPS_NEXT_CLUSTER_ID:\n+\t\tcaps->next_cluster_id_support = (number == 1);\n+\t\tDEBUGOUT2(\"%s: next_cluster_id_support = %d\\n\",\n+\t\t\t  prefix, caps->next_cluster_id_support);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Not one of the recognized common capabilities */\n+\t\tfound = false;\n+\t}\n+\n+\treturn found;\n+}\n+\n+/**\n+ * ixgbe_hweight8 - count set bits among the 8 lowest bits\n+ * @w: variable storing set bits to count\n+ *\n+ * Return: the number of set bits among the 8 lowest bits in the provided value.\n+ */\n+static u8 ixgbe_hweight8(u32 w)\n+{\n+\tu8 hweight = 0, i;\n+\n+\tfor (i = 0; i < 8; i++)\n+\t\tif (w & (1 << i))\n+\t\t\thweight++;\n+\n+\treturn hweight;\n+}\n+\n+/**\n+ * ixgbe_hweight32 - count set bits among the 32 lowest bits\n+ * @w: variable storing set bits to count\n+ *\n+ * Return: the number of set bits among the 32 lowest bits in the\n+ * provided value.\n+ */\n+static u8 ixgbe_hweight32(u32 w)\n+{\n+\tu32 bitMask = 0x1, i;\n+\tu8  bitCnt = 0;\n+\n+\tfor (i = 0; i < 32; i++)\n+\t{\n+\t\tif (w & bitMask)\n+\t\t\tbitCnt++;\n+\n+\t\tbitMask = bitMask << 0x1;\n+\t}\n+\n+\treturn bitCnt;\n+}\n+\n+/**\n+ * ixgbe_func_id_to_logical_id - map from function id to logical pf id\n+ * @active_function_bitmap: active function bitmap\n+ * @pf_id: function number of device\n+ *\n+ * Return: the logical id of a function mapped by the provided pf_id.\n+ */\n+static int ixgbe_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)\n+{\n+\tu8 logical_id = 0;\n+\tu8 i;\n+\n+\tfor (i = 0; i < pf_id; i++)\n+\t\tif (active_function_bitmap & BIT(i))\n+\t\t\tlogical_id++;\n+\n+\treturn logical_id;\n+}\n+\n+/**\n+ * ixgbe_parse_valid_functions_cap - Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS for device capabilities.\n+ */\n+static void\n+ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw,\n+\t\t\t\tstruct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\tstruct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tdev_p->num_funcs = ixgbe_hweight32(number);\n+\n+\thw->logical_pf_id = ixgbe_func_id_to_logical_id(number, hw->pf_id);\n+}\n+\n+/**\n+ * ixgbe_parse_vsi_dev_caps - Parse IXGBE_ACI_CAPS_VSI device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_VSI for device capabilities.\n+ */\n+static void ixgbe_parse_vsi_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t     struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t     struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tdev_p->num_vsi_allocd_to_host = number;\n+}\n+\n+/**\n+ * ixgbe_parse_1588_dev_caps - Parse IXGBE_ACI_CAPS_1588 device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_1588 for device capabilities.\n+ */\n+static void ixgbe_parse_1588_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t      struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t      struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tstruct ixgbe_ts_dev_info *info = &dev_p->ts_dev_info;\n+\tu32 logical_id = IXGBE_LE32_TO_CPU(cap->logical_id);\n+\tu32 phys_id = IXGBE_LE32_TO_CPU(cap->phys_id);\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tinfo->ena = ((number & IXGBE_TS_DEV_ENA_M) != 0);\n+\tdev_p->common_cap.ieee_1588 = info->ena;\n+\n+\tinfo->tmr0_owner = number & IXGBE_TS_TMR0_OWNR_M;\n+\tinfo->tmr0_owned = ((number & IXGBE_TS_TMR0_OWND_M) != 0);\n+\tinfo->tmr0_ena = ((number & IXGBE_TS_TMR0_ENA_M) != 0);\n+\n+\tinfo->tmr1_owner = (number & IXGBE_TS_TMR1_OWNR_M) >>\n+\t\t\t   IXGBE_TS_TMR1_OWNR_S;\n+\tinfo->tmr1_owned = ((number & IXGBE_TS_TMR1_OWND_M) != 0);\n+\tinfo->tmr1_ena = ((number & IXGBE_TS_TMR1_ENA_M) != 0);\n+\n+\tinfo->ena_ports = logical_id;\n+\tinfo->tmr_own_map = phys_id;\n+\n+}\n+\n+/**\n+ * ixgbe_parse_fdir_dev_caps - Parse IXGBE_ACI_CAPS_FD device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_FD for device capabilities.\n+ */\n+static void ixgbe_parse_fdir_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t      struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t      struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tdev_p->num_flow_director_fltr = number;\n+}\n+\n+/**\n+ * ixgbe_parse_dev_caps - Parse device capabilities\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @buf: buffer containing the device capability records\n+ * @cap_count: the number of capabilities\n+ *\n+ * Helper device to parse device (0x000B) capabilities list. For\n+ * capabilities shared between device and function, this relies on\n+ * ixgbe_parse_common_caps.\n+ *\n+ * Loop through the list of provided capabilities and extract the relevant\n+ * data into the device capabilities structured.\n+ */\n+static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t void *buf, u32 cap_count)\n+{\n+\tstruct ixgbe_aci_cmd_list_caps_elem *cap_resp;\n+\tu32 i;\n+\n+\tcap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf;\n+\n+\tmemset(dev_p, 0, sizeof(*dev_p));\n+\n+\tfor (i = 0; i < cap_count; i++) {\n+\t\tu16 cap = IXGBE_LE16_TO_CPU(cap_resp[i].cap);\n+\t\tbool found;\n+\n+\t\tfound = ixgbe_parse_common_caps(hw, &dev_p->common_cap,\n+\t\t\t\t\t      &cap_resp[i], \"dev caps\");\n+\n+\t\tswitch (cap) {\n+\t\tcase IXGBE_ACI_CAPS_VALID_FUNCTIONS:\n+\t\t\tixgbe_parse_valid_functions_cap(hw, dev_p,\n+\t\t\t\t\t\t\t&cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_CAPS_VSI:\n+\t\t\tixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_CAPS_1588:\n+\t\t\tixgbe_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase  IXGBE_ACI_CAPS_FD:\n+\t\t\tixgbe_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Don't list common capabilities as unknown */\n+\t\t\tif (!found)\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+}\n+\n+/**\n+ * ixgbe_get_num_per_func - determine number of resources per PF\n+ * @hw: pointer to the HW structure\n+ * @max: value to be evenly split between each PF\n+ *\n+ * Determine the number of valid functions by going through the bitmap returned\n+ * from parsing capabilities and use this to calculate the number of resources\n+ * per PF based on the max value passed in.\n+ *\n+ * Return: the number of resources per PF or 0, if no PH are available.\n+ */\n+static u32 ixgbe_get_num_per_func(struct ixgbe_hw *hw, u32 max)\n+{\n+\tu8 funcs;\n+\n+#define IXGBE_CAPS_VALID_FUNCS_M\t0xFF\n+\tfuncs = ixgbe_hweight8(hw->dev_caps.common_cap.valid_functions &\n+\t\t\t     IXGBE_CAPS_VALID_FUNCS_M);\n+\n+\tif (!funcs)\n+\t\treturn 0;\n+\n+\treturn max / funcs;\n+}\n+\n+/**\n+ * ixgbe_parse_vsi_func_caps - Parse IXGBE_ACI_CAPS_VSI function caps\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @cap: pointer to the capability element to parse\n+ *\n+ * Extract function capabilities for IXGBE_ACI_CAPS_VSI.\n+ */\n+static void ixgbe_parse_vsi_func_caps(struct ixgbe_hw *hw,\n+\t\t\t\t      struct ixgbe_hw_func_caps *func_p,\n+\t\t\t\t      struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tfunc_p->guar_num_vsi = ixgbe_get_num_per_func(hw, IXGBE_MAX_VSI);\n+}\n+\n+/**\n+ * ixgbe_parse_1588_func_caps - Parse IXGBE_ACI_CAPS_1588 function caps\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @cap: pointer to the capability element to parse\n+ *\n+ * Extract function capabilities for IXGBE_ACI_CAPS_1588.\n+ */\n+static void ixgbe_parse_1588_func_caps(struct ixgbe_hw *hw,\n+\t\t\t\t       struct ixgbe_hw_func_caps *func_p,\n+\t\t\t\t       struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tstruct ixgbe_ts_func_info *info = &func_p->ts_func_info;\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tinfo->ena = ((number & IXGBE_TS_FUNC_ENA_M) != 0);\n+\tfunc_p->common_cap.ieee_1588 = info->ena;\n+\n+\tinfo->src_tmr_owned = ((number & IXGBE_TS_SRC_TMR_OWND_M) != 0);\n+\tinfo->tmr_ena = ((number & IXGBE_TS_TMR_ENA_M) != 0);\n+\tinfo->tmr_index_owned = ((number & IXGBE_TS_TMR_IDX_OWND_M) != 0);\n+\tinfo->tmr_index_assoc = ((number & IXGBE_TS_TMR_IDX_ASSOC_M) != 0);\n+\n+\tinfo->clk_freq = (number & IXGBE_TS_CLK_FREQ_M) >> IXGBE_TS_CLK_FREQ_S;\n+\tinfo->clk_src = ((number & IXGBE_TS_CLK_SRC_M) != 0);\n+\n+\tif (info->clk_freq < NUM_IXGBE_TIME_REF_FREQ) {\n+\t\tinfo->time_ref = (enum ixgbe_time_ref_freq)info->clk_freq;\n+\t} else {\n+\t\t/* Unknown clock frequency, so assume a (probably incorrect)\n+\t\t * default to avoid out-of-bounds look ups of frequency\n+\t\t * related information.\n+\t\t */\n+\t\tinfo->time_ref = IXGBE_TIME_REF_FREQ_25_000;\n+\t}\n+\n+}\n+/**\n+ * ixgbe_parse_func_caps - Parse function capabilities\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @buf: buffer containing the function capability records\n+ * @cap_count: the number of capabilities\n+ *\n+ * Helper function to parse function (0x000A) capabilities list. For\n+ * capabilities shared between device and function, this relies on\n+ * ixgbe_parse_common_caps.\n+ *\n+ * Loop through the list of provided capabilities and extract the relevant\n+ * data into the function capabilities structured.\n+ */\n+static void ixgbe_parse_func_caps(struct ixgbe_hw *hw,\n+\t\t\t\t  struct ixgbe_hw_func_caps *func_p,\n+\t\t\t\t  void *buf, u32 cap_count)\n+{\n+\tstruct ixgbe_aci_cmd_list_caps_elem *cap_resp;\n+\tu32 i;\n+\n+\tcap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf;\n+\n+\tmemset(func_p, 0, sizeof(*func_p));\n+\n+\tfor (i = 0; i < cap_count; i++) {\n+\t\tu16 cap = IXGBE_LE16_TO_CPU(cap_resp[i].cap);\n+\n+\t\tixgbe_parse_common_caps(hw, &func_p->common_cap,\n+\t\t\t\t\t&cap_resp[i], \"func caps\");\n+\n+\t\tswitch (cap) {\n+\t\tcase IXGBE_ACI_CAPS_VSI:\n+\t\t\tixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_CAPS_1588:\n+\t\t\tixgbe_parse_1588_func_caps(hw, func_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Don't list common capabilities as unknown */\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+}\n+\n+/**\n+ * ixgbe_aci_list_caps - query function/device capabilities\n+ * @hw: pointer to the HW struct\n+ * @buf: a buffer to hold the capabilities\n+ * @buf_size: size of the buffer\n+ * @cap_count: if not NULL, set to the number of capabilities reported\n+ * @opc: capabilities type to discover, device or function\n+ *\n+ * Get the function (0x000A) or device (0x000B) capabilities description from\n+ * firmware and store it in the buffer.\n+ *\n+ * If the cap_count pointer is not NULL, then it is set to the number of\n+ * capabilities firmware will report. Note that if the buffer size is too\n+ * small, it is possible the command will return IXGBE_ERR_OUT_OF_MEM. The\n+ * cap_count will still be updated in this case. It is recommended that the\n+ * buffer size be set to IXGBE_ACI_MAX_BUFFER_SIZE (the largest possible\n+ * buffer that firmware could return) to avoid this.\n+ *\n+ * Return: the exit code of the operation.\n+ * Exit code of IXGBE_ERR_OUT_OF_MEM means the buffer size is too small.\n+ */\n+s32 ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size,\n+\t\t\tu32 *cap_count, enum ixgbe_aci_opc opc)\n+{\n+\tstruct ixgbe_aci_cmd_list_caps *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.get_cap;\n+\n+\tif (opc != ixgbe_aci_opc_list_func_caps &&\n+\t    opc != ixgbe_aci_opc_list_dev_caps)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, opc);\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, buf, buf_size);\n+\n+\tif (cap_count)\n+\t\t*cap_count = IXGBE_LE32_TO_CPU(cmd->count);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_discover_dev_caps - Read and extract device capabilities\n+ * @hw: pointer to the hardware structure\n+ * @dev_caps: pointer to device capabilities structure\n+ *\n+ * Read the device capabilities and extract them into the dev_caps structure\n+ * for later use.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_discover_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t    struct ixgbe_hw_dev_caps *dev_caps)\n+{\n+\tu32 status, cap_count = 0;\n+\tu8 *cbuf = NULL;\n+\n+\tcbuf = (u8*)ixgbe_malloc(hw, IXGBE_ACI_MAX_BUFFER_SIZE);\n+\tif (!cbuf)\n+\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\t/* Although the driver doesn't know the number of capabilities the\n+\t * device will return, we can simply send a 4KB buffer, the maximum\n+\t * possible size that firmware can return.\n+\t */\n+\tcap_count = IXGBE_ACI_MAX_BUFFER_SIZE /\n+\t\t    sizeof(struct ixgbe_aci_cmd_list_caps_elem);\n+\n+\tstatus = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE,\n+\t\t\t\t     &cap_count,\n+\t\t\t\t     ixgbe_aci_opc_list_dev_caps);\n+\tif (!status)\n+\t\tixgbe_parse_dev_caps(hw, dev_caps, cbuf, cap_count);\n+\n+\tif (cbuf)\n+\t\tixgbe_free(hw, cbuf);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_discover_func_caps - Read and extract function capabilities\n+ * @hw: pointer to the hardware structure\n+ * @func_caps: pointer to function capabilities structure\n+ *\n+ * Read the function capabilities and extract them into the func_caps structure\n+ * for later use.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_discover_func_caps(struct ixgbe_hw *hw,\n+\t\t\t     struct ixgbe_hw_func_caps *func_caps)\n+{\n+\tu32 cap_count = 0;\n+\tu8 *cbuf = NULL;\n+\ts32 status;\n+\n+\tcbuf = (u8*)ixgbe_malloc(hw, IXGBE_ACI_MAX_BUFFER_SIZE);\n+\tif(!cbuf)\n+\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\t/* Although the driver doesn't know the number of capabilities the\n+\t * device will return, we can simply send a 4KB buffer, the maximum\n+\t * possible size that firmware can return.\n+\t */\n+\tcap_count = IXGBE_ACI_MAX_BUFFER_SIZE /\n+\t\t    sizeof(struct ixgbe_aci_cmd_list_caps_elem);\n+\n+\tstatus = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE,\n+\t\t\t\t     &cap_count,\n+\t\t\t\t     ixgbe_aci_opc_list_func_caps);\n+\tif (!status)\n+\t\tixgbe_parse_func_caps(hw, func_caps, cbuf, cap_count);\n+\n+\tif (cbuf)\n+\t\tixgbe_free(hw, cbuf);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_get_caps - get info about the HW\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Retrieve both device and function capabilities.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_caps(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\n+\tstatus = ixgbe_discover_dev_caps(hw, &hw->dev_caps);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ixgbe_discover_func_caps(hw, &hw->func_caps);\n+}\n+\n+/**\n+ * ixgbe_aci_disable_rxen - disable RX\n+ * @hw: pointer to the HW struct\n+ *\n+ * Request a safe disable of Receive Enable using ACI command (0x000C).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_disable_rxen(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_disable_rxen *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tcmd = &desc.params.disable_rxen;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_disable_rxen);\n+\n+\tcmd->lport_num = (u8)hw->bus.func;\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_get_phy_caps - returns PHY capabilities\n+ * @hw: pointer to the HW struct\n+ * @qual_mods: report qualified modules\n+ * @report_mode: report mode capabilities\n+ * @pcaps: structure for PHY capabilities to be filled\n+ *\n+ * Returns the various PHY capabilities supported on the Port\n+ * using ACI command (0x0600).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,\n+\t\t\t   struct ixgbe_aci_cmd_get_phy_caps_data *pcaps)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps *cmd;\n+\tu16 pcaps_size = sizeof(*pcaps);\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.get_phy;\n+\n+\tif (!pcaps || (report_mode & ~IXGBE_ACI_REPORT_MODE_M))\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_phy_caps);\n+\n+\tif (qual_mods)\n+\t\tcmd->param0 |= IXGBE_CPU_TO_LE16(IXGBE_ACI_GET_PHY_RQM);\n+\n+\tcmd->param0 |= IXGBE_CPU_TO_LE16(report_mode);\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, pcaps, pcaps_size);\n+\n+\tif (status == IXGBE_SUCCESS &&\n+\t    report_mode == IXGBE_ACI_REPORT_TOPO_CAP_MEDIA) {\n+\t\thw->phy.phy_type_low = IXGBE_LE64_TO_CPU(pcaps->phy_type_low);\n+\t\thw->phy.phy_type_high = IXGBE_LE64_TO_CPU(pcaps->phy_type_high);\n+\t\tmemcpy(hw->link.link_info.module_type, &pcaps->module_type,\n+\t\t\t   sizeof(hw->link.link_info.module_type));\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_phy_caps_equals_cfg - check if capabilities match the PHY config\n+ * @phy_caps: PHY capabilities\n+ * @phy_cfg: PHY configuration\n+ *\n+ * Helper function to determine if PHY capabilities match PHY\n+ * configuration\n+ *\n+ * Return: true if PHY capabilities match PHY configuration.\n+ */\n+bool\n+ixgbe_phy_caps_equals_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *phy_caps,\n+\t\t\t  struct ixgbe_aci_cmd_set_phy_cfg_data *phy_cfg)\n+{\n+\tu8 caps_mask, cfg_mask;\n+\n+\tif (!phy_caps || !phy_cfg)\n+\t\treturn false;\n+\n+\t/* These bits are not common between capabilities and configuration.\n+\t * Do not use them to determine equality.\n+\t */\n+\tcaps_mask = IXGBE_ACI_PHY_CAPS_MASK & ~(IXGBE_ACI_PHY_AN_MODE |\n+\t\t\t\t\t      IXGBE_ACI_PHY_EN_MOD_QUAL);\n+\tcfg_mask = IXGBE_ACI_PHY_ENA_VALID_MASK &\n+\t\t   ~IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\tif (phy_caps->phy_type_low != phy_cfg->phy_type_low ||\n+\t    phy_caps->phy_type_high != phy_cfg->phy_type_high ||\n+\t    ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||\n+\t    phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||\n+\t    phy_caps->eee_cap != phy_cfg->eee_cap ||\n+\t    phy_caps->eeer_value != phy_cfg->eeer_value ||\n+\t    phy_caps->link_fec_options != phy_cfg->link_fec_opt)\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+/**\n+ * ixgbe_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data\n+ * @caps: PHY ability structure to copy data from\n+ * @cfg: PHY configuration structure to copy data to\n+ *\n+ * Helper function to copy data from PHY capabilities data structure\n+ * to PHY configuration data structure\n+ */\n+void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,\n+\t\t\t\tstruct ixgbe_aci_cmd_set_phy_cfg_data *cfg)\n+{\n+\tif (!caps || !cfg)\n+\t\treturn;\n+\n+\tmemset(cfg, 0, sizeof(*cfg));\n+\tcfg->phy_type_low = caps->phy_type_low;\n+\tcfg->phy_type_high = caps->phy_type_high;\n+\tcfg->caps = caps->caps;\n+\tcfg->low_power_ctrl_an = caps->low_power_ctrl_an;\n+\tcfg->eee_cap = caps->eee_cap;\n+\tcfg->eeer_value = caps->eeer_value;\n+\tcfg->link_fec_opt = caps->link_fec_options;\n+\tcfg->module_compliance_enforcement =\n+\t\tcaps->module_compliance_enforcement;\n+}\n+\n+/**\n+ * ixgbe_aci_set_phy_cfg - set PHY configuration\n+ * @hw: pointer to the HW struct\n+ * @cfg: structure with PHY configuration data to be set\n+ *\n+ * Set the various PHY configuration parameters supported on the Port\n+ * using ACI command (0x0601).\n+ * One or more of the Set PHY config parameters may be ignored in an MFP\n+ * mode as the PF may not have the privilege to set some of the PHY Config\n+ * parameters.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw,\n+\t\t\t  struct ixgbe_aci_cmd_set_phy_cfg_data *cfg)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tif (!cfg)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\t/* Ensure that only valid bits of cfg->caps can be turned on. */\n+\tif (cfg->caps & ~IXGBE_ACI_PHY_ENA_VALID_MASK) {\n+\t\tcfg->caps &= IXGBE_ACI_PHY_ENA_VALID_MASK;\n+\t}\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_phy_cfg);\n+\tdesc.flags |= IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_RD);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, cfg, sizeof(*cfg));\n+\n+\tif (!status)\n+\t\thw->phy.curr_user_phy_cfg = *cfg;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_set_link_restart_an - set up link and restart AN\n+ * @hw: pointer to the HW struct\n+ * @ena_link: if true: enable link, if false: disable link\n+ *\n+ * Function sets up the link and restarts the Auto-Negotiation over the link.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link)\n+{\n+\tstruct ixgbe_aci_cmd_restart_an *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tcmd = &desc.params.restart_an;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_restart_an);\n+\n+\tcmd->cmd_flags = IXGBE_ACI_RESTART_AN_LINK_RESTART;\n+\tif (ena_link)\n+\t\tcmd->cmd_flags |= IXGBE_ACI_RESTART_AN_LINK_ENABLE;\n+\telse\n+\t\tcmd->cmd_flags &= ~IXGBE_ACI_RESTART_AN_LINK_ENABLE;\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_is_media_cage_present - check if media cage is present\n+ * @hw: pointer to the HW struct\n+ *\n+ * Identify presence of media cage using the ACI command (0x06E0).\n+ *\n+ * Return: true if media cage is present, else false. If no cage, then\n+ * media type is backplane or BASE-T.\n+ */\n+static bool ixgbe_is_media_cage_present(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_link_topo *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tcmd = &desc.params.get_link_topo;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo);\n+\n+\tcmd->addr.topo_params.node_type_ctx =\n+\t\t(IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT <<\n+\t\t IXGBE_ACI_LINK_TOPO_NODE_CTX_S);\n+\n+\t/* set node type */\n+\tcmd->addr.topo_params.node_type_ctx |=\n+\t\t(IXGBE_ACI_LINK_TOPO_NODE_TYPE_M &\n+\t\t IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE);\n+\n+\t/* Node type cage can be used to determine if cage is present. If AQC\n+\t * returns error (ENOENT), then no cage present. If no cage present then\n+\t * connection type is backplane or BASE-T.\n+\t */\n+\treturn ixgbe_aci_get_netlist_node(hw, cmd, NULL, NULL);\n+}\n+\n+/**\n+ * ixgbe_get_media_type_from_phy_type - Gets media type based on phy type\n+ * @hw: pointer to the HW struct\n+ *\n+ * Try to identify the media type based on the phy type.\n+ * If more than one media type, the ixgbe_media_type_unknown is returned.\n+ * First, phy_type_low is checked, then phy_type_high.\n+ * If none are identified, the ixgbe_media_type_unknown is returned\n+ *\n+ * Return: type of a media based on phy type in form of enum.\n+ */\n+static enum ixgbe_media_type\n+ixgbe_get_media_type_from_phy_type(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_link_status *hw_link_info;\n+\n+\tif (!hw)\n+\t\treturn ixgbe_media_type_unknown;\n+\n+\thw_link_info = &hw->link.link_info;\n+\tif (hw_link_info->phy_type_low && hw_link_info->phy_type_high)\n+\t\t/* If more than one media type is selected, report unknown */\n+\t\treturn ixgbe_media_type_unknown;\n+\n+\tif (hw_link_info->phy_type_low) {\n+\t\t/* 1G SGMII is a special case where some DA cable PHYs\n+\t\t * may show this as an option when it really shouldn't\n+\t\t * be since SGMII is meant to be between a MAC and a PHY\n+\t\t * in a backplane. Try to detect this case and handle it\n+\t\t */\n+\t\tif (hw_link_info->phy_type_low == IXGBE_PHY_TYPE_LOW_1G_SGMII &&\n+\t\t    (hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] ==\n+\t\t    IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE ||\n+\t\t    hw_link_info->module_type[IXGBE_ACI_MOD_TYPE_IDENT] ==\n+\t\t    IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE))\n+\t\t\treturn ixgbe_media_type_da;\n+\n+\t\tswitch (hw_link_info->phy_type_low) {\n+\t\tcase IXGBE_PHY_TYPE_LOW_1000BASE_SX:\n+\t\tcase IXGBE_PHY_TYPE_LOW_1000BASE_LX:\n+\t\tcase IXGBE_PHY_TYPE_LOW_10GBASE_SR:\n+\t\tcase IXGBE_PHY_TYPE_LOW_10GBASE_LR:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_SR:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_LR:\n+\t\t\treturn ixgbe_media_type_fiber;\n+\t\tcase IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC:\n+\t\t\treturn ixgbe_media_type_fiber;\n+\t\tcase IXGBE_PHY_TYPE_LOW_100BASE_TX:\n+\t\tcase IXGBE_PHY_TYPE_LOW_1000BASE_T:\n+\t\tcase IXGBE_PHY_TYPE_LOW_2500BASE_T:\n+\t\tcase IXGBE_PHY_TYPE_LOW_5GBASE_T:\n+\t\tcase IXGBE_PHY_TYPE_LOW_10GBASE_T:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_T:\n+\t\t\treturn ixgbe_media_type_copper;\n+\t\tcase IXGBE_PHY_TYPE_LOW_10G_SFI_DA:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_CR:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_CR_S:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_CR1:\n+\t\t\treturn ixgbe_media_type_da;\n+\t\tcase IXGBE_PHY_TYPE_LOW_25G_AUI_C2C:\n+\t\t\tif (ixgbe_is_media_cage_present(hw))\n+\t\t\t\treturn ixgbe_media_type_aui;\n+\t\t\treturn ixgbe_media_type_backplane;\n+\t\tcase IXGBE_PHY_TYPE_LOW_1000BASE_KX:\n+\t\tcase IXGBE_PHY_TYPE_LOW_2500BASE_KX:\n+\t\tcase IXGBE_PHY_TYPE_LOW_2500BASE_X:\n+\t\tcase IXGBE_PHY_TYPE_LOW_5GBASE_KR:\n+\t\tcase IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1:\n+\t\tcase IXGBE_PHY_TYPE_LOW_10G_SFI_C2C:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_KR:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_KR1:\n+\t\tcase IXGBE_PHY_TYPE_LOW_25GBASE_KR_S:\n+\t\t\treturn ixgbe_media_type_backplane;\n+\t\t}\n+\t} else {\n+\t\tswitch (hw_link_info->phy_type_high) {\n+\t\tcase IXGBE_PHY_TYPE_HIGH_10BASE_T:\n+\t\t\treturn ixgbe_media_type_copper;\n+\t\t}\n+\t}\n+\treturn ixgbe_media_type_unknown;\n+}\n+\n+/**\n+ * ixgbe_update_link_info - update status of the HW network link\n+ * @hw: pointer to the HW struct\n+ *\n+ * Update the status of the HW network link.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_update_link_info(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data *pcaps;\n+\tstruct ixgbe_link_status *li;\n+\ts32 status;\n+\n+\tif (!hw)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tli = &hw->link.link_info;\n+\n+\tstatus = ixgbe_aci_get_link_info(hw, true, NULL);\n+\tif (status)\n+\t\treturn status;\n+\n+\tif (li->link_info & IXGBE_ACI_MEDIA_AVAILABLE) {\n+\t\tpcaps = (struct ixgbe_aci_cmd_get_phy_caps_data *)\n+\t\t\tixgbe_malloc(hw, sizeof(*pcaps));\n+\t\tif (!pcaps)\n+\t\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\n+\t\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\t\t\t\t\tIXGBE_ACI_REPORT_TOPO_CAP_MEDIA,\n+\t\t\t\t\t\tpcaps);\n+\n+\t\tif (status == IXGBE_SUCCESS)\n+\t\t\tmemcpy(li->module_type, &pcaps->module_type,\n+\t\t\t       sizeof(li->module_type));\n+\n+\t\tixgbe_free(hw, pcaps);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_get_link_status - get status of the HW network link\n+ * @hw: pointer to the HW struct\n+ * @link_up: pointer to bool (true/false = linkup/linkdown)\n+ *\n+ * Variable link_up is true if link is up, false if link is down.\n+ * The variable link_up is invalid if status is non zero. As a\n+ * result of this call, link status reporting becomes enabled\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_link_status(struct ixgbe_hw *hw, bool *link_up)\n+{\n+\ts32 status = IXGBE_SUCCESS;\n+\n+\tif (!hw || !link_up)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tif (hw->link.get_link_info) {\n+\t\tstatus = ixgbe_update_link_info(hw);\n+\t\tif (status) {\n+\t\t\treturn status;\n+\t\t}\n+\t}\n+\n+\t*link_up = hw->link.link_info.link_info & IXGBE_ACI_LINK_UP;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_get_link_info - get the link status\n+ * @hw: pointer to the HW struct\n+ * @ena_lse: enable/disable LinkStatusEvent reporting\n+ * @link: pointer to link status structure - optional\n+ *\n+ * Get the current Link Status using ACI command (0x607).\n+ * The current link can be optionally provided to update\n+ * the status.\n+ *\n+ * Return: the link status of the adapter.\n+ */\n+s32 ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,\n+\t\t\t    struct ixgbe_link_status *link)\n+{\n+\tstruct ixgbe_aci_cmd_get_link_status_data link_data = { 0 };\n+\tstruct ixgbe_aci_cmd_get_link_status *resp;\n+\tstruct ixgbe_link_status *li_old, *li;\n+\tstruct ixgbe_fc_info *hw_fc_info;\n+\tenum ixgbe_media_type *hw_media_type;\n+\tstruct ixgbe_aci_desc desc;\n+\tbool tx_pause, rx_pause;\n+\tu8 cmd_flags;\n+\ts32 status;\n+\n+\tif (!hw)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tli_old = &hw->link.link_info_old;\n+\thw_media_type = &hw->phy.media_type;\n+\tli = &hw->link.link_info;\n+\thw_fc_info = &hw->fc;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_status);\n+\tcmd_flags = (ena_lse) ? IXGBE_ACI_LSE_ENA : IXGBE_ACI_LSE_DIS;\n+\tresp = &desc.params.get_link_status;\n+\tresp->cmd_flags = cmd_flags;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, &link_data, sizeof(link_data));\n+\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\t/* save off old link status information */\n+\t*li_old = *li;\n+\n+\t/* update current link status information */\n+\tli->link_speed = IXGBE_LE16_TO_CPU(link_data.link_speed);\n+\tli->phy_type_low = IXGBE_LE64_TO_CPU(link_data.phy_type_low);\n+\tli->phy_type_high = IXGBE_LE64_TO_CPU(link_data.phy_type_high);\n+\t*hw_media_type = ixgbe_get_media_type_from_phy_type(hw);\n+\tli->link_info = link_data.link_info;\n+\tli->link_cfg_err = link_data.link_cfg_err;\n+\tli->an_info = link_data.an_info;\n+\tli->ext_info = link_data.ext_info;\n+\tli->max_frame_size = IXGBE_LE16_TO_CPU(link_data.max_frame_size);\n+\tli->fec_info = link_data.cfg & IXGBE_ACI_FEC_MASK;\n+\tli->topo_media_conflict = link_data.topo_media_conflict;\n+\tli->pacing = link_data.cfg & (IXGBE_ACI_CFG_PACING_M |\n+\t\t\t\t      IXGBE_ACI_CFG_PACING_TYPE_M);\n+\n+\t/* update fc info */\n+\ttx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_TX);\n+\trx_pause = !!(link_data.an_info & IXGBE_ACI_LINK_PAUSE_RX);\n+\tif (tx_pause && rx_pause)\n+\t\thw_fc_info->current_mode = ixgbe_fc_full;\n+\telse if (tx_pause)\n+\t\thw_fc_info->current_mode = ixgbe_fc_tx_pause;\n+\telse if (rx_pause)\n+\t\thw_fc_info->current_mode = ixgbe_fc_rx_pause;\n+\telse\n+\t\thw_fc_info->current_mode = ixgbe_fc_none;\n+\n+\tli->lse_ena = !!(resp->cmd_flags & IXGBE_ACI_LSE_IS_ENABLED);\n+\n+\t/* save link status information */\n+\tif (link)\n+\t\t*link = *li;\n+\n+\t/* flag cleared so calling functions don't call AQ again */\n+\thw->link.get_link_info = false;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_aci_set_event_mask - set event mask\n+ * @hw: pointer to the HW struct\n+ * @port_num: port number of the physical function\n+ * @mask: event mask to be set\n+ *\n+ * Set the event mask using ACI command (0x0613).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask)\n+{\n+\tstruct ixgbe_aci_cmd_set_event_mask *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tcmd = &desc.params.set_event_mask;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_event_mask);\n+\n+\tcmd->event_mask = IXGBE_CPU_TO_LE16(mask);\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_configure_lse - enable/disable link status events\n+ * @hw: pointer to the HW struct\n+ * @activate: bool value deciding if lse should be enabled nor disabled\n+ * @mask: event mask to be set; a set bit means deactivation of the\n+ * corresponding event\n+ *\n+ * Set the event mask and then enable or disable link status events\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask)\n+{\n+\ts32 rc;\n+\n+\trc = ixgbe_aci_set_event_mask(hw, (u8)hw->bus.func, mask);\n+\tif (rc) {\n+\t\treturn rc;\n+\t}\n+\n+\t/* Enabling link status events generation by fw */\n+\trc = ixgbe_aci_get_link_info(hw, activate, NULL);\n+\tif (rc) {\n+\t\treturn rc;\n+\t}\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_aci_get_netlist_node - get a node handle\n+ * @hw: pointer to the hw struct\n+ * @cmd: get_link_topo AQ structure\n+ * @node_part_number: output node part number if node found\n+ * @node_handle: output node handle parameter if node found\n+ *\n+ * Get the netlist node and assigns it to\n+ * the provided handle using ACI command (0x06E0).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,\n+\t\t\t       struct ixgbe_aci_cmd_get_link_topo *cmd,\n+\t\t\t       u8 *node_part_number, u16 *node_handle)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo);\n+\tdesc.params.get_link_topo = *cmd;\n+\n+\tif (ixgbe_aci_send_cmd(hw, &desc, NULL, 0))\n+\t\treturn IXGBE_ERR_NOT_SUPPORTED;\n+\n+\tif (node_handle)\n+\t\t*node_handle =\n+\t\t\tIXGBE_LE16_TO_CPU(desc.params.get_link_topo.addr.handle);\n+\tif (node_part_number)\n+\t\t*node_part_number = desc.params.get_link_topo.node_part_num;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_aci_get_netlist_node_pin - get a node pin handle\n+ * @hw: pointer to the hw struct\n+ * @cmd: get_link_topo_pin AQ structure\n+ * @node_handle: output node handle parameter if node found\n+ *\n+ * Get the netlist node pin and assign it to\n+ * the provided handle using ACI command (0x06E1).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_netlist_node_pin(struct ixgbe_hw *hw,\n+\t\t\t\t   struct ixgbe_aci_cmd_get_link_topo_pin *cmd,\n+\t\t\t\t   u16 *node_handle)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo_pin);\n+\tdesc.params.get_link_topo_pin = *cmd;\n+\n+\tif (ixgbe_aci_send_cmd(hw, &desc, NULL, 0))\n+\t\treturn IXGBE_ERR_NOT_SUPPORTED;\n+\n+\tif (node_handle)\n+\t\t*node_handle =\n+\t\t\tIXGBE_LE16_TO_CPU(desc.params.get_link_topo_pin.addr.handle);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_find_netlist_node - find a node handle\n+ * @hw: pointer to the hw struct\n+ * @node_type_ctx: type of netlist node to look for\n+ * @node_part_number: node part number to look for\n+ * @node_handle: output parameter if node found - optional\n+ *\n+ * Find and return the node handle for a given node type and part number in the\n+ * netlist. When found IXGBE_SUCCESS is returned, IXGBE_ERR_NOT_SUPPORTED\n+ * otherwise. If @node_handle provided, it would be set to found node handle.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_find_netlist_node(struct ixgbe_hw *hw, u8 node_type_ctx,\n+\t\t\t    u8 node_part_number, u16 *node_handle)\n+{\n+\tstruct ixgbe_aci_cmd_get_link_topo cmd;\n+\tu8 rec_node_part_number;\n+\tu16 rec_node_handle;\n+\ts32 status;\n+\tu8 idx;\n+\n+\tfor (idx = 0; idx < IXGBE_MAX_NETLIST_SIZE; idx++) {\n+\t\tmemset(&cmd, 0, sizeof(cmd));\n+\n+\t\tcmd.addr.topo_params.node_type_ctx =\n+\t\t\t(node_type_ctx << IXGBE_ACI_LINK_TOPO_NODE_TYPE_S);\n+\t\tcmd.addr.topo_params.index = idx;\n+\n+\t\tstatus = ixgbe_aci_get_netlist_node(hw, &cmd,\n+\t\t\t\t\t\t    &rec_node_part_number,\n+\t\t\t\t\t\t    &rec_node_handle);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tif (rec_node_part_number == node_part_number) {\n+\t\t\tif (node_handle)\n+\t\t\t\t*node_handle = rec_node_handle;\n+\t\t\treturn IXGBE_SUCCESS;\n+\t\t}\n+\t}\n+\n+\treturn IXGBE_ERR_NOT_SUPPORTED;\n+}\n+\n+/**\n+ * ixgbe_aci_read_i2c - read I2C register value\n+ * @hw: pointer to the hw struct\n+ * @topo_addr: topology address for a device to communicate with\n+ * @bus_addr: 7-bit I2C bus address\n+ * @addr: I2C memory address (I2C offset) with up to 16 bits\n+ * @params: I2C parameters: bit [7] - Repeated start,\n+ *\t\t\t\t      bits [6:5] data offset size,\n+ *\t\t\t    bit [4] - I2C address type, bits [3:0] - data size\n+ *\t\t\t\t      to read (0-16 bytes)\n+ * @data: pointer to data (0 to 16 bytes) to be read from the I2C device\n+ *\n+ * Read the value of the I2C pin register using ACI command (0x06E2).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_read_i2c(struct ixgbe_hw *hw,\n+\t\t       struct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t       u16 bus_addr, __le16 addr, u8 params, u8 *data)\n+{\n+\tstruct ixgbe_aci_desc desc = { 0 };\n+\tstruct ixgbe_aci_cmd_i2c *cmd;\n+\tu8 data_size;\n+\ts32 status;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_read_i2c);\n+\tcmd = &desc.params.read_write_i2c;\n+\n+\tif (!data)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tdata_size = (params & IXGBE_ACI_I2C_DATA_SIZE_M) >>\n+\t\t    IXGBE_ACI_I2C_DATA_SIZE_S;\n+\n+\tcmd->i2c_bus_addr = IXGBE_CPU_TO_LE16(bus_addr);\n+\tcmd->topo_addr = topo_addr;\n+\tcmd->i2c_params = params;\n+\tcmd->i2c_addr = addr;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (!status) {\n+\t\tstruct ixgbe_aci_cmd_read_i2c_resp *resp;\n+\t\tu8 i;\n+\n+\t\tresp = &desc.params.read_i2c_resp;\n+\t\tfor (i = 0; i < data_size; i++) {\n+\t\t\t*data = resp->i2c_data[i];\n+\t\t\tdata++;\n+\t\t}\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_write_i2c - write a value to I2C register\n+ * @hw: pointer to the hw struct\n+ * @topo_addr: topology address for a device to communicate with\n+ * @bus_addr: 7-bit I2C bus address\n+ * @addr: I2C memory address (I2C offset) with up to 16 bits\n+ * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size\n+ *\t\t\t\t      to write (0-7 bytes)\n+ * @data: pointer to data (0 to 4 bytes) to be written to the I2C device\n+ *\n+ * Write a value to the I2C pin register using ACI command (0x06E3).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_write_i2c(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t\tu16 bus_addr, __le16 addr, u8 params, u8 *data)\n+{\n+\tstruct ixgbe_aci_desc desc = { 0 };\n+\tstruct ixgbe_aci_cmd_i2c *cmd;\n+\tu8 i, data_size;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_write_i2c);\n+\tcmd = &desc.params.read_write_i2c;\n+\n+\tdata_size = (params & IXGBE_ACI_I2C_DATA_SIZE_M) >>\n+\t\t    IXGBE_ACI_I2C_DATA_SIZE_S;\n+\n+\t/* data_size limited to 4 */\n+\tif (data_size > 4)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tcmd->i2c_bus_addr = IXGBE_CPU_TO_LE16(bus_addr);\n+\tcmd->topo_addr = topo_addr;\n+\tcmd->i2c_params = params;\n+\tcmd->i2c_addr = addr;\n+\n+\tfor (i = 0; i < data_size; i++) {\n+\t\tcmd->i2c_data[i] = *data;\n+\t\tdata++;\n+\t}\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_set_gpio - set GPIO pin state\n+ * @hw: pointer to the hw struct\n+ * @gpio_ctrl_handle: GPIO controller node handle\n+ * @pin_idx: IO Number of the GPIO that needs to be set\n+ * @value: SW provide IO value to set in the LSB\n+ *\n+ * Set the GPIO pin state that is a part of the topology\n+ * using ACI command (0x06EC).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_set_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t       bool value)\n+{\n+\tstruct ixgbe_aci_cmd_gpio *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_gpio);\n+\tcmd = &desc.params.read_write_gpio;\n+\tcmd->gpio_ctrl_handle = IXGBE_CPU_TO_LE16(gpio_ctrl_handle);\n+\tcmd->gpio_num = pin_idx;\n+\tcmd->gpio_val = value ? 1 : 0;\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_get_gpio - get GPIO pin state\n+ * @hw: pointer to the hw struct\n+ * @gpio_ctrl_handle: GPIO controller node handle\n+ * @pin_idx: IO Number of the GPIO that needs to be set\n+ * @value: IO value read\n+ *\n+ * Get the value of a GPIO signal which is part of the topology\n+ * using ACI command (0x06ED).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t       bool *value)\n+{\n+\tstruct ixgbe_aci_cmd_gpio *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_gpio);\n+\tcmd = &desc.params.read_write_gpio;\n+\tcmd->gpio_ctrl_handle = IXGBE_CPU_TO_LE16(gpio_ctrl_handle);\n+\tcmd->gpio_num = pin_idx;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (status)\n+\t\treturn status;\n+\n+\t*value = !!cmd->gpio_val;\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_aci_sff_eeprom - read/write SFF EEPROM\n+ * @hw: pointer to the HW struct\n+ * @lport: bits [7:0] = logical port, bit [8] = logical port valid\n+ * @bus_addr: I2C bus address of the eeprom (typically 0xA0, 0=topo default)\n+ * @mem_addr: I2C offset. lower 8 bits for address, 8 upper bits zero padding.\n+ * @page: QSFP page\n+ * @page_bank_ctrl: configuration of SFF/CMIS paging and banking control\n+ * @data: pointer to data buffer to be read/written to the I2C device.\n+ * @length: 1-16 for read, 1 for write.\n+ * @write: 0 read, 1 for write.\n+ *\n+ * Read/write SFF EEPROM using ACI command (0x06EE).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_sff_eeprom(struct ixgbe_hw *hw, u16 lport, u8 bus_addr,\n+\t\t\t u16 mem_addr, u8 page, u8 page_bank_ctrl, u8 *data,\n+\t\t\t u8 length, bool write)\n+{\n+\tstruct ixgbe_aci_cmd_sff_eeprom *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tif (!data || (mem_addr & 0xff00))\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_sff_eeprom);\n+\tcmd = &desc.params.read_write_sff_param;\n+\tdesc.flags = IXGBE_CPU_TO_LE16(IXGBE_ACI_FLAG_RD);\n+\tcmd->lport_num = (u8)(lport & 0xff);\n+\tcmd->lport_num_valid = (u8)((lport >> 8) & 0x01);\n+\tcmd->i2c_bus_addr = IXGBE_CPU_TO_LE16(((bus_addr >> 1) &\n+\t\t\t\t\t IXGBE_ACI_SFF_I2CBUS_7BIT_M) |\n+\t\t\t\t\t((page_bank_ctrl <<\n+\t\t\t\t\t  IXGBE_ACI_SFF_PAGE_BANK_CTRL_S) &\n+\t\t\t\t\t IXGBE_ACI_SFF_PAGE_BANK_CTRL_M));\n+\tcmd->i2c_offset = IXGBE_CPU_TO_LE16(mem_addr & 0xff);\n+\tcmd->module_page = page;\n+\tif (write)\n+\t\tcmd->i2c_bus_addr |= IXGBE_CPU_TO_LE16(IXGBE_ACI_SFF_IS_WRITE);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, data, length);\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_prog_topo_dev_nvm - program Topology Device NVM\n+ * @hw: pointer to the hardware structure\n+ * @topo_params: pointer to structure storing topology parameters for a device\n+ *\n+ * Program Topology Device NVM using ACI command (0x06F2).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_prog_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params)\n+{\n+\tstruct ixgbe_aci_cmd_prog_topo_dev_nvm *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tcmd = &desc.params.prog_topo_dev_nvm;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_prog_topo_dev_nvm);\n+\n+\tmemcpy(&cmd->topo_params, topo_params, sizeof(*topo_params));\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_read_topo_dev_nvm - read Topology Device NVM\n+ * @hw: pointer to the hardware structure\n+ * @topo_params: pointer to structure storing topology parameters for a device\n+ * @start_address: byte offset in the topology device NVM\n+ * @data: pointer to data buffer\n+ * @data_size: number of bytes to be read from the topology device NVM\n+ * Read Topology Device NVM (0x06F3)\n+ *\n+ * Read Topology of Device NVM using ACI command (0x06F3).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_read_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params,\n+\t\t\tu32 start_address, u8 *data, u8 data_size)\n+{\n+\tstruct ixgbe_aci_cmd_read_topo_dev_nvm *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tif (!data || data_size == 0 ||\n+\t    data_size > IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tcmd = &desc.params.read_topo_dev_nvm;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_read_topo_dev_nvm);\n+\n+\tdesc.datalen = IXGBE_CPU_TO_LE16(data_size);\n+\tmemcpy(&cmd->topo_params, topo_params, sizeof(*topo_params));\n+\tcmd->start_address = IXGBE_CPU_TO_LE32(start_address);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (status)\n+\t\treturn status;\n+\n+\tmemcpy(data, cmd->data_read, data_size);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_acquire_nvm - Generic request for acquiring the NVM ownership\n+ * @hw: pointer to the HW structure\n+ * @access: NVM access type (read or write)\n+ *\n+ * Request NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_acquire_nvm(struct ixgbe_hw *hw,\n+\t\t      enum ixgbe_aci_res_access_type access)\n+{\n+\tu32 fla;\n+\n+\t/* Skip if we are in blank NVM programming mode */\n+\tfla = IXGBE_READ_REG(hw, GLNVM_FLA);\n+\tif ((fla & GLNVM_FLA_LOCKED_M) == 0)\n+\t\treturn IXGBE_SUCCESS;\n+\n+\treturn ixgbe_acquire_res(hw, IXGBE_NVM_RES_ID, access,\n+\t\t\t\t IXGBE_NVM_TIMEOUT);\n+}\n+\n+/**\n+ * ixgbe_release_nvm - Generic request for releasing the NVM ownership\n+ * @hw: pointer to the HW structure\n+ *\n+ * Release NVM ownership.\n+ */\n+void ixgbe_release_nvm(struct ixgbe_hw *hw)\n+{\n+\tu32 fla;\n+\n+\t/* Skip if we are in blank NVM programming mode */\n+\tfla = IXGBE_READ_REG(hw, GLNVM_FLA);\n+\tif ((fla & GLNVM_FLA_LOCKED_M) == 0)\n+\t\treturn;\n+\n+\tixgbe_release_res(hw, IXGBE_NVM_RES_ID);\n+}\n+\n+\n+/**\n+ * ixgbe_aci_read_nvm - read NVM\n+ * @hw: pointer to the HW struct\n+ * @module_typeid: module pointer location in words from the NVM beginning\n+ * @offset: byte offset from the module beginning\n+ * @length: length of the section to be read (in bytes from the offset)\n+ * @data: command buffer (size [bytes] = length)\n+ * @last_command: tells if this is the last command in a series\n+ * @read_shadow_ram: tell if this is a shadow RAM read\n+ *\n+ * Read the NVM using ACI command (0x0701).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,\n+\t\t       u16 length, void *data, bool last_command,\n+\t\t       bool read_shadow_ram)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\tstruct ixgbe_aci_cmd_nvm *cmd;\n+\n+\tcmd = &desc.params.nvm;\n+\n+\tif (offset > IXGBE_ACI_NVM_MAX_OFFSET)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_read);\n+\n+\tif (!read_shadow_ram && module_typeid == IXGBE_ACI_NVM_START_POINT)\n+\t\tcmd->cmd_flags |= IXGBE_ACI_NVM_FLASH_ONLY;\n+\n+\t/* If this is the last command in a series, set the proper flag. */\n+\tif (last_command)\n+\t\tcmd->cmd_flags |= IXGBE_ACI_NVM_LAST_CMD;\n+\tcmd->module_typeid = IXGBE_CPU_TO_LE16(module_typeid);\n+\tcmd->offset_low = IXGBE_CPU_TO_LE16(offset & 0xFFFF);\n+\tcmd->offset_high = (offset >> 16) & 0xFF;\n+\tcmd->length = IXGBE_CPU_TO_LE16(length);\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, data, length);\n+}\n+\n+/**\n+ * ixgbe_nvm_validate_checksum - validate checksum\n+ * @hw: pointer to the HW struct\n+ *\n+ * Verify NVM PFA checksum validity using ACI command (0x0706).\n+ * If the checksum verification failed, IXGBE_ERR_NVM_CHECKSUM is returned.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_nvm_checksum *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tcmd = &desc.params.nvm_checksum;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum);\n+\tcmd->flags = IXGBE_ACI_NVM_CHECKSUM_VERIFY;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\tif (!status)\n+\t\tif (IXGBE_LE16_TO_CPU(cmd->checksum) !=\n+\t\t    IXGBE_ACI_NVM_CHECKSUM_CORRECT) {\n+\t\t\tERROR_REPORT1(IXGBE_ERROR_INVALID_STATE,\n+\t\t\t\t      \"Invalid Shadow Ram checksum\");\n+\t\t\tstatus = IXGBE_ERR_NVM_CHECKSUM;\n+\t\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_nvm_recalculate_checksum - recalculate checksum\n+ * @hw: pointer to the HW struct\n+ *\n+ * Recalculate NVM PFA checksum using ACI command (0x0706).\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_nvm_recalculate_checksum(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_nvm_checksum *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tcmd = &desc.params.nvm_checksum;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum);\n+\tcmd->flags = IXGBE_ACI_NVM_CHECKSUM_RECALC;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_get_flash_bank_offset - Get offset into requested flash bank\n+ * @hw: pointer to the HW structure\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @module: the module to read from\n+ *\n+ * Based on the module, lookup the module offset from the beginning of the\n+ * flash.\n+ *\n+ * Return: the flash offset. Note that a value of zero is invalid and must be\n+ * treated as an error.\n+ */\n+static u32 ixgbe_get_flash_bank_offset(struct ixgbe_hw *hw,\n+\t\t\t\t       enum ixgbe_bank_select bank,\n+\t\t\t\t       u16 module)\n+{\n+\tstruct ixgbe_bank_info *banks = &hw->flash.banks;\n+\tenum ixgbe_flash_bank active_bank;\n+\tbool second_bank_active;\n+\tu32 offset, size;\n+\n+\tswitch (module) {\n+\tcase E610_SR_1ST_NVM_BANK_PTR:\n+\t\toffset = banks->nvm_ptr;\n+\t\tsize = banks->nvm_size;\n+\t\tactive_bank = banks->nvm_bank;\n+\t\tbreak;\n+\tcase E610_SR_1ST_OROM_BANK_PTR:\n+\t\toffset = banks->orom_ptr;\n+\t\tsize = banks->orom_size;\n+\t\tactive_bank = banks->orom_bank;\n+\t\tbreak;\n+\tcase E610_SR_NETLIST_BANK_PTR:\n+\t\toffset = banks->netlist_ptr;\n+\t\tsize = banks->netlist_size;\n+\t\tactive_bank = banks->netlist_bank;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\tswitch (active_bank) {\n+\tcase IXGBE_1ST_FLASH_BANK:\n+\t\tsecond_bank_active = false;\n+\t\tbreak;\n+\tcase IXGBE_2ND_FLASH_BANK:\n+\t\tsecond_bank_active = true;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+    }\n+\n+\t/* The second flash bank is stored immediately following the first\n+\t * bank. Based on whether the 1st or 2nd bank is active, and whether\n+\t * we want the active or inactive bank, calculate the desired offset.\n+\t */\n+\tswitch (bank) {\n+\tcase IXGBE_ACTIVE_FLASH_BANK:\n+\t\treturn offset + (second_bank_active ? size : 0);\n+\tcase IXGBE_INACTIVE_FLASH_BANK:\n+\t\treturn offset + (second_bank_active ? 0 : size);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ixgbe_read_flash_module - Read a word from one of the main NVM modules\n+ * @hw: pointer to the HW structure\n+ * @bank: which bank of the module to read\n+ * @module: the module to read\n+ * @offset: the offset into the module in bytes\n+ * @data: storage for the word read from the flash\n+ * @length: bytes of data to read\n+ *\n+ * Read data from the specified flash module. The bank parameter indicates\n+ * whether or not to read from the active bank or the inactive bank of that\n+ * module.\n+ *\n+ * The word will be read using flat NVM access, and relies on the\n+ * hw->flash.banks data being setup by ixgbe_determine_active_flash_banks()\n+ * during initialization.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_flash_module(struct ixgbe_hw *hw,\n+\t\t\t\t   enum ixgbe_bank_select bank,\n+\t\t\t\t   u16 module, u32 offset, u8 *data, u32 length)\n+{\n+\ts32 status;\n+\tu32 start;\n+\n+\tstart = ixgbe_get_flash_bank_offset(hw, bank, module);\n+\tif (!start) {\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_flat_nvm(hw, start + offset, &length, data, false);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_read_nvm_module - Read from the active main NVM module\n+ * @hw: pointer to the HW structure\n+ * @bank: whether to read from active or inactive NVM module\n+ * @offset: offset into the NVM module to read, in words\n+ * @data: storage for returned word value\n+ *\n+ * Read the specified word from the active NVM module. This includes the CSS\n+ * header at the start of the NVM module.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_nvm_module(struct ixgbe_hw *hw,\n+\t\t\t\t enum ixgbe_bank_select bank,\n+\t\t\t\t  u32 offset, u16 *data)\n+{\n+\t__le16 data_local;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_flash_module(hw, bank, E610_SR_1ST_NVM_BANK_PTR,\n+\t\t\t\t\t offset * sizeof(u16),\n+\t\t\t\t\t (u8 *)&data_local,\n+\t\t\t\t\t sizeof(u16));\n+\tif (!status)\n+\t\t*data = IXGBE_LE16_TO_CPU(data_local);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_get_nvm_css_hdr_len - Read the CSS header length from the\n+ * NVM CSS header\n+ * @hw: pointer to the HW struct\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @hdr_len: storage for header length in words\n+ *\n+ * Read the CSS header length from the NVM CSS header and add the\n+ * Authentication header size, and then convert to words.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_get_nvm_css_hdr_len(struct ixgbe_hw *hw,\n+\t\t\t\t     enum ixgbe_bank_select bank,\n+\t\t\t\t     u32 *hdr_len)\n+{\n+\tu16 hdr_len_l, hdr_len_h;\n+\tu32 hdr_len_dword;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_L,\n+\t\t\t\t       &hdr_len_l);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_HDR_LEN_H,\n+\t\t\t\t       &hdr_len_h);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* CSS header length is in DWORD, so convert to words and add\n+\t * authentication header size\n+\t */\n+\thdr_len_dword = hdr_len_h << 16 | hdr_len_l;\n+\t*hdr_len = (hdr_len_dword * 2) + IXGBE_NVM_AUTH_HEADER_LEN;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_nvm_sr_copy - Read a word from the Shadow RAM copy in the NVM bank\n+ * @hw: pointer to the HW structure\n+ * @bank: whether to read from the active or inactive NVM module\n+ * @offset: offset into the Shadow RAM copy to read, in words\n+ * @data: storage for returned word value\n+ *\n+ * Read the specified word from the copy of the Shadow RAM found in the\n+ * specified NVM module.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_nvm_sr_copy(struct ixgbe_hw *hw,\n+\t\t\t\t  enum ixgbe_bank_select bank,\n+\t\t\t\t  u32 offset, u16 *data)\n+{\n+\tu32 hdr_len;\n+\ts32 status;\n+\n+\tstatus = ixgbe_get_nvm_css_hdr_len(hw, bank, &hdr_len);\n+\tif (status)\n+\t\treturn status;\n+\n+\thdr_len = ROUND_UP(hdr_len, 32);\n+\n+\treturn ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data);\n+}\n+\n+/**\n+ * ixgbe_get_nvm_minsrevs - Get the minsrevs values from flash\n+ * @hw: pointer to the HW struct\n+ * @minsrevs: structure to store NVM and OROM minsrev values\n+ *\n+ * Read the Minimum Security Revision TLV and extract\n+ * the revision values from the flash image\n+ * into a readable structure for processing.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_nvm_minsrevs(struct ixgbe_hw *hw,\n+\t\t\t   struct ixgbe_minsrev_info *minsrevs)\n+{\n+\tstruct ixgbe_aci_cmd_nvm_minsrev data;\n+\ts32 status;\n+\tu16 valid;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_MINSREV_MOD_ID,\n+\t\t\t\t    0, sizeof(data), &data,\n+\t\t\t\t    true, false);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\tif (status)\n+\t\treturn status;\n+\n+\tvalid = IXGBE_LE16_TO_CPU(data.validity);\n+\n+\t/* Extract NVM minimum security revision */\n+\tif (valid & IXGBE_ACI_NVM_MINSREV_NVM_VALID) {\n+\t\tu16 minsrev_l = IXGBE_LE16_TO_CPU(data.nvm_minsrev_l);\n+\t\tu16 minsrev_h = IXGBE_LE16_TO_CPU(data.nvm_minsrev_h);\n+\n+\t\tminsrevs->nvm = minsrev_h << 16 | minsrev_l;\n+\t\tminsrevs->nvm_valid = true;\n+\t}\n+\n+\t/* Extract the OROM minimum security revision */\n+\tif (valid & IXGBE_ACI_NVM_MINSREV_OROM_VALID) {\n+\t\tu16 minsrev_l = IXGBE_LE16_TO_CPU(data.orom_minsrev_l);\n+\t\tu16 minsrev_h = IXGBE_LE16_TO_CPU(data.orom_minsrev_h);\n+\n+\t\tminsrevs->orom = minsrev_h << 16 | minsrev_l;\n+\t\tminsrevs->orom_valid = true;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_get_nvm_srev - Read the security revision from the NVM CSS header\n+ * @hw: pointer to the HW struct\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @srev: storage for security revision\n+ *\n+ * Read the security revision out of the CSS header of the active NVM module\n+ * bank.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_get_nvm_srev(struct ixgbe_hw *hw,\n+\t\t\t      enum ixgbe_bank_select bank, u32 *srev)\n+{\n+\tu16 srev_l, srev_h;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_L, &srev_l);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_nvm_module(hw, bank, IXGBE_NVM_CSS_SREV_H, &srev_h);\n+\tif (status)\n+\t\treturn status;\n+\n+\t*srev = srev_h << 16 | srev_l;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_get_nvm_ver_info - Read NVM version information\n+ * @hw: pointer to the HW struct\n+ * @bank: whether to read from the active or inactive flash bank\n+ * @nvm: pointer to NVM info structure\n+ *\n+ * Read the NVM EETRACK ID and map version of the main NVM image bank, filling\n+ * in the nvm info structure.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_get_nvm_ver_info(struct ixgbe_hw *hw,\n+\t\t\t\t  enum ixgbe_bank_select bank,\n+\t\t\t\t  struct ixgbe_nvm_info *nvm)\n+{\n+\tu16 eetrack_lo, eetrack_hi, ver;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_nvm_sr_copy(hw, bank,\n+\t\t\t\t\tE610_SR_NVM_DEV_STARTER_VER, &ver);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tnvm->major = (ver & E610_NVM_VER_HI_MASK) >> E610_NVM_VER_HI_SHIFT;\n+\tnvm->minor = (ver & E610_NVM_VER_LO_MASK) >> E610_NVM_VER_LO_SHIFT;\n+\n+\tstatus = ixgbe_read_nvm_sr_copy(hw, bank, E610_SR_NVM_EETRACK_LO,\n+\t\t\t\t\t&eetrack_lo);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\tstatus = ixgbe_read_nvm_sr_copy(hw, bank, E610_SR_NVM_EETRACK_HI,\n+\t\t\t\t\t&eetrack_hi);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tnvm->eetrack = (eetrack_hi << 16) | eetrack_lo;\n+\n+\tstatus = ixgbe_get_nvm_srev(hw, bank, &nvm->srev);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_get_inactive_nvm_ver - Read Option ROM version from the inactive bank\n+ * @hw: pointer to the HW structure\n+ * @nvm: storage for Option ROM version information\n+ *\n+ * Reads the NVM EETRACK ID, Map version, and security revision of the\n+ * inactive NVM bank. Used to access version data for a pending update that\n+ * has not yet been activated.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm)\n+{\n+\treturn ixgbe_get_nvm_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, nvm);\n+}\n+\n+/**\n+ * ixgbe_get_active_nvm_ver - Read Option ROM version from the active bank\n+ * @hw: pointer to the HW structure\n+ * @nvm: storage for Option ROM version information\n+ *\n+ * Reads the NVM EETRACK ID, Map version, and security revision of the\n+ * active NVM bank.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm)\n+{\n+\treturn ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, nvm);\n+}\n+\n+/**\n+ * ixgbe_read_sr_pointer - Read the value of a Shadow RAM pointer word\n+ * @hw: pointer to the HW structure\n+ * @offset: the word offset of the Shadow RAM word to read\n+ * @pointer: pointer value read from Shadow RAM\n+ *\n+ * Read the given Shadow RAM word, and convert it to a pointer value specified\n+ * in bytes. This function assumes the specified offset is a valid pointer\n+ * word.\n+ *\n+ * Each pointer word specifies whether it is stored in word size or 4KB\n+ * sector size by using the highest bit. The reported pointer value will be in\n+ * bytes, intended for flat NVM reads.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_sr_pointer(struct ixgbe_hw *hw, u16 offset, u32 *pointer)\n+{\n+\ts32 status;\n+\tu16 value;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, offset, &value);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Determine if the pointer is in 4KB or word units */\n+\tif (value & IXGBE_SR_NVM_PTR_4KB_UNITS)\n+\t\t*pointer = (value & ~IXGBE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;\n+\telse\n+\t\t*pointer = value * 2;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_sr_area_size - Read an area size from a Shadow RAM word\n+ * @hw: pointer to the HW structure\n+ * @offset: the word offset of the Shadow RAM to read\n+ * @size: size value read from the Shadow RAM\n+ *\n+ * Read the given Shadow RAM word, and convert it to an area size value\n+ * specified in bytes. This function assumes the specified offset is a valid\n+ * area size word.\n+ *\n+ * Each area size word is specified in 4KB sector units. This function reports\n+ * the size in bytes, intended for flat NVM reads.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_sr_area_size(struct ixgbe_hw *hw, u16 offset, u32 *size)\n+{\n+\ts32 status;\n+\tu16 value;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, offset, &value);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Area sizes are always specified in 4KB units */\n+\t*size = value * 4 * 1024;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_discover_flash_size - Discover the available flash size.\n+ * @hw: pointer to the HW struct\n+ *\n+ * The device flash could be up to 16MB in size. However, it is possible that\n+ * the actual size is smaller. Use bisection to determine the accessible size\n+ * of flash memory.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_discover_flash_size(struct ixgbe_hw *hw)\n+{\n+\tu32 min_size = 0, max_size = IXGBE_ACI_NVM_MAX_OFFSET + 1;\n+\ts32 status;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\twhile ((max_size - min_size) > 1) {\n+\t\tu32 offset = (max_size + min_size) / 2;\n+\t\tu32 len = 1;\n+\t\tu8 data;\n+\n+\t\tstatus = ixgbe_read_flat_nvm(hw, offset, &len, &data, false);\n+\t\tif (status == IXGBE_ERR_ACI_ERROR &&\n+\t\t    hw->aci.last_status == IXGBE_ACI_RC_EINVAL) {\n+\t\t\tstatus = IXGBE_SUCCESS;\n+\t\t\tmax_size = offset;\n+\t\t} else if (!status) {\n+\t\t\tmin_size = offset;\n+\t\t} else {\n+\t\t\t/* an unexpected error occurred */\n+\t\t\tgoto err_read_flat_nvm;\n+\t\t}\n+\t}\n+\n+\thw->flash.flash_size = max_size;\n+\n+err_read_flat_nvm:\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_determine_active_flash_banks - Discover active bank for each module\n+ * @hw: pointer to the HW struct\n+ *\n+ * Read the Shadow RAM control word and determine which banks are active for\n+ * the NVM, OROM, and Netlist modules. Also read and calculate the associated\n+ * pointer and size. These values are then cached into the ixgbe_flash_info\n+ * structure for later use in order to calculate the correct offset to read\n+ * from the active module.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_determine_active_flash_banks(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_bank_info *banks = &hw->flash.banks;\n+\tu16 ctrl_word;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, E610_SR_NVM_CTRL_WORD, &ctrl_word);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\t/* Check that the control word indicates validity */\n+\tif ((ctrl_word & IXGBE_SR_CTRL_WORD_1_M) >> IXGBE_SR_CTRL_WORD_1_S !=\n+\t    IXGBE_SR_CTRL_WORD_VALID) {\n+\t\treturn IXGBE_ERR_CONFIG;\n+\t}\n+\n+\tif (!(ctrl_word & IXGBE_SR_CTRL_WORD_NVM_BANK))\n+\t\tbanks->nvm_bank = IXGBE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->nvm_bank = IXGBE_2ND_FLASH_BANK;\n+\n+\tif (!(ctrl_word & IXGBE_SR_CTRL_WORD_OROM_BANK))\n+\t\tbanks->orom_bank = IXGBE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->orom_bank = IXGBE_2ND_FLASH_BANK;\n+\n+\tif (!(ctrl_word & IXGBE_SR_CTRL_WORD_NETLIST_BANK))\n+\t\tbanks->netlist_bank = IXGBE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->netlist_bank = IXGBE_2ND_FLASH_BANK;\n+\n+\tstatus = ixgbe_read_sr_pointer(hw, E610_SR_1ST_NVM_BANK_PTR,\n+\t\t\t\t       &banks->nvm_ptr);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_area_size(hw, E610_SR_NVM_BANK_SIZE,\n+\t\t\t\t\t &banks->nvm_size);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_pointer(hw, E610_SR_1ST_OROM_BANK_PTR,\n+\t\t\t\t       &banks->orom_ptr);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_area_size(hw, E610_SR_OROM_BANK_SIZE,\n+\t\t\t\t\t &banks->orom_size);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_pointer(hw, E610_SR_NETLIST_BANK_PTR,\n+\t\t\t\t       &banks->netlist_ptr);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_area_size(hw, E610_SR_NETLIST_BANK_SIZE,\n+\t\t\t\t\t &banks->netlist_size);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_init_nvm - initializes NVM setting\n+ * @hw: pointer to the HW struct\n+ *\n+ * Read and populate NVM settings such as Shadow RAM size,\n+ * max_timeout, and blank_nvm_mode\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_init_nvm(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_flash_info *flash = &hw->flash;\n+\tu32 fla, gens_stat, status;\n+\tu8 sr_size;\n+\n+\t/* The SR size is stored regardless of the NVM programming mode\n+\t * as the blank mode may be used in the factory line.\n+\t */\n+\tgens_stat = IXGBE_READ_REG(hw, GLNVM_GENS);\n+\tsr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;\n+\n+\t/* Switching to words (sr_size contains power of 2) */\n+\tflash->sr_words = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB;\n+\n+\t/* Check if we are in the normal or blank NVM programming mode */\n+\tfla = IXGBE_READ_REG(hw, GLNVM_FLA);\n+\tif (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */\n+\t\tflash->blank_nvm_mode = false;\n+\t} else {\n+\t\t/* Blank programming mode */\n+\t\tflash->blank_nvm_mode = true;\n+\t\treturn IXGBE_ERR_NVM_BLANK_MODE;\n+\t}\n+\n+\tstatus = ixgbe_discover_flash_size(hw);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_determine_active_flash_banks(hw);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK,\n+\t\t\t\t\t&flash->nvm);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_sanitize_operate - Clear the user data\n+ * @hw: pointer to the HW struct\n+ *\n+ * Clear user data from NVM using ACI command (0x070C).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_sanitize_operate(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\tu8 values;\n+\n+\tu8 cmd_flags = IXGBE_ACI_SANITIZE_REQ_OPERATE |\n+\t\t       IXGBE_ACI_SANITIZE_OPERATE_SUBJECT_CLEAR;\n+\n+\tstatus = ixgbe_sanitize_nvm(hw, cmd_flags, &values);\n+\tif (status)\n+\t\treturn status;\n+\tif ((!(values & IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE) &&\n+\t     !(values & IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE)) ||\n+\t    ((values & IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE) &&\n+\t     !(values & IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS)) ||\n+\t    ((values & IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE) &&\n+\t     !(values & IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS)))\n+\t\treturn IXGBE_ERR_ACI_ERROR;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_sanitize_nvm - Sanitize NVM\n+ * @hw: pointer to the HW struct\n+ * @cmd_flags: flag to the ACI command\n+ * @values: values returned from the command\n+ *\n+ * Sanitize NVM using ACI command (0x070C).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_sanitize_nvm(struct ixgbe_hw *hw, u8 cmd_flags, u8 *values)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\tstruct ixgbe_aci_cmd_nvm_sanitization *cmd;\n+\ts32 status;\n+\n+\tcmd = &desc.params.nvm_sanitization;\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_sanitization);\n+\tcmd->cmd_flags = cmd_flags;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (values)\n+\t\t*values = cmd->values;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_read_sr_word_aci - Reads Shadow RAM via ACI\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using ixgbe_read_flat_nvm.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_sr_word_aci(struct ixgbe_hw  *hw, u16 offset, u16 *data)\n+{\n+\tu32 bytes = sizeof(u16);\n+\t__le16 data_local;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_flat_nvm(hw, offset * sizeof(u16), &bytes,\n+\t\t\t\t     (u8 *)&data_local, true);\n+\tif (status)\n+\t\treturn status;\n+\n+\t*data = IXGBE_LE16_TO_CPU(data_local);\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_sr_buf_aci - Reads Shadow RAM buf via ACI\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buf) from the Shadow RAM. Ownership of the NVM is\n+ * taken before reading the buffer and later released.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words,\n+\t\t\t  u16 *data)\n+{\n+\tu32 bytes = *words * 2, i;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_flat_nvm(hw, offset * 2, &bytes, (u8 *)data, true);\n+\n+\t*words = bytes / 2;\n+\n+\tfor (i = 0; i < *words; i++)\n+\t\tdata[i] = IXGBE_LE16_TO_CPU(((__le16 *)data)[i]);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_read_flat_nvm - Read portion of NVM by flat offset\n+ * @hw: pointer to the HW struct\n+ * @offset: offset from beginning of NVM\n+ * @length: (in) number of bytes to read; (out) number of bytes actually read\n+ * @data: buffer to return data in (sized to fit the specified length)\n+ * @read_shadow_ram: if true, read from shadow RAM instead of NVM\n+ *\n+ * Reads a portion of the NVM, as a flat memory space. This function correctly\n+ * breaks read requests across Shadow RAM sectors, prevents Shadow RAM size\n+ * from being exceeded in case of Shadow RAM read requests and ensures that no\n+ * single read request exceeds the maximum 4KB read for a single admin command.\n+ *\n+ * Returns a status code on failure. Note that the data pointer may be\n+ * partially updated if some reads succeed before a failure.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_flat_nvm(struct ixgbe_hw  *hw, u32 offset, u32 *length,\n+\t\t\tu8 *data, bool read_shadow_ram)\n+{\n+\tu32 inlen = *length;\n+\tu32 bytes_read = 0;\n+\tbool last_cmd;\n+\ts32 status;\n+\n+\t*length = 0;\n+\n+\t/* Verify the length of the read if this is for the Shadow RAM */\n+\tif (read_shadow_ram && ((offset + inlen) >\n+\t\t\t\t(hw->eeprom.word_size * 2u))) {\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+\n+\tdo {\n+\t\tu32 read_size, sector_offset;\n+\n+\t\t/* ixgbe_aci_read_nvm cannot read more than 4KB at a time.\n+\t\t * Additionally, a read from the Shadow RAM may not cross over\n+\t\t * a sector boundary. Conveniently, the sector size is also 4KB.\n+\t\t */\n+\t\tsector_offset = offset % IXGBE_ACI_MAX_BUFFER_SIZE;\n+\t\tread_size = MIN_T(u32,\n+\t\t\t\t  IXGBE_ACI_MAX_BUFFER_SIZE - sector_offset,\n+\t\t\t\t  inlen - bytes_read);\n+\n+\t\tlast_cmd = !(bytes_read + read_size < inlen);\n+\n+\t\t/* ixgbe_aci_read_nvm takes the length as a u16. Our read_size\n+\t\t * is calculated using a u32, but the IXGBE_ACI_MAX_BUFFER_SIZE\n+\t\t * maximum size guarantees that it will fit within the 2 bytes.\n+\t\t */\n+\t\tstatus = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_START_POINT,\n+\t\t\t\t\t    offset, (u16)read_size,\n+\t\t\t\t\t    data + bytes_read, last_cmd,\n+\t\t\t\t\t    read_shadow_ram);\n+\t\tif (status)\n+\t\t\tbreak;\n+\n+\t\tbytes_read += read_size;\n+\t\toffset += read_size;\n+\t} while (!last_cmd);\n+\n+\t*length = bytes_read;\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_alternate_write - write to alternate structure\n+ * @hw: pointer to the hardware structure\n+ * @reg_addr0: address of first dword to be written\n+ * @reg_val0: value to be written under 'reg_addr0'\n+ * @reg_addr1: address of second dword to be written\n+ * @reg_val1: value to be written under 'reg_addr1'\n+ *\n+ * Write one or two dwords to alternate structure using ACI command (0x0900).\n+ * Fields are indicated by 'reg_addr0' and 'reg_addr1' register numbers.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_write(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t      u32 reg_val0, u32 reg_addr1, u32 reg_val1)\n+{\n+\tstruct ixgbe_aci_cmd_read_write_alt_direct *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.read_write_alt_direct;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_write_alt_direct);\n+\tcmd->dword0_addr = IXGBE_CPU_TO_LE32(reg_addr0);\n+\tcmd->dword1_addr = IXGBE_CPU_TO_LE32(reg_addr1);\n+\tcmd->dword0_value = IXGBE_CPU_TO_LE32(reg_val0);\n+\tcmd->dword1_value = IXGBE_CPU_TO_LE32(reg_val1);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_alternate_read - read from alternate structure\n+ * @hw: pointer to the hardware structure\n+ * @reg_addr0: address of first dword to be read\n+ * @reg_val0: pointer for data read from 'reg_addr0'\n+ * @reg_addr1: address of second dword to be read\n+ * @reg_val1: pointer for data read from 'reg_addr1'\n+ *\n+ * Read one or two dwords from alternate structure using ACI command (0x0902).\n+ * Fields are indicated by 'reg_addr0' and 'reg_addr1' register numbers.\n+ * If 'reg_val1' pointer is not passed then only register at 'reg_addr0'\n+ * is read.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_read(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t     u32 *reg_val0, u32 reg_addr1, u32 *reg_val1)\n+{\n+\tstruct ixgbe_aci_cmd_read_write_alt_direct *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.read_write_alt_direct;\n+\n+\tif (!reg_val0)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_read_alt_direct);\n+\tcmd->dword0_addr = IXGBE_CPU_TO_LE32(reg_addr0);\n+\tcmd->dword1_addr = IXGBE_CPU_TO_LE32(reg_addr1);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tif (status == IXGBE_SUCCESS) {\n+\t\t*reg_val0 = IXGBE_LE32_TO_CPU(cmd->dword0_value);\n+\n+\t\tif (reg_val1)\n+\t\t\t*reg_val1 = IXGBE_LE32_TO_CPU(cmd->dword1_value);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_alternate_write_done - check if writing to alternate structure\n+ * is done\n+ * @hw: pointer to the HW structure.\n+ * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS\n+ * @reset_needed: indicates the SW should trigger GLOBAL reset\n+ *\n+ * Indicates to the FW that alternate structures have been changed.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_write_done(struct ixgbe_hw *hw, u8 bios_mode,\n+\t\t\t\t   bool *reset_needed)\n+{\n+\tstruct ixgbe_aci_cmd_done_alt_write *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.done_alt_write;\n+\n+\tif (!reset_needed)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_done_alt_write);\n+\tcmd->flags = bios_mode;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (!status)\n+\t\t*reset_needed = (IXGBE_LE16_TO_CPU(cmd->flags) &\n+\t\t\t\t IXGBE_ACI_RESP_RESET_NEEDED) != 0;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_alternate_clear - clear alternate structure\n+ * @hw: pointer to the HW structure.\n+ *\n+ * Clear the alternate structures of the port from which the function\n+ * is called.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_clear(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc,\n+\t\t\t\t\tixgbe_aci_opc_clear_port_alt_write);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_get_internal_data - get internal FW/HW data\n+ * @hw: pointer to the hardware structure\n+ * @cluster_id: specific cluster to dump\n+ * @table_id: table ID within cluster\n+ * @start: index of line in the block to read\n+ * @buf: dump buffer\n+ * @buf_size: dump buffer size\n+ * @ret_buf_size: return buffer size (returned by FW)\n+ * @ret_next_cluster: next cluster to read (returned by FW)\n+ * @ret_next_table: next block to read (returned by FW)\n+ * @ret_next_index: next index to read (returned by FW)\n+ *\n+ * Get internal FW/HW data using ACI command (0xFF08) for debug purposes.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_internal_data(struct ixgbe_hw *hw, u16 cluster_id,\n+\t\t\t\tu16 table_id, u32 start, void *buf,\n+\t\t\t\tu16 buf_size, u16 *ret_buf_size,\n+\t\t\t\tu16 *ret_next_cluster, u16 *ret_next_table,\n+\t\t\t\tu32 *ret_next_index)\n+{\n+\tstruct ixgbe_aci_cmd_debug_dump_internals *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.debug_dump;\n+\n+\tif (buf_size == 0 || !buf)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc,\n+\t\t\t\t\tixgbe_aci_opc_debug_dump_internals);\n+\n+\tcmd->cluster_id = IXGBE_CPU_TO_LE16(cluster_id);\n+\tcmd->table_id = IXGBE_CPU_TO_LE16(table_id);\n+\tcmd->idx = IXGBE_CPU_TO_LE32(start);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, buf, buf_size);\n+\n+\tif (!status) {\n+\t\tif (ret_buf_size)\n+\t\t\t*ret_buf_size = IXGBE_LE16_TO_CPU(desc.datalen);\n+\t\tif (ret_next_cluster)\n+\t\t\t*ret_next_cluster = IXGBE_LE16_TO_CPU(cmd->cluster_id);\n+\t\tif (ret_next_table)\n+\t\t\t*ret_next_table = IXGBE_LE16_TO_CPU(cmd->table_id);\n+\t\tif (ret_next_index)\n+\t\t\t*ret_next_index = IXGBE_LE32_TO_CPU(cmd->idx);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_validate_nvm_rw_reg - Check that an NVM access request is valid\n+ * @cmd: NVM access command structure\n+ *\n+ * Validates that an NVM access structure is request to read or write a valid\n+ * register offset. First validates that the module and flags are correct, and\n+ * then ensures that the register offset is one of the accepted registers.\n+ *\n+ * Return: 0 if the register access is valid, out of range error code otherwise.\n+ */\n+static s32\n+ixgbe_validate_nvm_rw_reg(struct ixgbe_nvm_access_cmd *cmd)\n+{\n+\tu16 i;\n+\n+\tswitch (cmd->offset) {\n+\tcase GL_HICR:\n+\tcase GL_HICR_EN: /* Note, this register is read only */\n+\tcase GL_FWSTS:\n+\tcase GL_MNG_FWSM:\n+\tcase GLNVM_GENS:\n+\tcase GLNVM_FLA:\n+\tcase GL_FWRESETCNT:\n+\t\treturn 0;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i <= GL_HIDA_MAX_INDEX; i++)\n+\t\tif (cmd->offset == (u32)GL_HIDA(i))\n+\t\t\treturn 0;\n+\n+\tfor (i = 0; i <= GL_HIBA_MAX_INDEX; i++)\n+\t\tif (cmd->offset == (u32)GL_HIBA(i))\n+\t\t\treturn 0;\n+\n+\t/* All other register offsets are not valid */\n+\treturn IXGBE_ERR_OUT_OF_RANGE;\n+}\n+\n+/**\n+ * ixgbe_nvm_access_read - Handle an NVM read request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command to process\n+ * @data: storage for the register value read\n+ *\n+ * Process an NVM access request to read a register.\n+ *\n+ * Return: 0 if the register read is valid and successful,\n+ * out of range error code otherwise.\n+ */\n+static s32 ixgbe_nvm_access_read(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\tstruct ixgbe_nvm_access_data *data)\n+{\n+\ts32 status;\n+\n+\t/* Always initialize the output data, even on failure */\n+\tmemset(&data->regval, 0, cmd->data_size);\n+\n+\t/* Make sure this is a valid read/write access request */\n+\tstatus = ixgbe_validate_nvm_rw_reg(cmd);\n+\tif (status)\n+\t\treturn status;\n+\n+\tDEBUGOUT1(\"NVM access: reading register %08x\\n\", cmd->offset);\n+\n+\t/* Read the register and store the contents in the data field */\n+\tdata->regval = IXGBE_READ_REG(hw, cmd->offset);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ixgbe_nvm_access_write - Handle an NVM write request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command to process\n+ * @data: NVM access data to write\n+ *\n+ * Process an NVM access request to write a register.\n+ *\n+ * Return: 0 if the register write is valid and successful,\n+ * out of range error code otherwise.\n+ */\n+static s32 ixgbe_nvm_access_write(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\tstruct ixgbe_nvm_access_data *data)\n+{\n+\ts32 status;\n+\n+\t/* Make sure this is a valid read/write access request */\n+\tstatus = ixgbe_validate_nvm_rw_reg(cmd);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Reject requests to write to read-only registers */\n+\tswitch (cmd->offset) {\n+\tcase GL_HICR_EN:\n+\t\treturn IXGBE_ERR_OUT_OF_RANGE;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tDEBUGOUT2(\"NVM access: writing register %08x with value %08x\\n\",\n+\t\tcmd->offset, data->regval);\n+\n+\t/* Write the data field to the specified register */\n+\tIXGBE_WRITE_REG(hw, cmd->offset, data->regval);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ixgbe_handle_nvm_access - Handle an NVM access request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command info\n+ * @data: pointer to read or return data\n+ *\n+ * Process an NVM access request. Read the command structure information and\n+ * determine if it is valid. If not, report an error indicating the command\n+ * was invalid.\n+ *\n+ * For valid commands, perform the necessary function, copying the data into\n+ * the provided data buffer.\n+ *\n+ * Return: 0 if the nvm access request is valid and successful,\n+ * error code otherwise.\n+ */\n+s32 ixgbe_handle_nvm_access(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\tstruct ixgbe_nvm_access_data *data)\n+{\n+\tswitch (cmd->command) {\n+\tcase IXGBE_NVM_CMD_READ:\n+\t\treturn ixgbe_nvm_access_read(hw, cmd, data);\n+\tcase IXGBE_NVM_CMD_WRITE:\n+\t\treturn ixgbe_nvm_access_write(hw, cmd, data);\n+\tdefault:\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+}\n+\n+/**\n+ * ixgbe_init_ops_E610 - Inits func ptrs and MAC type\n+ * @hw: pointer to hardware structure\n+ *\n+ * Initialize the function pointers and assign the MAC type for E610.\n+ * Does not touch the hardware.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_init_ops_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tstruct ixgbe_mac_info *mac = &hw->mac;\n+\tstruct ixgbe_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\n+\tret_val = ixgbe_init_ops_X550(hw);\n+\t/* TODO Additional ops overrides for e610 to go here */\n+\n+\t/* MAC */\n+\tmac->ops.reset_hw = ixgbe_reset_hw_E610;\n+\tmac->ops.start_hw = ixgbe_start_hw_E610;\n+\tmac->ops.get_media_type = ixgbe_get_media_type_E610;\n+\tmac->ops.get_supported_physical_layer =\n+\t\tixgbe_get_supported_physical_layer_E610;\n+\tmac->ops.get_san_mac_addr = NULL;\n+\tmac->ops.set_san_mac_addr = NULL;\n+\tmac->ops.get_wwn_prefix = NULL;\n+\tmac->ops.setup_link = ixgbe_setup_link_E610;\n+\tmac->ops.check_link = ixgbe_check_link_E610;\n+\tmac->ops.get_link_capabilities = ixgbe_get_link_capabilities_E610;\n+\tmac->ops.setup_fc = ixgbe_setup_fc_E610;\n+\tmac->ops.fc_autoneg = ixgbe_fc_autoneg_E610;\n+\tmac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_E610;\n+\tmac->ops.disable_rx = ixgbe_disable_rx_E610;\n+\tmac->ops.setup_eee = ixgbe_setup_eee_E610;\n+\tmac->ops.fw_recovery_mode = ixgbe_fw_recovery_mode_E610;\n+\tmac->ops.get_fw_tsam_mode = ixgbe_get_fw_tsam_mode_E610;\n+\tmac->ops.get_fw_version = ixgbe_aci_get_fw_ver;\n+\tmac->ops.get_nvm_version = ixgbe_get_active_nvm_ver;\n+\n+\t/* PHY */\n+\tphy->ops.init = ixgbe_init_phy_ops_E610;\n+\tphy->ops.identify = ixgbe_identify_phy_E610;\n+\tphy->eee_speeds_supported = IXGBE_LINK_SPEED_10_FULL |\n+\t\t\t\t    IXGBE_LINK_SPEED_100_FULL |\n+\t\t\t\t    IXGBE_LINK_SPEED_1GB_FULL;\n+\tphy->eee_speeds_advertised = phy->eee_speeds_supported;\n+\n+\t/* Additional ops overrides for e610 to go here */\n+\teeprom->ops.init_params = ixgbe_init_eeprom_params_E610;\n+\teeprom->ops.read = ixgbe_read_ee_aci_E610;\n+\teeprom->ops.read_buffer = ixgbe_read_ee_aci_buffer_E610;\n+\teeprom->ops.write = NULL;\n+\teeprom->ops.write_buffer = NULL;\n+\teeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_E610;\n+\teeprom->ops.update_checksum = NULL;\n+\teeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_E610;\n+\teeprom->ops.read_pba_string = ixgbe_read_pba_string_E610;\n+\n+\t/* Initialize bus function number */\n+\thw->mac.ops.set_lan_id(hw);\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * ixgbe_reset_hw_E610 - Perform hardware reset\n+ * @hw: pointer to hardware structure\n+ *\n+ * Resets the hardware by resetting the transmit and receive units, masks\n+ * and clears all interrupts, and perform a reset.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_reset_hw_E610(struct ixgbe_hw *hw)\n+{\n+\tu32 swfw_mask = hw->phy.phy_semaphore_mask;\n+\tu32 ctrl, i;\n+\ts32 status;\n+\n+\tDEBUGFUNC(\"ixgbe_reset_hw_E610\");\n+\n+\t/* Call adapter stop to disable tx/rx and clear interrupts */\n+\tstatus = hw->mac.ops.stop_adapter(hw);\n+\tif (status != IXGBE_SUCCESS)\n+\t\tgoto reset_hw_out;\n+\n+\t/* flush pending Tx transactions */\n+\tixgbe_clear_tx_pending(hw);\n+\n+\tstatus = hw->phy.ops.init(hw);\n+\tif (status != IXGBE_SUCCESS)\n+\t\tDEBUGOUT1(\"Failed to initialize PHY ops, STATUS = %d\\n\",\n+\t\t\t  status);\n+mac_reset_top:\n+\tstatus = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\tERROR_REPORT2(IXGBE_ERROR_CAUTION,\n+\t\t\t      \"semaphore failed with %d\", status);\n+\t\treturn IXGBE_ERR_SWFW_SYNC;\n+\t}\n+\tctrl = IXGBE_CTRL_RST;\n+\tctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);\n+\tIXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);\n+\tIXGBE_WRITE_FLUSH(hw);\n+\thw->mac.ops.release_swfw_sync(hw, swfw_mask);\n+\n+\t/* Poll for reset bit to self-clear indicating reset is complete */\n+\tfor (i = 0; i < 10; i++) {\n+\t\tusec_delay(1);\n+\t\tctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);\n+\t\tif (!(ctrl & IXGBE_CTRL_RST_MASK))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (ctrl & IXGBE_CTRL_RST_MASK) {\n+\t\tstatus = IXGBE_ERR_RESET_FAILED;\n+\t\tERROR_REPORT1(IXGBE_ERROR_POLLING,\n+\t\t\t      \"Reset polling failed to complete.\\n\");\n+\t}\n+\tmsec_delay(100);\n+\n+\t/*\n+\t * Double resets are required for recovery from certain error\n+\t * conditions.  Between resets, it is necessary to stall to allow time\n+\t * for any pending HW events to complete.\n+\t */\n+\tif (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {\n+\t\thw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;\n+\t\tgoto mac_reset_top;\n+\t}\n+\n+\t/* Set the Rx packet buffer size. */\n+\tIXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT);\n+\n+\t/* Store the permanent mac address */\n+\thw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);\n+\n+\t/*\n+\t * Store MAC address from RAR0, clear receive address registers, and\n+\t * clear the multicast table.  Also reset num_rar_entries to 128,\n+\t * since we modify this value when programming the SAN MAC address.\n+\t */\n+\thw->mac.num_rar_entries = 128;\n+\thw->mac.ops.init_rx_addrs(hw);\n+\n+reset_hw_out:\n+\treturn status;\n+}\n+/**\n+ * ixgbe_fw_ver_check - Check the reported FW API version\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Checks if the driver should load on a given FW API version.\n+ *\n+ * Return: 'true' if the driver should attempt to load. 'false' otherwise.\n+ */\n+static bool ixgbe_fw_ver_check(struct ixgbe_hw *hw)\n+{\n+\tif (hw->api_maj_ver > IXGBE_FW_API_VER_MAJOR) {\n+\t\tERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, \"The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\\n\");\n+\t\treturn false;\n+\t} else if (hw->api_maj_ver == IXGBE_FW_API_VER_MAJOR) {\n+\t\tif (hw->api_min_ver >\n+\t\t    (IXGBE_FW_API_VER_MINOR + IXGBE_FW_API_VER_DIFF_ALLOWED)) {\n+\t\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION, \"The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\\n\");\n+\t\t} else if ((hw->api_min_ver + IXGBE_FW_API_VER_DIFF_ALLOWED) <\n+\t\t\t   IXGBE_FW_API_VER_MINOR) {\n+\t\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION, \"The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\\n\");\n+\t\t}\n+\t} else {\n+\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION, \"The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\\n\");\n+\t}\n+\treturn true;\n+}\n+/**\n+ * ixgbe_start_hw_E610 - Prepare hardware for Tx/Rx\n+ * @hw: pointer to hardware structure\n+ *\n+ * Gets firmware version and if API version matches it\n+ * starts the hardware using the generic start_hw function\n+ * and the generation start_hw function.\n+ * Then performs revision-specific operations, if any.\n+ **/\n+s32 ixgbe_start_hw_E610(struct ixgbe_hw *hw)\n+{\n+\ts32 ret_val = IXGBE_SUCCESS;\n+\n+\tret_val = hw->mac.ops.get_fw_version(hw);\n+\tif (ret_val)\n+\t\tgoto out;\n+\n+\tif (!ixgbe_fw_ver_check(hw)) {\n+\t\tret_val = IXGBE_ERR_FW_API_VER;\n+\t\tgoto out;\n+\t}\n+\tret_val = ixgbe_start_hw_generic(hw);\n+\tif (ret_val != IXGBE_SUCCESS)\n+\t\tgoto out;\n+\n+\tixgbe_start_hw_gen2(hw);\n+\n+out:\n+\treturn ret_val;\n+}\n+\n+/**\n+ * ixgbe_get_media_type_E610 - Gets media type\n+ * @hw: pointer to the HW struct\n+ *\n+ * In order to get the media type, the function gets PHY\n+ * capabilities and later on use them to identify the PHY type\n+ * checking phy_type_high and phy_type_low.\n+ *\n+ * Return: the type of media in form of ixgbe_media_type enum\n+ * or ixgbe_media_type_unknown in case of an error.\n+ */\n+enum ixgbe_media_type ixgbe_get_media_type_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data pcaps;\n+\tu64 phy_mask = 0;\n+\ts32 rc;\n+\tu8 i;\n+\n+\trc = ixgbe_update_link_info(hw);\n+\tif (rc) {\n+\t\treturn ixgbe_media_type_unknown;\n+\t}\n+\n+\t/* If there is no link but PHY (dongle) is available SW should use\n+\t * Get PHY Caps admin command instead of Get Link Status, find most\n+\t * significant bit that is set in PHY types reported by the command\n+\t * and use it to discover media type.\n+\t */\n+\tif (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP) &&\n+\t    (hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE)) {\n+\t\t/* Get PHY Capabilities */\n+\t\trc = ixgbe_aci_get_phy_caps(hw, false,\n+\t\t\t\t\t    IXGBE_ACI_REPORT_TOPO_CAP_MEDIA,\n+\t\t\t\t\t    &pcaps);\n+\t\tif (rc) {\n+\t\t\treturn ixgbe_media_type_unknown;\n+\t\t}\n+\n+\t\t/* Check if there is some bit set in phy_type_high */\n+\t\tfor (i = 64; i > 0; i--) {\n+\t\t\tphy_mask = (u64)((u64)1 << (i - 1));\n+\t\t\tif ((pcaps.phy_type_high & phy_mask) != 0) {\n+\t\t\t\t/* If any bit is set treat it as PHY type */\n+\t\t\t\thw->link.link_info.phy_type_high = phy_mask;\n+\t\t\t\thw->link.link_info.phy_type_low = 0;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t\tphy_mask = 0;\n+\t\t}\n+\n+\t\t/* If nothing found in phy_type_high search in phy_type_low */\n+\t\tif (phy_mask == 0) {\n+\t\t\tfor (i = 64; i > 0; i--) {\n+\t\t\t\tphy_mask = (u64)((u64)1 << (i - 1));\n+\t\t\t\tif ((pcaps.phy_type_low & phy_mask) != 0) {\n+\t\t\t\t\t/* If any bit is set treat it as PHY type */\n+\t\t\t\t\thw->link.link_info.phy_type_high = 0;\n+\t\t\t\t\thw->link.link_info.phy_type_low = phy_mask;\n+\t\t\t\t\tbreak;\n+\t\t\t\t}\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* Based on search above try to discover media type */\n+\t\thw->phy.media_type = ixgbe_get_media_type_from_phy_type(hw);\n+\t}\n+\n+\treturn hw->phy.media_type;\n+}\n+\n+/**\n+ * ixgbe_get_supported_physical_layer_E610 - Returns physical layer type\n+ * @hw: pointer to hardware structure\n+ *\n+ * Determines physical layer capabilities of the current configuration.\n+ *\n+ * Return: the exit code of the operation.\n+ **/\n+u64 ixgbe_get_supported_physical_layer_E610(struct ixgbe_hw *hw)\n+{\n+\tu64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data pcaps;\n+\tu64 phy_type;\n+\ts32 rc;\n+\n+\trc = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_TOPO_CAP_MEDIA,\n+\t\t\t\t    &pcaps);\n+\tif (rc)\n+\t\treturn IXGBE_PHYSICAL_LAYER_UNKNOWN;\n+\n+\tphy_type = IXGBE_LE64_TO_CPU(pcaps.phy_type_low);\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_1000BASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_100BASE_TX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_LR)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_LR;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_SR)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_SR;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_1000BASE_KX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_1000BASE_SX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_SX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_2500BASE_KX)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_2500BASE_KX;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_2500BASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_2500BASE_T;\n+\tif(phy_type & IXGBE_PHY_TYPE_LOW_5GBASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_5000BASE_T;\n+\n+\tphy_type = IXGBE_LE64_TO_CPU(pcaps.phy_type_high);\n+\tif(phy_type & IXGBE_PHY_TYPE_HIGH_10BASE_T)\n+\t\tphysical_layer |= IXGBE_PHYSICAL_LAYER_10BASE_T;\n+\n+\treturn physical_layer;\n+}\n+\n+/**\n+ * ixgbe_setup_link_E610 - Set up link\n+ * @hw: pointer to hardware structure\n+ * @speed: new link speed\n+ * @autoneg_wait: true when waiting for completion is needed\n+ *\n+ * Set up the link with the specified speed.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_setup_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n+\t\t\t  bool autoneg_wait)\n+{\n+\n+\t/* Simply request FW to perform proper PHY setup */\n+\treturn hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait);\n+}\n+\n+/**\n+ * ixgbe_check_link_E610 - Determine link and speed status\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @link_up: true when link is up\n+ * @link_up_wait_to_complete: bool used to wait for link up or not\n+ *\n+ * Determine if the link is up and the current link speed\n+ * using ACI command (0x0607).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_check_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n+\t\t\t  bool *link_up, bool link_up_wait_to_complete)\n+{\n+\ts32 rc;\n+\tu32 i;\n+\n+\tif (!speed || !link_up)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\t/* Set get_link_info flag to ensure that fresh\n+\t * link information will be obtained from FW\n+\t * by sending Get Link Status admin command. */\n+\thw->link.get_link_info = true;\n+\n+\t/* Update link information in adapter context. */\n+\trc = ixgbe_get_link_status(hw, link_up);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\t/* Wait for link up if it was requested. */\n+\tif (link_up_wait_to_complete && *link_up == false) {\n+\t\tfor (i = 0; i < hw->mac.max_link_up_time; i++) {\n+\t\t\tmsec_delay(100);\n+\t\t\thw->link.get_link_info = true;\n+\t\t\trc = ixgbe_get_link_status(hw, link_up);\n+\t\t\tif (rc)\n+\t\t\t\treturn rc;\n+\t\t\tif (*link_up)\n+\t\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\t/* Use link information in adapter context updated by the call\n+\t * to ixgbe_get_link_status() to determine current link speed.\n+\t * Link speed information is valid only when link up was\n+\t * reported by FW. */\n+\tif (*link_up) {\n+\t\tswitch (hw->link.link_info.link_speed) {\n+\t\tcase IXGBE_ACI_LINK_SPEED_10MB:\n+\t\t\t*speed = IXGBE_LINK_SPEED_10_FULL;\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_LINK_SPEED_100MB:\n+\t\t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_LINK_SPEED_1000MB:\n+\t\t\t*speed = IXGBE_LINK_SPEED_1GB_FULL;\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_LINK_SPEED_2500MB:\n+\t\t\t*speed = IXGBE_LINK_SPEED_2_5GB_FULL;\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_LINK_SPEED_5GB:\n+\t\t\t*speed = IXGBE_LINK_SPEED_5GB_FULL;\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_LINK_SPEED_10GB:\n+\t\t\t*speed = IXGBE_LINK_SPEED_10GB_FULL;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n+\t\t\tbreak;\n+\t\t}\n+\t} else {\n+\t\t*speed = IXGBE_LINK_SPEED_UNKNOWN;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_get_link_capabilities_E610 - Determine link capabilities\n+ * @hw: pointer to hardware structure\n+ * @speed: pointer to link speed\n+ * @autoneg: true when autoneg or autotry is enabled\n+ *\n+ * Determine speed and AN parameters of a link.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_link_capabilities_E610(struct ixgbe_hw *hw,\n+\t\t\t\t     ixgbe_link_speed *speed,\n+\t\t\t\t     bool *autoneg)\n+{\n+\n+\tif (!speed || !autoneg)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\t*autoneg = true;\n+\t*speed = hw->phy.speeds_supported;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_cfg_phy_fc - Configure PHY Flow Control (FC) data based on FC mode\n+ * @hw: pointer to hardware structure\n+ * @cfg: PHY configuration data to set FC mode\n+ * @req_mode: FC mode to configure\n+ *\n+ * Configures PHY Flow Control according to the provided configuration.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_cfg_phy_fc(struct ixgbe_hw *hw,\n+\t\t     struct ixgbe_aci_cmd_set_phy_cfg_data *cfg,\n+\t\t     enum ixgbe_fc_mode req_mode)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data* pcaps = NULL;\n+\ts32 status = IXGBE_SUCCESS;\n+\tu8 pause_mask = 0x0;\n+\n+\tif (!cfg)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tswitch (req_mode) {\n+\tcase ixgbe_fc_auto:\n+\t{\n+\t\tpcaps = (struct ixgbe_aci_cmd_get_phy_caps_data *)\n+\t\t\tixgbe_malloc(hw, sizeof(*pcaps));\n+\t\tif (!pcaps) {\n+\t\t\tstatus = IXGBE_ERR_OUT_OF_MEM;\n+\t\t\tgoto out;\n+\t\t}\n+\n+\t\t/* Query the value of FC that both the NIC and the attached\n+\t\t * media can do. */\n+\t\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\t\tIXGBE_ACI_REPORT_TOPO_CAP_MEDIA, pcaps);\n+\t\tif (status)\n+\t\t\tgoto out;\n+\n+\t\tpause_mask |= pcaps->caps & IXGBE_ACI_PHY_EN_TX_LINK_PAUSE;\n+\t\tpause_mask |= pcaps->caps & IXGBE_ACI_PHY_EN_RX_LINK_PAUSE;\n+\n+\t\tbreak;\n+\t}\n+\tcase ixgbe_fc_full:\n+\t\tpause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE;\n+\t\tpause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE;\n+\t\tbreak;\n+\tcase ixgbe_fc_rx_pause:\n+\t\tpause_mask |= IXGBE_ACI_PHY_EN_RX_LINK_PAUSE;\n+\t\tbreak;\n+\tcase ixgbe_fc_tx_pause:\n+\t\tpause_mask |= IXGBE_ACI_PHY_EN_TX_LINK_PAUSE;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\t/* clear the old pause settings */\n+\tcfg->caps &= ~(IXGBE_ACI_PHY_EN_TX_LINK_PAUSE |\n+\t\tIXGBE_ACI_PHY_EN_RX_LINK_PAUSE);\n+\n+\t/* set the new capabilities */\n+\tcfg->caps |= pause_mask;\n+\n+out:\n+\tif (pcaps)\n+\t\tixgbe_free(hw, pcaps);\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_setup_fc_E610 - Set up flow control\n+ * @hw: pointer to hardware structure\n+ *\n+ * Set up flow control. This has to be done during init time.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_setup_fc_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data pcaps = { 0 };\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data cfg = { 0 };\n+\ts32 status;\n+\n+\t/* Get the current PHY config */\n+\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\tIXGBE_ACI_REPORT_ACTIVE_CFG, &pcaps);\n+\tif (status)\n+\t\treturn status;\n+\n+\tixgbe_copy_phy_caps_to_cfg(&pcaps, &cfg);\n+\n+\t/* Configure the set PHY data */\n+\tstatus = ixgbe_cfg_phy_fc(hw, &cfg, hw->fc.requested_mode);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* If the capabilities have changed, then set the new config */\n+\tif (cfg.caps != pcaps.caps) {\n+\t\tcfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\t\tstatus = ixgbe_aci_set_phy_cfg(hw, &cfg);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_fc_autoneg_E610 - Configure flow control\n+ * @hw: pointer to hardware structure\n+ *\n+ * Configure Flow Control.\n+ */\n+void ixgbe_fc_autoneg_E610(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\n+\t/* Get current link status.\n+\t * Current FC mode will be stored in the hw context. */\n+\tstatus = ixgbe_aci_get_link_info(hw, false, NULL);\n+\tif (status) {\n+\t\tgoto out;\n+\t}\n+\n+\t/* Check if the link is up */\n+\tif (!(hw->link.link_info.link_info & IXGBE_ACI_LINK_UP)) {\n+\t\tstatus = IXGBE_ERR_FC_NOT_NEGOTIATED;\n+\t\tgoto out;\n+\t}\n+\n+\t/* Check if auto-negotiation has completed */\n+\tif (!(hw->link.link_info.an_info & IXGBE_ACI_AN_COMPLETED)) {\n+\t\tstatus = IXGBE_ERR_FC_NOT_NEGOTIATED;\n+\t\tgoto out;\n+\t}\n+\n+out:\n+\tif (status == IXGBE_SUCCESS) {\n+\t\thw->fc.fc_was_autonegged = true;\n+\t} else {\n+\t\thw->fc.fc_was_autonegged = false;\n+\t\thw->fc.current_mode = hw->fc.requested_mode;\n+\t}\n+}\n+\n+/**\n+ * ixgbe_set_fw_drv_ver_E610 - Send driver version to FW\n+ * @hw: pointer to the HW structure\n+ * @maj: driver version major number\n+ * @minor: driver version minor number\n+ * @build: driver version build number\n+ * @sub: driver version sub build number\n+ * @len: length of driver_ver string\n+ * @driver_ver: driver string\n+ *\n+ * Send driver version number to Firmware using ACI command (0x0002).\n+ *\n+ * Return: the exit code of the operation.\n+ * IXGBE_SUCCESS - OK\n+ * IXGBE_ERR_PARAM - incorrect parameters were given\n+ * IXGBE_ERR_ACI_ERROR - encountered an error during sending the command\n+ * IXGBE_ERR_ACI_TIMEOUT - a timeout occurred\n+ * IXGBE_ERR_OUT_OF_MEM - ran out of memory\n+ */\n+s32 ixgbe_set_fw_drv_ver_E610(struct ixgbe_hw *hw, u8 maj, u8 minor, u8 build,\n+\t\t\t      u8 sub, u16 len, const char *driver_ver)\n+{\n+\tsize_t limited_len = min(len, (u16)IXGBE_DRV_VER_STR_LEN_E610);\n+\tstruct ixgbe_driver_ver dv;\n+\n+\tDEBUGFUNC(\"ixgbe_set_fw_drv_ver_E610\");\n+\n+\tif (!len || !driver_ver)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tdv.major_ver = maj;\n+\tdv.minor_ver = minor;\n+\tdv.build_ver = build;\n+\tdv.subbuild_ver = sub;\n+\n+\tmemset(dv.driver_string, 0, IXGBE_DRV_VER_STR_LEN_E610);\n+\tmemcpy(dv.driver_string, driver_ver, limited_len);\n+\n+\treturn ixgbe_aci_send_driver_ver(hw, &dv);\n+}\n+\n+/**\n+ * ixgbe_disable_rx_E610 - Disable RX unit\n+ * @hw: pointer to hardware structure\n+ *\n+ * Disable RX DMA unit on E610 with use of ACI command (0x000C).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+void ixgbe_disable_rx_E610(struct ixgbe_hw *hw)\n+{\n+\tu32 rxctrl;\n+\n+\tDEBUGFUNC(\"ixgbe_disable_rx_E610\");\n+\n+\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n+\tif (rxctrl & IXGBE_RXCTRL_RXEN) {\n+\t\tu32 pfdtxgswc;\n+\t\ts32 status;\n+\n+\t\tpfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);\n+\t\tif (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {\n+\t\t\tpfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;\n+\t\t\tIXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);\n+\t\t\thw->mac.set_lben = true;\n+\t\t} else {\n+\t\t\thw->mac.set_lben = false;\n+\t\t}\n+\n+\t\tstatus = ixgbe_aci_disable_rxen(hw);\n+\n+\t\t/* If we fail - disable RX using register write */\n+\t\tif (status) {\n+\t\t\trxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);\n+\t\t\tif (rxctrl & IXGBE_RXCTRL_RXEN) {\n+\t\t\t\trxctrl &= ~IXGBE_RXCTRL_RXEN;\n+\t\t\t\tIXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);\n+\t\t\t}\n+\t\t}\n+\t}\n+}\n+\n+/**\n+ * ixgbe_setup_eee_E610 - Enable/disable EEE support\n+ * @hw: pointer to the HW structure\n+ * @enable_eee: boolean flag to enable EEE\n+ *\n+ * Enables/disable EEE based on enable_eee flag.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_setup_eee_E610(struct ixgbe_hw *hw, bool enable_eee)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data phy_caps = { 0 };\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = { 0 };\n+\tu16 eee_cap = 0;\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\tIXGBE_ACI_REPORT_ACTIVE_CFG, &phy_caps);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\tixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg);\n+\n+\tphy_cfg.caps |= IXGBE_ACI_PHY_ENA_LINK;\n+\tphy_cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\tif (enable_eee) {\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_100BASE_TX)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_100BASE_TX;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_T)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_1000BASE_T;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_1000BASE_KX)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_1000BASE_KX;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_T)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_10GBASE_T;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_10GBASE_KR;\n+\t\tif (phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_25GBASE_KR   ||\n+\t\t    phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_25GBASE_KR_S ||\n+\t\t    phy_caps.phy_type_low & IXGBE_PHY_TYPE_LOW_25GBASE_KR1)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_25GBASE_KR;\n+\n+\t\tif (phy_caps.phy_type_high & IXGBE_PHY_TYPE_HIGH_10BASE_T)\n+\t\t\teee_cap |= IXGBE_ACI_PHY_EEE_EN_10BASE_T;\n+\t}\n+\n+\t/* Set EEE capability for particular PHY types */\n+\tphy_cfg.eee_cap = IXGBE_CPU_TO_LE16(eee_cap);\n+\n+\tstatus = ixgbe_aci_set_phy_cfg(hw, &phy_cfg);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_fw_recovery_mode_E610 - Check FW NVM recovery mode\n+ * @hw: pointer to hardware structure\n+ *\n+ * Checks FW NVM recovery mode by\n+ * reading the value of the dedicated register.\n+ *\n+ * Return: true if FW is in recovery mode, otherwise false.\n+ */\n+bool ixgbe_fw_recovery_mode_E610(struct ixgbe_hw *hw)\n+{\n+\tu32 fwsm = IXGBE_READ_REG(hw, GL_MNG_FWSM);\n+\n+\treturn !!(fwsm & GL_MNG_FWSM_FW_MODES_RECOVERY_M);\n+}\n+\n+/**\n+ * ixgbe_get_fw_tsam_mode_E610 - Check FW NVM Thermal Sensor Autonomous Mode\n+ * @hw: pointer to hardware structure\n+ *\n+ * Checks Thermal Sensor Autonomous Mode by reading the\n+ * value of the dedicated register.\n+ *\n+ * Return: true if FW is in TSAM, otherwise false.\n+ */\n+bool ixgbe_get_fw_tsam_mode_E610(struct ixgbe_hw *hw)\n+{\n+\tu32 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM_X550EM_a);\n+\n+\treturn !!(fwsm & IXGBE_FWSM_TS_ENABLED);\n+}\n+\n+/**\n+ * ixgbe_init_phy_ops_E610 - PHY specific init\n+ * @hw: pointer to hardware structure\n+ *\n+ * Initialize any function pointers that were not able to be\n+ * set during init_shared_code because the PHY type was not known.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_init_phy_ops_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_mac_info *mac = &hw->mac;\n+\tstruct ixgbe_phy_info *phy = &hw->phy;\n+\ts32 ret_val;\n+\n+\tphy->ops.identify_sfp = ixgbe_identify_module_E610;\n+\tphy->ops.read_reg = NULL; /* PHY reg access is not required */\n+\tphy->ops.write_reg = NULL;\n+\tphy->ops.read_reg_mdi = NULL;\n+\tphy->ops.write_reg_mdi = NULL;\n+\tphy->ops.setup_link = ixgbe_setup_phy_link_E610;\n+\tphy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_E610;\n+\tphy->ops.read_i2c_byte = NULL; /* disabled for E610 */\n+\tphy->ops.write_i2c_byte = NULL; /* disabled for E610 */\n+\tphy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_E610;\n+\tphy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_E610;\n+\tphy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_E610;\n+\tphy->ops.i2c_bus_clear = NULL; /* do not use generic implementation  */\n+\tphy->ops.check_overtemp = ixgbe_check_overtemp_E610;\n+\tif (mac->ops.get_media_type(hw) == ixgbe_media_type_copper)\n+\t\tphy->ops.set_phy_power = ixgbe_set_phy_power_E610;\n+\telse\n+\t\tphy->ops.set_phy_power = NULL;\n+\tphy->ops.enter_lplu = ixgbe_enter_lplu_E610;\n+\tphy->ops.handle_lasi = NULL; /* no implementation for E610 */\n+\tphy->ops.read_i2c_byte_unlocked = NULL; /* disabled for E610 */\n+\tphy->ops.write_i2c_byte_unlocked = NULL; /* disabled for E610 */\n+\n+\t/* TODO: Set functions pointers based on device ID */\n+\n+\t/* Identify the PHY */\n+\tret_val = phy->ops.identify(hw);\n+\tif (ret_val != IXGBE_SUCCESS)\n+\t\treturn ret_val;\n+\n+\t/* TODO: Set functions pointers based on PHY type */\n+\n+\treturn ret_val;\n+}\n+\n+/**\n+ * ixgbe_identify_phy_E610 - Identify PHY\n+ * @hw: pointer to hardware structure\n+ * \n+ * Determine PHY type, supported speeds and PHY ID.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_identify_phy_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data pcaps;\n+\ts32 rc;\n+\n+\t/* Set PHY type */\n+\thw->phy.type = ixgbe_phy_fw;\n+\n+\trc = ixgbe_aci_get_phy_caps(hw, false, IXGBE_ACI_REPORT_TOPO_CAP_MEDIA,\n+\t\t\t\t    &pcaps);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tif (!(pcaps.module_compliance_enforcement &\n+\t      IXGBE_ACI_MOD_ENFORCE_STRICT_MODE)) {\n+\t\t/* Handle lenient mode */\n+\t\trc = ixgbe_aci_get_phy_caps(hw, false,\n+\t\t\t\t\t    IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA,\n+\t\t\t\t\t    &pcaps);\n+\t\tif (rc)\n+\t\t\treturn rc;\n+\t}\n+\n+\t/* Determine supported speeds */\n+\thw->phy.speeds_supported = IXGBE_LINK_SPEED_UNKNOWN;\n+\n+\tif (pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_10BASE_T ||\n+\t    pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_10M_SGMII)\n+\t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_10_FULL;\n+\tif (pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_100BASE_TX ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_100M_SGMII ||\n+\t    pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_100M_USXGMII)\n+\t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;\n+\tif (pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_1000BASE_T  ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_1000BASE_SX ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_1000BASE_LX ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_1000BASE_KX ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_1G_SGMII    ||\n+\t    pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_1G_USXGMII)\n+\t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;\n+\tif (pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_2500BASE_T   ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_2500BASE_X   ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_2500BASE_KX  ||\n+\t    pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_SGMII ||\n+\t    pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_2500M_USXGMII)\n+\t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;\n+\tif (pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_5GBASE_T  ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_5GBASE_KR ||\n+\t    pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_5G_USXGMII)\n+\t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;\n+\tif (pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_10GBASE_T       ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_10G_SFI_DA      ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_10GBASE_SR      ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_10GBASE_LR      ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1  ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC ||\n+\t    pcaps.phy_type_low  & IXGBE_PHY_TYPE_LOW_10G_SFI_C2C     ||\n+\t    pcaps.phy_type_high & IXGBE_PHY_TYPE_HIGH_10G_USXGMII)\n+\t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;\n+\n+\t/* Initialize autoneg speeds */\n+\tif (!hw->phy.autoneg_advertised)\n+\t\thw->phy.autoneg_advertised = hw->phy.speeds_supported;\n+\n+\t/* Set PHY ID */\n+\tmemcpy(&hw->phy.id, pcaps.phy_id_oui, sizeof(u32));\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_identify_module_E610 - Identify SFP module type\n+ * @hw: pointer to hardware structure\n+ *\n+ * Identify the SFP module type.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_identify_module_E610(struct ixgbe_hw *hw)\n+{\n+\tbool media_available;\n+\tu8 module_type;\n+\ts32 rc;\n+\n+\trc = ixgbe_update_link_info(hw);\n+\tif (rc)\n+\t\tgoto err;\n+\n+\tmedia_available =\n+\t\t(hw->link.link_info.link_info &\n+\t\t IXGBE_ACI_MEDIA_AVAILABLE) ? true : false;\n+\n+\tif (media_available) {\n+\t\thw->phy.sfp_type = ixgbe_sfp_type_unknown;\n+\n+\t\t/* Get module type from hw context updated by ixgbe_update_link_info() */\n+\t\tmodule_type = hw->link.link_info.module_type[IXGBE_ACI_MOD_TYPE_IDENT];\n+\n+\t\tif ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE) ||\n+\t\t    (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE)) {\n+\t\t\thw->phy.sfp_type = ixgbe_sfp_type_da_cu;\n+\t\t} else if (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR) {\n+\t\t\thw->phy.sfp_type = ixgbe_sfp_type_sr;\n+\t\t} else if ((module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR) ||\n+\t\t\t   (module_type & IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM)) {\n+\t\t\thw->phy.sfp_type = ixgbe_sfp_type_lr;\n+\t\t}\n+\t\trc = IXGBE_SUCCESS;\n+\t} else {\n+\t\thw->phy.sfp_type = ixgbe_sfp_type_not_present;\n+\t\trc = IXGBE_ERR_SFP_NOT_PRESENT;\n+\t}\n+err:\n+\treturn rc;\n+}\n+\n+/**\n+ * ixgbe_setup_phy_link_E610 - Sets up firmware-controlled PHYs\n+ * @hw: pointer to hardware structure\n+ *\n+ * Set the parameters for the firmware-controlled PHYs.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_setup_phy_link_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data pcaps;\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data pcfg;\n+\tu8 rmode = IXGBE_ACI_REPORT_ACTIVE_CFG;\n+\ts32 rc;\n+\n+\trc = ixgbe_aci_get_link_info(hw, false, NULL);\n+\tif (rc) {\n+\t\tgoto err;\n+\t}\n+\n+\t/* If media is not available get default config */\n+\tif (!(hw->link.link_info.link_info & IXGBE_ACI_MEDIA_AVAILABLE))\n+\t\trmode = IXGBE_ACI_REPORT_DFLT_CFG;\n+\n+\trc = ixgbe_aci_get_phy_caps(hw, false, rmode, &pcaps);\n+\tif (rc) {\n+\t\tgoto err;\n+\t}\n+\n+\tixgbe_copy_phy_caps_to_cfg(&pcaps, &pcfg);\n+\n+\t/* Set default PHY types for a given speed */\n+\tpcfg.phy_type_low = 0;\n+\tpcfg.phy_type_high = 0;\n+\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10_FULL) {\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_10BASE_T;\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_10M_SGMII;\n+\t}\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) {\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_100BASE_TX;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_100M_SGMII;\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_100M_USXGMII;\n+\t}\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) {\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_1000BASE_T;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_1000BASE_SX;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_1000BASE_LX;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_1000BASE_KX;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_1G_SGMII;\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_1G_USXGMII;\n+\t}\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_2_5GB_FULL) {\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_2500BASE_T;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_2500BASE_X;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_2500BASE_KX;\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_SGMII;\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_2500M_USXGMII;\n+\t}\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) {\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_5GBASE_T;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_5GBASE_KR;\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_5G_USXGMII;\n+\t}\n+\tif (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) {\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_10GBASE_T;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_10G_SFI_DA;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_10GBASE_SR;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_10GBASE_LR;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC;\n+\t\tpcfg.phy_type_low  |= IXGBE_PHY_TYPE_LOW_10G_SFI_C2C;\n+\t\tpcfg.phy_type_high |= IXGBE_PHY_TYPE_HIGH_10G_USXGMII;\n+\t}\n+\n+\t/* Mask the set values to avoid requesting unsupported link types */\n+\tpcfg.phy_type_low &= pcaps.phy_type_low;\n+\tpcfg.phy_type_high &= pcaps.phy_type_high;\n+\n+\tif (pcfg.phy_type_high != pcaps.phy_type_high ||\n+\t    pcfg.phy_type_low != pcaps.phy_type_low ||\n+\t    pcfg.caps != pcaps.caps) {\n+\t\tpcfg.caps |= IXGBE_ACI_PHY_ENA_LINK;\n+\t\tpcfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\t\trc = ixgbe_aci_set_phy_cfg(hw, &pcfg);\n+\t}\n+\n+err:\n+\treturn rc;\n+}\n+\n+/**\n+ * ixgbe_get_phy_firmware_version_E610 - Gets the PHY Firmware Version\n+ * @hw: pointer to hardware structure\n+ * @firmware_version: pointer to the PHY Firmware Version\n+ * \n+ * Determines PHY FW version based on response to Get PHY Capabilities\n+ * admin command (0x0600).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_phy_firmware_version_E610(struct ixgbe_hw *hw,\n+\t\t\t\t\tu16 *firmware_version)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data pcaps;\n+\ts32 status;\n+\n+\tif (!firmware_version)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\t\t\t\tIXGBE_ACI_REPORT_ACTIVE_CFG,\n+\t\t\t\t\t&pcaps);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* TODO: determine which bytes of the 8-byte phy_fw_ver\n+\t * field should be written to the 2-byte firmware_version\n+\t * output argument. */\n+\tmemcpy(firmware_version, pcaps.phy_fw_ver, sizeof(u16));\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_i2c_sff8472_E610 - Reads 8 bit word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: byte offset at address 0xA2\n+ * @sff8472_data: value read\n+ *\n+ * Performs byte read operation from SFP module's SFF-8472 data over I2C.\n+ *\n+ * Return: the exit code of the operation.\n+ **/\n+s32 ixgbe_read_i2c_sff8472_E610(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\tu8 *sff8472_data)\n+{\n+\treturn ixgbe_aci_sff_eeprom(hw, 0, IXGBE_I2C_EEPROM_DEV_ADDR2,\n+\t\t\t\t    byte_offset, 0,\n+\t\t\t\t    IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE,\n+\t\t\t\t    sff8472_data, 1, false);\n+}\n+\n+/**\n+ * ixgbe_read_i2c_eeprom_E610 - Reads 8 bit EEPROM word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: EEPROM byte offset to read\n+ * @eeprom_data: value read\n+ *\n+ * Performs byte read operation from SFP module's EEPROM over I2C interface.\n+ *\n+ * Return: the exit code of the operation.\n+ **/\n+s32 ixgbe_read_i2c_eeprom_E610(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t       u8 *eeprom_data)\n+{\n+\treturn ixgbe_aci_sff_eeprom(hw, 0, IXGBE_I2C_EEPROM_DEV_ADDR,\n+\t\t\t\t    byte_offset, 0,\n+\t\t\t\t    IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE,\n+\t\t\t\t    eeprom_data, 1, false);\n+}\n+\n+/**\n+ * ixgbe_write_i2c_eeprom_E610 - Writes 8 bit EEPROM word over I2C interface\n+ * @hw: pointer to hardware structure\n+ * @byte_offset: EEPROM byte offset to write\n+ * @eeprom_data: value to write\n+ *\n+ * Performs byte write operation to SFP module's EEPROM over I2C interface.\n+ *\n+ * Return: the exit code of the operation.\n+ **/\n+s32 ixgbe_write_i2c_eeprom_E610(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\tu8 eeprom_data)\n+{\n+\treturn ixgbe_aci_sff_eeprom(hw, 0, IXGBE_I2C_EEPROM_DEV_ADDR,\n+\t\t\t\t    byte_offset, 0,\n+\t\t\t\t    IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE,\n+\t\t\t\t    &eeprom_data, 1, true);\n+}\n+\n+/**\n+ * ixgbe_check_overtemp_E610 - Check firmware-controlled PHYs for overtemp\n+ * @hw: pointer to hardware structure\n+ *\n+ * Get the link status and check if the PHY temperature alarm detected.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_check_overtemp_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_link_status_data link_data = { 0 };\n+\tstruct ixgbe_aci_cmd_get_link_status *resp;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status = IXGBE_SUCCESS;\n+\n+\tif (!hw)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_status);\n+\tresp = &desc.params.get_link_status;\n+\tresp->cmd_flags = IXGBE_CPU_TO_LE16(IXGBE_ACI_LSE_NOP);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, &link_data, sizeof(link_data));\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\tif (link_data.ext_info & IXGBE_ACI_LINK_PHY_TEMP_ALARM) {\n+\t\tERROR_REPORT1(IXGBE_ERROR_CAUTION,\n+\t\t\t      \"PHY Temperature Alarm detected\");\n+\t\tstatus = IXGBE_ERR_OVERTEMP;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_set_phy_power_E610 - Control power for copper PHY\n+ * @hw: pointer to hardware structure\n+ * @on: true for on, false for off\n+ *\n+ * Set the power on/off of the PHY\n+ * by getting its capabilities and setting the appropriate\n+ * configuration parameters.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_set_phy_power_E610(struct ixgbe_hw *hw, bool on)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data phy_caps = { 0 };\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = { 0 };\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\tIXGBE_ACI_REPORT_ACTIVE_CFG, &phy_caps);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\tixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg);\n+\n+\tif (on) {\n+\t\tphy_cfg.caps &= ~IXGBE_ACI_PHY_ENA_LOW_POWER;\n+\t} else {\n+\t\tphy_cfg.caps |= IXGBE_ACI_PHY_ENA_LOW_POWER;\n+\t}\n+\n+\t/* PHY is already in requested power mode */\n+\tif (phy_caps.caps == phy_cfg.caps)\n+\t\treturn IXGBE_SUCCESS;\n+\n+\tphy_cfg.caps |= IXGBE_ACI_PHY_ENA_LINK;\n+\tphy_cfg.caps |= IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\tstatus = ixgbe_aci_set_phy_cfg(hw, &phy_cfg);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_enter_lplu_E610 - Transition to low power states\n+ * @hw: pointer to hardware structure\n+ *\n+ * Configures Low Power Link Up on transition to low power states\n+ * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the\n+ * X557 PHY immediately prior to entering LPLU.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_enter_lplu_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps_data phy_caps = { 0 };\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data phy_cfg = { 0 };\n+\ts32 status;\n+\n+\tstatus = ixgbe_aci_get_phy_caps(hw, false,\n+\t\tIXGBE_ACI_REPORT_ACTIVE_CFG, &phy_caps);\n+\tif (status != IXGBE_SUCCESS)\n+\t\treturn status;\n+\n+\tixgbe_copy_phy_caps_to_cfg(&phy_caps, &phy_cfg);\n+\n+\tphy_cfg.low_power_ctrl_an |= IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG;\n+\n+\tstatus = ixgbe_aci_set_phy_cfg(hw, &phy_cfg);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_init_eeprom_params_E610 - Initialize EEPROM params\n+ * @hw: pointer to hardware structure\n+ *\n+ * Initializes the EEPROM parameters ixgbe_eeprom_info within the\n+ * ixgbe_hw struct in order to set up EEPROM access.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_init_eeprom_params_E610(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_eeprom_info *eeprom = &hw->eeprom;\n+\tu32 gens_stat;\n+\tu8 sr_size;\n+\n+\tif (eeprom->type == ixgbe_eeprom_uninitialized) {\n+\t\teeprom->type = ixgbe_flash;\n+\n+\t\tgens_stat = IXGBE_READ_REG(hw, GLNVM_GENS);\n+\t\tsr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >>\n+\t\t\t  GLNVM_GENS_SR_SIZE_S;\n+\n+\t\t/* Switching to words (sr_size contains power of 2) */\n+\t\teeprom->word_size = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB;\n+\n+\t\tDEBUGOUT2(\"Eeprom params: type = %d, size = %d\\n\",\n+\t\t\t  eeprom->type, eeprom->word_size);\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_ee_aci_E610 - Read EEPROM word using the admin command.\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of  word in the EEPROM to read\n+ * @data: word read from the EEPROM\n+ *\n+ * Reads a 16 bit word from the EEPROM using the ACI.\n+ * If the EEPROM params are not initialized, the function\n+ * initialize them before proceeding with reading.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 *data)\n+{\n+\ts32 status;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_sr_word_aci(hw, offset, data);\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_read_ee_aci_buffer_E610- Read EEPROM word(s) using admin commands.\n+ * @hw: pointer to hardware structure\n+ * @offset: offset of  word in the EEPROM to read\n+ * @words: number of words\n+ * @data: word(s) read from the EEPROM\n+ *\n+ * Reads a 16 bit word(s) from the EEPROM using the ACI.\n+ * If the EEPROM params are not initialized, the function\n+ * initialize them before proceeding with reading.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_ee_aci_buffer_E610(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t  u16 words, u16 *data)\n+{\n+\ts32 status;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_read_sr_buf_aci(hw, offset, &words, data);\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_calc_eeprom_checksum_E610 - Calculates and returns the checksum\n+ * @hw: pointer to hardware structure\n+ *\n+ * Calculate SW Checksum that covers the whole 64kB shadow RAM\n+ * except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD\n+ * is customer specific and unknown. Therefore, this function skips all maximum\n+ * possible size of VPD (1kB).\n+ * If the EEPROM params are not initialized, the function\n+ * initializes them before proceeding.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the negative error code on error, or the 16-bit checksum\n+ */\n+s32 ixgbe_calc_eeprom_checksum_E610(struct ixgbe_hw *hw)\n+{\n+\tbool nvm_acquired = false;\n+\tu16 pcie_alt_module = 0;\n+\tu16 checksum_local = 0;\n+\tu16 checksum = 0;\n+\tu16 vpd_module;\n+\tvoid *vmem;\n+\ts32 status;\n+\tu16 *data;\n+\tu16 i;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tvmem = ixgbe_calloc(hw, IXGBE_SR_SECTOR_SIZE_IN_WORDS, sizeof(u16));\n+\tif (!vmem)\n+\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\tdata = (u16 *)vmem;\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\tnvm_acquired = true;\n+\n+\t/* read pointer to VPD area */\n+\tstatus = ixgbe_read_sr_word_aci(hw, E610_SR_VPD_PTR, &vpd_module);\n+\tif (status)\n+\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\n+\t/* read pointer to PCIe Alt Auto-load module */\n+\tstatus = ixgbe_read_sr_word_aci(hw, E610_SR_PCIE_ALT_AUTO_LOAD_PTR,\n+\t\t\t\t\t&pcie_alt_module);\n+\tif (status)\n+\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\n+\t/* Calculate SW checksum that covers the whole 64kB shadow RAM\n+\t * except the VPD and PCIe ALT Auto-load modules\n+\t */\n+\tfor (i = 0; i < hw->eeprom.word_size; i++) {\n+\t\t/* Read SR page */\n+\t\tif ((i % IXGBE_SR_SECTOR_SIZE_IN_WORDS) == 0) {\n+\t\t\tu16 words = IXGBE_SR_SECTOR_SIZE_IN_WORDS;\n+\n+\t\t\tstatus = ixgbe_read_sr_buf_aci(hw, i, &words, data);\n+\t\t\tif (status != IXGBE_SUCCESS)\n+\t\t\t\tgoto ixgbe_calc_sr_checksum_exit;\n+\t\t}\n+\n+\t\t/* Skip Checksum word */\n+\t\tif (i == E610_SR_SW_CHECKSUM_WORD)\n+\t\t\tcontinue;\n+\t\t/* Skip VPD module (convert byte size to word count) */\n+\t\tif (i >= (u32)vpd_module &&\n+\t\t    i < ((u32)vpd_module + E610_SR_VPD_SIZE_WORDS))\n+\t\t\tcontinue;\n+\t\t/* Skip PCIe ALT module (convert byte size to word count) */\n+\t\tif (i >= (u32)pcie_alt_module &&\n+\t\t    i < ((u32)pcie_alt_module + E610_SR_PCIE_ALT_SIZE_WORDS))\n+\t\t\tcontinue;\n+\n+\t\tchecksum_local += data[i % IXGBE_SR_SECTOR_SIZE_IN_WORDS];\n+\t}\n+\n+\tchecksum = (u16)IXGBE_SR_SW_CHECKSUM_BASE - checksum_local;\n+\n+ixgbe_calc_sr_checksum_exit:\n+\tif(nvm_acquired)\n+\t\tixgbe_release_nvm(hw);\n+\tixgbe_free(hw, vmem);\n+\n+\tif(!status)\n+\t\treturn (s32)checksum;\n+\telse\n+\t\treturn status;\n+}\n+\n+/**\n+ * ixgbe_validate_eeprom_checksum_E610 - Validate EEPROM checksum\n+ * @hw: pointer to hardware structure\n+ * @checksum_val: calculated checksum\n+ *\n+ * Performs checksum calculation and validates the EEPROM checksum. If the\n+ * caller does not need checksum_val, the value can be NULL.\n+ * If the EEPROM params are not initialized, the function\n+ * initialize them before proceeding.\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_validate_eeprom_checksum_E610(struct ixgbe_hw *hw, u16 *checksum_val)\n+{\n+\tu32 status;\n+\n+\tif (hw->eeprom.type == ixgbe_eeprom_uninitialized) {\n+\t\tstatus = ixgbe_init_eeprom_params(hw);\n+\t\tif (status)\n+\t\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_nvm_validate_checksum(hw);\n+\n+\tif (status)\n+\t\treturn status;\n+\n+\tif (checksum_val) {\n+\t\tu16 tmp_checksum;\n+\t\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tstatus = ixgbe_read_sr_word_aci(hw, E610_SR_SW_CHECKSUM_WORD,\n+\t\t\t\t\t\t&tmp_checksum);\n+\t\tixgbe_release_nvm(hw);\n+\n+\t\tif (!status)\n+\t\t\t*checksum_val = tmp_checksum;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_get_pfa_module_tlv - Reads sub module TLV from NVM PFA\n+ * @hw: pointer to hardware structure\n+ * @module_tlv: pointer to module TLV to return\n+ * @module_tlv_len: pointer to module TLV length to return\n+ * @module_type: module type requested\n+ *\n+ * Finds the requested sub module TLV type from the Preserved Field\n+ * Area (PFA) and returns the TLV pointer and length. The caller can\n+ * use these to read the variable length TLV value.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+STATIC s32 ixgbe_get_pfa_module_tlv(struct ixgbe_hw *hw, u16 *module_tlv,\n+\t\t\t\t    u16 *module_tlv_len, u16 module_type)\n+{\n+\tu16 pfa_len, pfa_ptr, pfa_end_ptr;\n+\tu16 next_tlv;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, E610_SR_PFA_PTR, &pfa_ptr);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\tstatus = ixgbe_read_ee_aci_E610(hw, pfa_ptr, &pfa_len);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\t/* Starting with first TLV after PFA length, iterate through the list\n+\t * of TLVs to find the requested one.\n+\t */\n+\tnext_tlv = pfa_ptr + 1;\n+\tpfa_end_ptr = pfa_ptr + pfa_len;\n+\twhile (next_tlv < pfa_end_ptr) {\n+\t\tu16 tlv_sub_module_type, tlv_len;\n+\n+\t\t/* Read TLV type */\n+\t\tstatus = ixgbe_read_ee_aci_E610(hw, next_tlv,\n+\t\t\t\t\t\t&tlv_sub_module_type);\n+\t\tif (status != IXGBE_SUCCESS) {\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Read TLV length */\n+\t\tstatus = ixgbe_read_ee_aci_E610(hw, next_tlv + 1, &tlv_len);\n+\t\tif (status != IXGBE_SUCCESS) {\n+\t\t\tbreak;\n+\t\t}\n+\t\tif (tlv_sub_module_type == module_type) {\n+\t\t\tif (tlv_len) {\n+\t\t\t\t*module_tlv = next_tlv;\n+\t\t\t\t*module_tlv_len = tlv_len;\n+\t\t\t\treturn IXGBE_SUCCESS;\n+\t\t\t}\n+\t\t\treturn IXGBE_ERR_INVAL_SIZE;\n+\t\t}\n+\t\t/* Check next TLV, i.e. current TLV pointer + length + 2 words\n+\t\t * (for current TLV's type and length)\n+\t\t */\n+\t\tnext_tlv = next_tlv + tlv_len + 2;\n+\t}\n+\t/* Module does not exist */\n+\treturn IXGBE_ERR_DOES_NOT_EXIST;\n+}\n+\n+/**\n+ * ixgbe_read_pba_string_E610 - Reads part number string from NVM\n+ * @hw: pointer to hardware structure\n+ * @pba_num: stores the part number string from the NVM\n+ * @pba_num_size: part number string buffer length\n+ *\n+ * Reads the part number string from the NVM.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_read_pba_string_E610(struct ixgbe_hw *hw, u8 *pba_num,\n+\t\t\t       u32 pba_num_size)\n+{\n+\tu16 pba_tlv, pba_tlv_len;\n+\tu16 pba_word, pba_size;\n+\ts32 status;\n+\tu16 i;\n+\n+\tstatus = ixgbe_get_pfa_module_tlv(hw, &pba_tlv, &pba_tlv_len,\n+\t\t\t\t\tE610_SR_PBA_BLOCK_PTR);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\n+\t/* pba_size is the next word */\n+\tstatus = ixgbe_read_ee_aci_E610(hw, (pba_tlv + 2), &pba_size);\n+\tif (status != IXGBE_SUCCESS) {\n+\t\treturn status;\n+\t}\n+\n+\tif (pba_tlv_len < pba_size) {\n+\t\treturn IXGBE_ERR_INVAL_SIZE;\n+\t}\n+\n+\t/* Subtract one to get PBA word count (PBA Size word is included in\n+\t * total size)\n+\t */\n+\tpba_size--;\n+\tif (pba_num_size < (((u32)pba_size * 2) + 1)) {\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+\n+\tfor (i = 0; i < pba_size; i++) {\n+\t\tstatus = ixgbe_read_ee_aci_E610(hw, (pba_tlv + 2 + 1) + i,\n+\t\t\t\t\t\t&pba_word);\n+\t\tif (status != IXGBE_SUCCESS) {\n+\t\t\treturn status;\n+\t\t}\n+\n+\t\tpba_num[(i * 2)] = (pba_word >> 8) & 0xFF;\n+\t\tpba_num[(i * 2) + 1] = pba_word & 0xFF;\n+\t}\n+\tpba_num[(pba_size * 2)] = '\\0';\n+\n+\treturn status;\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.h b/drivers/net/ixgbe/base/ixgbe_e610.h\nnew file mode 100644\nindex 0000000000..f241955ada\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.h\n@@ -0,0 +1,163 @@\n+#ifndef _IXGBE_E610_H_\n+#define _IXGBE_E610_H_\n+\n+#include \"ixgbe_type.h\"\n+\n+void ixgbe_init_aci(struct ixgbe_hw *hw);\n+void ixgbe_shutdown_aci(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_aci_send_cmd(struct ixgbe_hw *hw, struct ixgbe_aci_desc *desc,\n+\t\t       void *buf, u16 buf_size);\n+bool ixgbe_aci_check_event_pending(struct ixgbe_hw *hw);\n+s32 ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,\n+\t\t\tbool *pending);\n+\n+void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode);\n+\n+s32 ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw);\n+s32 ixgbe_aci_send_driver_ver(struct ixgbe_hw *hw, struct ixgbe_driver_ver *dv);\n+s32 ixgbe_aci_set_pf_context(struct ixgbe_hw *hw, u8 pf_id);\n+\n+s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n+\t\t      enum ixgbe_aci_res_access_type access, u32 timeout);\n+void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res);\n+s32 ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size,\n+\t\t\tu32 *cap_count, enum ixgbe_aci_opc opc);\n+s32 ixgbe_discover_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t    struct ixgbe_hw_dev_caps *dev_caps);\n+s32 ixgbe_discover_func_caps(struct ixgbe_hw* hw,\n+\t\t\t     struct ixgbe_hw_func_caps* func_caps);\n+s32 ixgbe_get_caps(struct ixgbe_hw *hw);\n+s32 ixgbe_aci_disable_rxen(struct ixgbe_hw *hw);\n+s32 ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,\n+\t\t\t   struct ixgbe_aci_cmd_get_phy_caps_data *pcaps);\n+bool ixgbe_phy_caps_equals_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,\n+\t\t\t       struct ixgbe_aci_cmd_set_phy_cfg_data *cfg);\n+void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,\n+\t\t\t\tstruct ixgbe_aci_cmd_set_phy_cfg_data *cfg);\n+s32 ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw,\n+\t\t\t  struct ixgbe_aci_cmd_set_phy_cfg_data *cfg);\n+s32 ixgbe_aci_set_link_restart_an(struct ixgbe_hw *hw, bool ena_link);\n+s32 ixgbe_update_link_info(struct ixgbe_hw *hw);\n+s32 ixgbe_get_link_status(struct ixgbe_hw *hw, bool *link_up);\n+s32 ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,\n+\t\t\t    struct ixgbe_link_status *link);\n+s32 ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask);\n+s32 ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask);\n+\n+s32 ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,\n+\t\t\t       struct ixgbe_aci_cmd_get_link_topo *cmd,\n+\t\t\t       u8 *node_part_number, u16 *node_handle);\n+s32 ixgbe_aci_get_netlist_node_pin(struct ixgbe_hw *hw,\n+\t\t\t\t   struct ixgbe_aci_cmd_get_link_topo_pin *cmd,\n+\t\t\t\t   u16 *node_handle);\n+s32 ixgbe_find_netlist_node(struct ixgbe_hw *hw, u8 node_type_ctx,\n+\t\t\t    u8 node_part_number, u16 *node_handle);\n+s32 ixgbe_aci_read_i2c(struct ixgbe_hw *hw,\n+\t\t       struct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t       u16 bus_addr, __le16 addr, u8 params, u8 *data);\n+s32 ixgbe_aci_write_i2c(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t\tu16 bus_addr, __le16 addr, u8 params, u8 *data);\n+s32 ixgbe_aci_set_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t       bool value);\n+s32 ixgbe_aci_get_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t       bool *value);\n+s32 ixgbe_aci_sff_eeprom(struct ixgbe_hw *hw, u16 lport, u8 bus_addr,\n+\t\t\t u16 mem_addr, u8 page, u8 page_bank_ctrl, u8 *data,\n+\t\t\t u8 length, bool write);\n+s32 ixgbe_aci_prog_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params);\n+s32 ixgbe_aci_read_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params,\n+\t\t\tu32 start_address, u8 *data, u8 data_size);\n+\n+s32 ixgbe_acquire_nvm(struct ixgbe_hw *hw,\n+\t\t      enum ixgbe_aci_res_access_type access);\n+void ixgbe_release_nvm(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,\n+\t\t       u16 length, void *data, bool last_command,\n+\t\t       bool read_shadow_ram);\n+\n+s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw);\n+s32 ixgbe_nvm_recalculate_checksum(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_get_nvm_minsrevs(struct ixgbe_hw *hw, struct ixgbe_minsrev_info *minsrevs);\n+s32 ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n+s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n+s32 ixgbe_init_nvm(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_sanitize_operate(struct ixgbe_hw *hw);\n+s32 ixgbe_sanitize_nvm(struct ixgbe_hw *hw, u8 cmd_flags, u8 *values);\n+\n+s32 ixgbe_read_sr_word_aci(struct ixgbe_hw  *hw, u16 offset, u16 *data);\n+s32 ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words, u16 *data);\n+s32 ixgbe_read_flat_nvm(struct ixgbe_hw  *hw, u32 offset, u32 *length,\n+\t\t\tu8 *data, bool read_shadow_ram);\n+\n+s32 ixgbe_aci_alternate_write(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t      u32 reg_val0, u32 reg_addr1, u32 reg_val1);\n+s32 ixgbe_aci_alternate_read(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t     u32 *reg_val0, u32 reg_addr1, u32 *reg_val1);\n+s32 ixgbe_aci_alternate_write_done(struct ixgbe_hw *hw, u8 bios_mode,\n+\t\t\t\t   bool *reset_needed);\n+s32 ixgbe_aci_alternate_clear(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_aci_get_internal_data(struct ixgbe_hw *hw, u16 cluster_id,\n+\t\t\t\tu16 table_id, u32 start, void *buf,\n+\t\t\t\tu16 buf_size, u16 *ret_buf_size,\n+\t\t\t\tu16 *ret_next_cluster, u16 *ret_next_table,\n+\t\t\t\tu32 *ret_next_index);\n+\n+s32 ixgbe_handle_nvm_access(struct ixgbe_hw *hw,\n+\t\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\t\tstruct ixgbe_nvm_access_data *data);\n+\n+/* E610 operations */\n+s32 ixgbe_reset_hw_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_start_hw_E610(struct ixgbe_hw *hw);\n+enum ixgbe_media_type ixgbe_get_media_type_E610(struct ixgbe_hw *hw);\n+u64 ixgbe_get_supported_physical_layer_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed speed,\n+\t\t\t  bool autoneg_wait);\n+s32 ixgbe_check_link_E610(struct ixgbe_hw *hw, ixgbe_link_speed *speed,\n+\t\t\t  bool *link_up, bool link_up_wait_to_complete);\n+s32 ixgbe_get_link_capabilities_E610(struct ixgbe_hw *hw,\n+\t\t\t\t     ixgbe_link_speed *speed,\n+\t\t\t\t     bool *autoneg);\n+s32 ixgbe_cfg_phy_fc(struct ixgbe_hw *hw,\n+\t\t     struct ixgbe_aci_cmd_set_phy_cfg_data *cfg,\n+\t\t     enum ixgbe_fc_mode req_mode);\n+s32 ixgbe_setup_fc_E610(struct ixgbe_hw *hw);\n+void ixgbe_fc_autoneg_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_set_fw_drv_ver_E610(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build,\n+\t\t\t      u8 sub, u16 len, const char *driver_ver);\n+void ixgbe_disable_rx_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_eee_E610(struct ixgbe_hw *hw, bool enable_eee);\n+bool ixgbe_fw_recovery_mode_E610(struct ixgbe_hw *hw);\n+bool ixgbe_get_fw_tsam_mode_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_init_phy_ops_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_identify_phy_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_identify_module_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_setup_phy_link_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_get_phy_firmware_version_E610(struct ixgbe_hw *hw,\n+\t\t\t\t\tu16 *firmware_version);\n+s32 ixgbe_read_i2c_sff8472_E610(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\tu8 *sff8472_data);\n+s32 ixgbe_read_i2c_eeprom_E610(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t       u8 *eeprom_data);\n+s32 ixgbe_write_i2c_eeprom_E610(struct ixgbe_hw *hw, u8 byte_offset,\n+\t\t\t\tu8 eeprom_data);\n+s32 ixgbe_check_overtemp_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_set_phy_power_E610(struct ixgbe_hw *hw, bool on);\n+s32 ixgbe_enter_lplu_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_init_eeprom_params_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_read_ee_aci_E610(struct ixgbe_hw *hw, u16 offset, u16 *data);\n+s32 ixgbe_read_ee_aci_buffer_E610(struct ixgbe_hw *hw, u16 offset,\n+\t\t\t\t  u16 words, u16 *data);\n+s32 ixgbe_calc_eeprom_checksum_E610(struct ixgbe_hw *hw);\n+s32 ixgbe_validate_eeprom_checksum_E610(struct ixgbe_hw *hw, u16 *checksum_val);\n+s32 ixgbe_read_pba_string_E610(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size);\n+\n+#endif /* _IXGBE_E610_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_hv_vf.c b/drivers/net/ixgbe/base/ixgbe_hv_vf.c\nindex 1279659926..246dafcdf1 100644\n--- a/drivers/net/ixgbe/base/ixgbe_hv_vf.c\n+++ b/drivers/net/ixgbe/base/ixgbe_hv_vf.c\n@@ -136,7 +136,8 @@ static s32 ixgbevf_hv_check_mac_link_vf(struct ixgbe_hw *hw,\n \t\tbreak;\n \tcase IXGBE_LINKS_SPEED_100_82599:\n \t\t*speed = IXGBE_LINK_SPEED_100_FULL;\n-\t\tif (hw->mac.type == ixgbe_mac_X550) {\n+\t\tif (hw->mac.type == ixgbe_mac_X550 ||\n+\t\t    hw->mac.type == ixgbe_mac_E610) {\n \t\t\tif (links_reg & IXGBE_LINKS_SPEED_NON_STD)\n \t\t\t\t*speed = IXGBE_LINK_SPEED_5GB_FULL;\n \t\t}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_mbx.c b/drivers/net/ixgbe/base/ixgbe_mbx.c\nindex 2dab347396..9ad45fbfcc 100644\n--- a/drivers/net/ixgbe/base/ixgbe_mbx.c\n+++ b/drivers/net/ixgbe/base/ixgbe_mbx.c\n@@ -777,6 +777,7 @@ STATIC s32 ixgbe_check_for_rst_pf(struct ixgbe_hw *hw, u16 vf_id)\n \tcase ixgbe_mac_X550EM_x:\n \tcase ixgbe_mac_X550EM_a:\n \tcase ixgbe_mac_X540:\n+\tcase ixgbe_mac_E610:\n \t\tvflre = IXGBE_READ_REG(hw, IXGBE_PFVFLREC(index));\n \t\tbreak;\n \tdefault:\n@@ -1061,6 +1062,7 @@ void ixgbe_init_mbx_params_pf(struct ixgbe_hw *hw)\n \t    hw->mac.type != ixgbe_mac_X550 &&\n \t    hw->mac.type != ixgbe_mac_X550EM_x &&\n \t    hw->mac.type != ixgbe_mac_X550EM_a &&\n+\t    hw->mac.type != ixgbe_mac_E610 &&\n \t    hw->mac.type != ixgbe_mac_X540)\n \t\treturn;\n \n@@ -1103,6 +1105,7 @@ void ixgbe_upgrade_mbx_params_pf(struct ixgbe_hw *hw, u16 vf_id)\n \t    hw->mac.type != ixgbe_mac_X550 &&\n \t    hw->mac.type != ixgbe_mac_X550EM_x &&\n \t    hw->mac.type != ixgbe_mac_X550EM_a &&\n+\t    hw->mac.type != ixgbe_mac_E610 &&\n \t    hw->mac.type != ixgbe_mac_X540)\n \t\treturn;\n \ndiff --git a/drivers/net/ixgbe/base/ixgbe_osdep.c b/drivers/net/ixgbe/base/ixgbe_osdep.c\nnew file mode 100644\nindex 0000000000..fe4db60a8d\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_osdep.c\n@@ -0,0 +1,43 @@\n+#include <stdlib.h>\n+\n+#include <rte_common.h>\n+\n+#include \"ixgbe_osdep.h\"\n+\n+void *\n+ixgbe_calloc(struct ixgbe_hw __rte_unused *hw, size_t count, size_t size)\n+{\n+\treturn malloc(count * size);\n+}\n+\n+void *\n+ixgbe_malloc(struct ixgbe_hw __rte_unused *hw, size_t size)\n+{\n+\treturn malloc(size);\n+}\n+\n+void\n+ixgbe_free(struct ixgbe_hw __rte_unused *hw, void *addr)\n+{\n+\tfree(addr);\n+}\n+\n+void ixgbe_init_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_init(&lock->mutex, NULL);\n+}\n+\n+void ixgbe_destroy_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_destroy(&lock->mutex);\n+}\n+\n+void ixgbe_acquire_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_lock(&lock->mutex);\n+}\n+\n+void ixgbe_release_lock(struct ixgbe_lock *lock)\n+{\n+\tpthread_mutex_unlock(&lock->mutex);\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h\nindex 6c25f608b1..721043fb2e 100644\n--- a/drivers/net/ixgbe/base/ixgbe_osdep.h\n+++ b/drivers/net/ixgbe/base/ixgbe_osdep.h\n@@ -5,6 +5,7 @@\n #ifndef _IXGBE_OS_H_\n #define _IXGBE_OS_H_\n \n+#include <pthread.h>\n #include <string.h>\n #include <stdint.h>\n #include <stdio.h>\n@@ -79,7 +80,9 @@ enum {\n #define IXGBE_NTOHS(_i)\trte_be_to_cpu_16(_i)\n #define IXGBE_CPU_TO_LE16(_i)  rte_cpu_to_le_16(_i)\n #define IXGBE_CPU_TO_LE32(_i)  rte_cpu_to_le_32(_i)\n+#define IXGBE_LE16_TO_CPU(_i)  rte_le_to_cpu_16(_i)\n #define IXGBE_LE32_TO_CPU(_i)  rte_le_to_cpu_32(_i)\n+#define IXGBE_LE64_TO_CPU(_i)  rte_le_to_cpu_64(_i)\n #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)\n #define IXGBE_CPU_TO_BE16(_i)  rte_cpu_to_be_16(_i)\n #define IXGBE_CPU_TO_BE32(_i)  rte_cpu_to_be_32(_i)\n@@ -152,4 +155,18 @@ do {\t\t\t\t\t\t\t\t\t\\\n \t\trte_delay_ms(1);\t\t\t\t\t\\\n } while (0)\n \n+struct ixgbe_hw;\n+struct ixgbe_lock {\n+\tpthread_mutex_t mutex;\n+};\n+\n+void *ixgbe_calloc(struct ixgbe_hw *hw, size_t count, size_t size);\n+void *ixgbe_malloc(struct ixgbe_hw *hw, size_t size);\n+void ixgbe_free(struct ixgbe_hw *hw, void *addr);\n+\n+void ixgbe_init_lock(struct ixgbe_lock *lock);\n+void ixgbe_destroy_lock(struct ixgbe_lock *lock);\n+void ixgbe_acquire_lock(struct ixgbe_lock *lock);\n+void ixgbe_release_lock(struct ixgbe_lock *lock);\n+\n #endif /* _IXGBE_OS_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_phy.c b/drivers/net/ixgbe/base/ixgbe_phy.c\nindex 8a7712c8f2..47dab74b3c 100644\n--- a/drivers/net/ixgbe/base/ixgbe_phy.c\n+++ b/drivers/net/ixgbe/base/ixgbe_phy.c\n@@ -800,7 +800,8 @@ s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)\n \t\t\t     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,\n \t\t\t     &autoneg_reg);\n \n-\tif (hw->mac.type == ixgbe_mac_X550) {\n+\tif ((hw->mac.type == ixgbe_mac_X550) ||\n+\t    (hw->mac.type == ixgbe_mac_E610)) {\n \t\t/* Set or unset auto-negotiation 5G advertisement */\n \t\tautoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;\n \t\tif ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&\n@@ -915,6 +916,7 @@ static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)\n \n \tswitch (hw->mac.type) {\n \tcase ixgbe_mac_X550:\n+\tcase ixgbe_mac_E610:\n \t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;\n \t\thw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;\n \t\tbreak;\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex 5db9e03b4d..1070c281a2 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -44,6 +44,7 @@\n  */\n \n #include \"ixgbe_osdep.h\"\n+#include \"ixgbe_type_e610.h\"\n \n /* Override this by setting IOMEM in your ixgbe_osdep.h header */\n \n@@ -124,6 +125,11 @@\n #define IXGBE_DEV_ID_X550EM_A_VF_HV\t\t0x15B4\n #define IXGBE_DEV_ID_X550EM_X_VF\t\t0x15A8\n #define IXGBE_DEV_ID_X550EM_X_VF_HV\t\t0x15A9\n+#define IXGBE_DEV_ID_E610_BACKPLANE\t\t0x57AE\n+#define IXGBE_DEV_ID_E610_SFP\t\t\t0x57AF\n+#define IXGBE_DEV_ID_E610_10G_T\t\t\t0x57B0\n+#define IXGBE_DEV_ID_E610_2_5G_T\t\t0x57B1\n+#define IXGBE_DEV_ID_E610_SGMII\t\t\t0x57B2\n \n #define IXGBE_CAT(r, m) IXGBE_##r##m\n \n@@ -1887,6 +1893,7 @@ enum {\n #define IXGBE_EICR_MAILBOX\t0x00080000 /* VF to PF Mailbox Interrupt */\n #define IXGBE_EICR_LSC\t\t0x00100000 /* Link Status Change */\n #define IXGBE_EICR_LINKSEC\t0x00200000 /* PN Threshold */\n+#define IXGBE_EICR_FW_EVENT\t0x00200000 /* Async FW event */\n #define IXGBE_EICR_MNG\t\t0x00400000 /* Manageability Event Interrupt */\n #define IXGBE_EICR_TS\t\t0x00800000 /* Thermal Sensor Event */\n #define IXGBE_EICR_TIMESYNC\t0x01000000 /* Timesync Event */\n@@ -1922,6 +1929,7 @@ enum {\n #define IXGBE_EICS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n #define IXGBE_EICS_MAILBOX\tIXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */\n #define IXGBE_EICS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n+#define IXGBE_EICS_FW_EVENT\tIXGBE_EICR_FW_EVENT /* Async FW event */\n #define IXGBE_EICS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n #define IXGBE_EICS_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n #define IXGBE_EICS_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n@@ -1943,6 +1951,7 @@ enum {\n #define IXGBE_EIMS_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n #define IXGBE_EIMS_MAILBOX\tIXGBE_EICR_MAILBOX   /* VF to PF Mailbox Int */\n #define IXGBE_EIMS_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n+#define IXGBE_EIMS_FW_EVENT\tIXGBE_EICR_FW_EVENT /* Async FW event */\n #define IXGBE_EIMS_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n #define IXGBE_EIMS_TS\t\tIXGBE_EICR_TS /* Thermal Sensor Event */\n #define IXGBE_EIMS_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n@@ -1965,6 +1974,7 @@ enum {\n #define IXGBE_EIMC_PCI\t\tIXGBE_EICR_PCI /* PCI Exception */\n #define IXGBE_EIMC_MAILBOX\tIXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */\n #define IXGBE_EIMC_LSC\t\tIXGBE_EICR_LSC /* Link Status Change */\n+#define IXGBE_EIMC_FW_EVENT\tIXGBE_EICR_FW_EVENT /* Async FW event */\n #define IXGBE_EIMC_MNG\t\tIXGBE_EICR_MNG /* MNG Event Interrupt */\n #define IXGBE_EIMC_TIMESYNC\tIXGBE_EICR_TIMESYNC /* Timesync Event */\n #define IXGBE_EIMC_GPI_SDP0\tIXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */\n@@ -2372,6 +2382,7 @@ enum {\n #define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR\t0x11\n #define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR\t0x04\n \n+#define IXGBE_PCIE_MSIX_LKV_CAPS\t\t0xB2\n #define IXGBE_PCIE_MSIX_82599_CAPS\t0x72\n #define IXGBE_MAX_MSIX_VECTORS_82599\t0x40\n #define IXGBE_PCIE_MSIX_82598_CAPS\t0x62\n@@ -2489,6 +2500,7 @@ enum {\n #define IXGBE_PCI_DEVICE_STATUS\t\t0xAA\n #define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING\t0x0020\n #define IXGBE_PCI_LINK_STATUS\t\t0xB2\n+#define IXGBE_PCI_LINK_STATUS_E610\t0x82\n #define IXGBE_PCI_DEVICE_CONTROL2\t0xC8\n #define IXGBE_PCI_LINK_WIDTH\t\t0x3F0\n #define IXGBE_PCI_LINK_WIDTH_1\t\t0x10\n@@ -2499,6 +2511,7 @@ enum {\n #define IXGBE_PCI_LINK_SPEED_2500\t0x1\n #define IXGBE_PCI_LINK_SPEED_5000\t0x2\n #define IXGBE_PCI_LINK_SPEED_8000\t0x3\n+#define IXGBE_PCI_LINK_SPEED_16000\t0x4\n #define IXGBE_PCI_HEADER_TYPE_REGISTER\t0x0E\n #define IXGBE_PCI_HEADER_TYPE_MULTIFUNC\t0x80\n #define IXGBE_PCI_DEVICE_CONTROL2_16ms\t0x0005\n@@ -2626,6 +2639,7 @@ enum {\n #define IXGBE_RXMTRL_V2_MGMT_MSG\t0x0D00\n \n #define IXGBE_FCTRL_SBP\t\t0x00000002 /* Store Bad Packet */\n+#define IXGBE_FCTRL_TPE\t\t0x00000080 /* Tag Promiscuous Ena*/\n #define IXGBE_FCTRL_MPE\t\t0x00000100 /* Multicast Promiscuous Ena*/\n #define IXGBE_FCTRL_UPE\t\t0x00000200 /* Unicast Promiscuous Ena */\n #define IXGBE_FCTRL_BAM\t\t0x00000400 /* Broadcast Accept Mode */\n@@ -2693,6 +2707,7 @@ enum {\n /* Multiple Transmit Queue Command Register */\n #define IXGBE_MTQC_RT_ENA\t0x1 /* DCB Enable */\n #define IXGBE_MTQC_VT_ENA\t0x2 /* VMDQ2 Enable */\n+#define IXGBE_MTQC_NUM_TC_OR_Q  0xC /* Numer of TCs or TxQs per pool */\n #define IXGBE_MTQC_64Q_1PB\t0x0 /* 64 queues 1 pack buffer */\n #define IXGBE_MTQC_32VF\t\t0x8 /* 4 TX Queues per pool w/32VF's */\n #define IXGBE_MTQC_64VF\t\t0x4 /* 2 TX Queues per pool w/64VF's */\n@@ -3660,6 +3675,7 @@ enum ixgbe_mac_type {\n \tixgbe_mac_X550_vf,\n \tixgbe_mac_X550EM_x_vf,\n \tixgbe_mac_X550EM_a_vf,\n+\tixgbe_mac_E610,\n \tixgbe_num_macs\n };\n \n@@ -3738,7 +3754,9 @@ enum ixgbe_media_type {\n \tixgbe_media_type_copper,\n \tixgbe_media_type_backplane,\n \tixgbe_media_type_cx4,\n-\tixgbe_media_type_virtual\n+\tixgbe_media_type_virtual,\n+\tixgbe_media_type_da,\n+\tixgbe_media_type_aui\n };\n \n /* Flow Control Settings */\n@@ -3747,6 +3765,8 @@ enum ixgbe_fc_mode {\n \tixgbe_fc_rx_pause,\n \tixgbe_fc_tx_pause,\n \tixgbe_fc_full,\n+\tixgbe_fc_auto,\n+\tixgbe_fc_pfc,\n \tixgbe_fc_default\n };\n \n@@ -3779,6 +3799,7 @@ enum ixgbe_bus_speed {\n \tixgbe_bus_speed_2500\t= 2500,\n \tixgbe_bus_speed_5000\t= 5000,\n \tixgbe_bus_speed_8000\t= 8000,\n+\tixgbe_bus_speed_16000   = 16000,\n \tixgbe_bus_speed_reserved\n };\n \n@@ -3923,6 +3944,7 @@ struct ixgbe_eeprom_operations {\n \ts32 (*validate_checksum)(struct ixgbe_hw *, u16 *);\n \ts32 (*update_checksum)(struct ixgbe_hw *);\n \ts32 (*calc_checksum)(struct ixgbe_hw *);\n+\ts32 (*read_pba_string)(struct ixgbe_hw *, u8 *, u32);\n };\n \n struct ixgbe_mac_operations {\n@@ -4029,6 +4051,9 @@ struct ixgbe_mac_operations {\n \tvoid (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap);\n \tvoid (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf);\n \tbool (*fw_recovery_mode)(struct ixgbe_hw *hw);\n+\tbool (*get_fw_tsam_mode)(struct ixgbe_hw *hw);\n+\ts32 (*get_fw_version)(struct ixgbe_hw *hw);\n+\ts32 (*get_nvm_version)(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n };\n \n struct ixgbe_phy_operations {\n@@ -4073,6 +4098,9 @@ struct ixgbe_link_operations {\n struct ixgbe_link_info {\n \tstruct ixgbe_link_operations ops;\n \tu8 addr;\n+\tstruct ixgbe_link_status link_info;\n+\tstruct ixgbe_link_status link_info_old;\n+\tu8 get_link_info;\n };\n \n struct ixgbe_eeprom_info {\n@@ -4144,6 +4172,9 @@ struct ixgbe_phy_info {\n \tbool reset_if_overtemp;\n \tbool qsfp_shared_i2c_bus;\n \tu32 nw_mng_if_sel;\n+\tu64 phy_type_low;\n+\tu64 phy_type_high;\n+\tstruct ixgbe_aci_cmd_set_phy_cfg_data curr_user_phy_cfg;\n };\n \n #include \"ixgbe_mbx.h\"\n@@ -4165,6 +4196,8 @@ struct ixgbe_hw {\n \tu16 subsystem_device_id;\n \tu16 subsystem_vendor_id;\n \tu8 revision_id;\n+\tu8 pf_id;\n+\tu8 logical_pf_id;\n \tbool adapter_stopped;\n \tint api_version;\n \tbool force_full_reset;\n@@ -4172,6 +4205,19 @@ struct ixgbe_hw {\n \tbool wol_enabled;\n \tbool need_crosstalk_fix;\n \tu32 fw_rst_cnt;\n+\tu8 api_branch;\n+\tu8 api_maj_ver;\n+\tu8 api_min_ver;\n+\tu8 api_patch;\n+\tu8 fw_branch;\n+\tu8 fw_maj_ver;\n+\tu8 fw_min_ver;\n+\tu8 fw_patch;\n+\tu32 fw_build;\n+\tstruct ixgbe_aci_info aci;\n+\tstruct ixgbe_flash_info flash;\n+\tstruct ixgbe_hw_dev_caps dev_caps;\n+\tstruct ixgbe_hw_func_caps func_caps;\n };\n \n #define ixgbe_call_func(hw, func, params, error) \\\n@@ -4221,6 +4267,23 @@ struct ixgbe_hw {\n #define IXGBE_ERR_MBX\t\t\t\t-41\n #define IXGBE_ERR_MBX_NOMSG\t\t\t-42\n #define IXGBE_ERR_TIMEOUT\t\t\t-43\n+#define IXGBE_ERR_NOT_SUPPORTED\t\t\t-45\n+#define IXGBE_ERR_OUT_OF_RANGE\t\t\t-46\n+\n+#define IXGBE_ERR_NVM\t\t\t\t-50\n+#define IXGBE_ERR_NVM_CHECKSUM\t\t\t-51\n+#define IXGBE_ERR_BUF_TOO_SHORT\t\t\t-52\n+#define IXGBE_ERR_NVM_BLANK_MODE\t\t-53\n+#define IXGBE_ERR_INVAL_SIZE\t\t\t-54\n+#define IXGBE_ERR_DOES_NOT_EXIST\t\t-55\n+\n+#define IXGBE_ERR_ACI_ERROR\t\t\t-100\n+#define IXGBE_ERR_ACI_DISABLED\t\t\t-101\n+#define IXGBE_ERR_ACI_TIMEOUT\t\t\t-102\n+#define IXGBE_ERR_ACI_BUSY\t\t\t-103\n+#define IXGBE_ERR_ACI_NO_WORK\t\t\t-104\n+#define IXGBE_ERR_ACI_NO_EVENTS\t\t\t-105\n+#define IXGBE_ERR_FW_API_VER\t\t\t-106\n \n #define IXGBE_NOT_IMPLEMENTED\t\t\t0x7FFFFFFF\n \ndiff --git a/drivers/net/ixgbe/base/ixgbe_type_e610.h b/drivers/net/ixgbe/base/ixgbe_type_e610.h\nnew file mode 100644\nindex 0000000000..0b734d5af7\n--- /dev/null\n+++ b/drivers/net/ixgbe/base/ixgbe_type_e610.h\n@@ -0,0 +1,2181 @@\n+#ifndef _IXGBE_TYPE_E610_H_\n+#define _IXGBE_TYPE_E610_H_\n+\n+/* Little Endian defines */\n+#ifndef __le16\n+#define __le16  u16\n+#endif\n+#ifndef __le32\n+#define __le32  u32\n+#endif\n+#ifndef __le64\n+#define __le64  u64\n+#endif\n+\n+/* Generic defines */\n+#ifndef BIT\n+#define BIT(a) (1UL << (a))\n+#endif /* !BIT */\n+#ifndef BIT_ULL\n+#define BIT_ULL(a) (1ULL << (a))\n+#endif /* !BIT_ULL */\n+#ifndef BITS_PER_BYTE\n+#define BITS_PER_BYTE\t8\n+#endif /* !BITS_PER_BYTE */\n+#ifndef DIVIDE_AND_ROUND_UP\n+#define DIVIDE_AND_ROUND_UP(a, b) (((a) + (b) - 1) / (b))\n+#endif /* !DIVIDE_AND_ROUND_UP */\n+\n+#ifndef ROUND_UP\n+/**\n+ * ROUND_UP - round up to next arbitrary multiple (not a power of 2)\n+ * @a: value to round up\n+ * @b: arbitrary multiple\n+ *\n+ * Round up to the next multiple of the arbitrary b.\n+ */\n+#define ROUND_UP(a, b)\t((b) * DIVIDE_AND_ROUND_UP((a), (b)))\n+#endif /* !ROUND_UP */\n+\n+#define MAKEMASK(mask, shift) (mask << shift)\n+\n+#define BYTES_PER_WORD\t2\n+#define BYTES_PER_DWORD\t4\n+\n+#ifndef BITS_PER_LONG\n+#define BITS_PER_LONG\t\t64\n+#endif /* !BITS_PER_LONG */\n+#ifndef BITS_PER_LONG_LONG\n+#define BITS_PER_LONG_LONG\t64\n+#endif /* !BITS_PER_LONG_LONG */\n+#undef GENMASK\n+#define GENMASK(h, l) \\\n+\t(((~0UL) << (l)) & (~0UL >> (BITS_PER_LONG - 1 - (h))))\n+#undef GENMASK_ULL\n+#define GENMASK_ULL(h, l) \\\n+\t(((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h))))\n+\n+/* Data type manipulation macros. */\n+#define HI_DWORD(x)\t((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))\n+#define LO_DWORD(x)\t((u32)((x) & 0xFFFFFFFF))\n+#define HI_WORD(x)\t((u16)(((x) >> 16) & 0xFFFF))\n+#define LO_WORD(x)\t((u16)((x) & 0xFFFF))\n+#define HI_BYTE(x)\t((u8)(((x) >> 8) & 0xFF))\n+#define LO_BYTE(x)\t((u8)((x) & 0xFF))\n+\n+#define MIN_T(_t, _a, _b)\tmin((_t)(_a), (_t)(_b))\n+\n+#define IS_ASCII(_ch)\t((_ch) < 0x80)\n+\n+#define STRUCT_HACK_VAR_LEN\n+/**\n+ * ixgbe_struct_size - size of struct with C99 flexible array member\n+ * @ptr: pointer to structure\n+ * @field: flexible array member (last member of the structure)\n+ * @num: number of elements of that flexible array member\n+ */\n+#define ixgbe_struct_size(ptr, field, num) \\\n+\t(sizeof(*(ptr)) + sizeof(*(ptr)->field) * (num))\n+\n+/* General E610 defines */\n+#define IXGBE_MAX_VSI\t\t\t768\n+\n+/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n+#define E610_SR_VPD_SIZE_WORDS\t\t512\n+#define E610_SR_PCIE_ALT_SIZE_WORDS\t512\n+\n+/* Checksum and Shadow RAM pointers */\n+#define E610_SR_NVM_DEV_STARTER_VER\t\t0x18\n+#define E610_NVM_VER_LO_SHIFT\t\t\t0\n+#define E610_NVM_VER_LO_MASK\t\t\t(0xff << E610_NVM_VER_LO_SHIFT)\n+#define E610_NVM_VER_HI_SHIFT\t\t\t12\n+#define E610_NVM_VER_HI_MASK\t\t\t(0xf << E610_NVM_VER_HI_SHIFT)\n+#define E610_SR_NVM_MAP_VER\t\t\t0x29\n+#define E610_SR_NVM_EETRACK_LO\t\t\t0x2D\n+#define E610_SR_NVM_EETRACK_HI\t\t\t0x2E\n+#define E610_SR_VPD_PTR\t\t\t\t0x2F\n+#define E610_SR_PCIE_ALT_AUTO_LOAD_PTR\t\t0x3E\n+#define E610_SR_SW_CHECKSUM_WORD\t\t0x3F\n+#define E610_SR_PFA_PTR\t\t\t\t0x40\n+#define E610_SR_1ST_NVM_BANK_PTR\t\t0x42\n+#define E610_SR_NVM_BANK_SIZE\t\t\t0x43\n+#define E610_SR_1ST_OROM_BANK_PTR\t\t0x44\n+#define E610_SR_OROM_BANK_SIZE\t\t\t0x45\n+#define E610_SR_NETLIST_BANK_PTR\t\t0x46\n+#define E610_SR_NETLIST_BANK_SIZE\t\t0x47\n+#define E610_SR_POINTER_TYPE_BIT\t\tBIT(15)\n+#define E610_SR_POINTER_MASK\t\t\t0x7fff\n+#define E610_SR_HALF_4KB_SECTOR_UNITS\t\t2048\n+#define E610_GET_PFA_POINTER_IN_WORDS(offset)\t\t\t\t    \\\n+    ((offset & E610_SR_POINTER_TYPE_BIT) == E610_SR_POINTER_TYPE_BIT) ?     \\\n+        ((offset & E610_SR_POINTER_MASK) * E610_SR_HALF_4KB_SECTOR_UNITS) : \\\n+        (offset & E610_SR_POINTER_MASK)\n+\n+/* Checksum and Shadow RAM pointers */\n+#define E610_SR_NVM_CTRL_WORD\t\t0x00\n+#define E610_SR_PBA_BLOCK_PTR\t\t0x16\n+\n+/* The Orom version topology */\n+#define IXGBE_OROM_VER_PATCH_SHIFT\t0\n+#define IXGBE_OROM_VER_PATCH_MASK\t(0xff << IXGBE_OROM_VER_PATCH_SHIFT)\n+#define IXGBE_OROM_VER_BUILD_SHIFT\t8\n+#define IXGBE_OROM_VER_BUILD_MASK\t(0xffff << IXGBE_OROM_VER_BUILD_SHIFT)\n+#define IXGBE_OROM_VER_SHIFT\t\t24\n+#define IXGBE_OROM_VER_MASK\t\t(0xff << IXGBE_OROM_VER_SHIFT)\n+\n+/* CSS Header words */\n+#define IXGBE_NVM_CSS_HDR_LEN_L\t\t\t0x02\n+#define IXGBE_NVM_CSS_HDR_LEN_H\t\t\t0x03\n+#define IXGBE_NVM_CSS_SREV_L\t\t\t0x14\n+#define IXGBE_NVM_CSS_SREV_H\t\t\t0x15\n+\n+/* Length of Authentication header section in words */\n+#define IXGBE_NVM_AUTH_HEADER_LEN\t\t0x08\n+\n+/* The Netlist ID Block is located after all of the Link Topology nodes. */\n+#define IXGBE_NETLIST_ID_BLK_SIZE\t\t0x30\n+#define IXGBE_NETLIST_ID_BLK_OFFSET(n)\t\tIXGBE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))\n+\n+/* netlist ID block field offsets (word offsets) */\n+#define IXGBE_NETLIST_ID_BLK_MAJOR_VER_LOW\t0x02\n+#define IXGBE_NETLIST_ID_BLK_MAJOR_VER_HIGH\t0x03\n+#define IXGBE_NETLIST_ID_BLK_MINOR_VER_LOW\t0x04\n+#define IXGBE_NETLIST_ID_BLK_MINOR_VER_HIGH\t0x05\n+#define IXGBE_NETLIST_ID_BLK_TYPE_LOW\t\t0x06\n+#define IXGBE_NETLIST_ID_BLK_TYPE_HIGH\t\t0x07\n+#define IXGBE_NETLIST_ID_BLK_REV_LOW\t\t0x08\n+#define IXGBE_NETLIST_ID_BLK_REV_HIGH\t\t0x09\n+#define IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(n)\t(0x0A + (n))\n+#define IXGBE_NETLIST_ID_BLK_CUST_VER\t\t0x2F\n+\n+/* The Link Topology Netlist section is stored as a series of words. It is\n+ * stored in the NVM as a TLV, with the first two words containing the type\n+ * and length.\n+ */\n+#define IXGBE_NETLIST_LINK_TOPO_MOD_ID\t\t0x011B\n+#define IXGBE_NETLIST_TYPE_OFFSET\t\t0x0000\n+#define IXGBE_NETLIST_LEN_OFFSET\t\t0x0001\n+\n+/* The Link Topology section follows the TLV header. When reading the netlist\n+ * using ixgbe_read_netlist_module, we need to account for the 2-word TLV\n+ * header.\n+ */\n+#define IXGBE_NETLIST_LINK_TOPO_OFFSET(n)\t((n) + 2)\n+#define IXGBE_LINK_TOPO_MODULE_LEN\tIXGBE_NETLIST_LINK_TOPO_OFFSET(0x0000)\n+#define IXGBE_LINK_TOPO_NODE_COUNT\tIXGBE_NETLIST_LINK_TOPO_OFFSET(0x0001)\n+#define IXGBE_LINK_TOPO_NODE_COUNT_M\tMAKEMASK(0x3FF, 0)\n+\n+/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n+#define IXGBE_SR_CTRL_WORD_1_S\t\t0x06\n+#define IXGBE_SR_CTRL_WORD_1_M\t\t(0x03 << IXGBE_SR_CTRL_WORD_1_S)\n+#define IXGBE_SR_CTRL_WORD_VALID\t0x1\n+#define IXGBE_SR_CTRL_WORD_OROM_BANK\tBIT(3)\n+#define IXGBE_SR_CTRL_WORD_NETLIST_BANK\tBIT(4)\n+#define IXGBE_SR_CTRL_WORD_NVM_BANK\tBIT(5)\n+#define IXGBE_SR_NVM_PTR_4KB_UNITS\tBIT(15)\n+\n+/* These macros strip from NVM Image Revision the particular part of NVM ver:\n+   major ver, minor ver and image id */\n+#define E610_NVM_MAJOR_VER(x)\t((x & 0xF000) >> 12)\n+#define E610_NVM_MINOR_VER(x)\t(x & 0x00FF)\n+\n+/* Minimal Security Revision */\n+\n+/* Shadow RAM related */\n+#define IXGBE_SR_SECTOR_SIZE_IN_WORDS\t\t0x800\n+#define IXGBE_SR_WORDS_IN_1KB\t\t\t512\n+/* Checksum should be calculated such that after adding all the words,\n+ * including the checksum word itself, the sum should be 0xBABA.\n+ */\n+#define IXGBE_SR_SW_CHECKSUM_BASE\t\t0xBABA\n+\n+/* Netlist */\n+#define IXGBE_MAX_NETLIST_SIZE\t\t\t10\n+\n+/* General registers */\n+\n+/* Firmware Status Register (GL_FWSTS) */\n+#define GL_FWSTS\t\t\t\t0x00083048 /* Reset Source: POR */\n+#define GL_FWSTS_FWS0B_S\t\t\t0\n+#define GL_FWSTS_FWS0B_M\t\t\tMAKEMASK(0xFF, 0)\n+#define GL_FWSTS_FWROWD_S\t\t\t8\n+#define GL_FWSTS_FWROWD_M\t\t\tBIT(8)\n+#define GL_FWSTS_FWRI_S\t\t\t\t9\n+#define GL_FWSTS_FWRI_M\t\t\t\tBIT(9)\n+#define GL_FWSTS_FWS1B_S\t\t\t16\n+#define GL_FWSTS_FWS1B_M\t\t\tMAKEMASK(0xFF, 16)\n+#define GL_FWSTS_EP_PF0\t\t\t\tBIT(24)\n+#define GL_FWSTS_EP_PF1\t\t\t\tBIT(25)\n+\n+/* Recovery mode values of Firmware Status 1 Byte (FWS1B) bitfield */\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_CORER_LEGACY  0x0B\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_GLOBR_LEGACY  0x0C\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_CORER         0x30\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_GLOBR         0x31\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_TRANSITION    0x32\n+#define GL_FWSTS_FWS1B_RECOVERY_MODE_NVM           0x33\n+\n+/* Firmware Status (GL_MNG_FWSM) */\n+#define GL_MNG_FWSM\t\t\t\t0x000B6134 /* Reset Source: POR */\n+#define GL_MNG_FWSM_FW_MODES_S\t\t\t0\n+#define GL_MNG_FWSM_FW_MODES_M\t\t\tMAKEMASK(0x7, 0)\n+#define GL_MNG_FWSM_RSV0_S\t\t\t2\n+#define GL_MNG_FWSM_RSV0_M\t\t\tMAKEMASK(0xFF, 2)\n+#define GL_MNG_FWSM_EEP_RELOAD_IND_S\t\t10\n+#define GL_MNG_FWSM_EEP_RELOAD_IND_M\t\tBIT(10)\n+#define GL_MNG_FWSM_RSV1_S\t\t\t11\n+#define GL_MNG_FWSM_RSV1_M\t\t\tMAKEMASK(0xF, 11)\n+#define GL_MNG_FWSM_RSV2_S\t\t\t15\n+#define GL_MNG_FWSM_RSV2_M\t\t\tBIT(15)\n+#define GL_MNG_FWSM_PCIR_AL_FAILURE_S\t\t16\n+#define GL_MNG_FWSM_PCIR_AL_FAILURE_M\t\tBIT(16)\n+#define GL_MNG_FWSM_POR_AL_FAILURE_S\t\t17\n+#define GL_MNG_FWSM_POR_AL_FAILURE_M\t\tBIT(17)\n+#define GL_MNG_FWSM_RSV3_S\t\t\t18\n+#define GL_MNG_FWSM_RSV3_M\t\t\tBIT(18)\n+#define GL_MNG_FWSM_EXT_ERR_IND_S\t\t19\n+#define GL_MNG_FWSM_EXT_ERR_IND_M\t\tMAKEMASK(0x3F, 19)\n+#define GL_MNG_FWSM_RSV4_S\t\t\t25\n+#define GL_MNG_FWSM_RSV4_M\t\t\tBIT(25)\n+#define GL_MNG_FWSM_RESERVED_11_S\t\t26\n+#define GL_MNG_FWSM_RESERVED_11_M\t\tMAKEMASK(0xF, 26)\n+#define GL_MNG_FWSM_RSV5_S\t\t\t30\n+#define GL_MNG_FWSM_RSV5_M\t\t\tMAKEMASK(0x3, 30)\n+\n+/* FW mode indications */\n+#define GL_MNG_FWSM_FW_MODES_DEBUG_M           BIT(0)\n+#define GL_MNG_FWSM_FW_MODES_RECOVERY_M        BIT(1)\n+#define GL_MNG_FWSM_FW_MODES_ROLLBACK_M        BIT(2)\n+\n+/* PF - Manageability  Registers  */\n+\n+/* Global NVM General Status Register */\n+#define GLNVM_GENS\t\t\t\t0x000B6100 /* Reset Source: POR */\n+#define GLNVM_GENS_NVM_PRES_S\t\t\t0\n+#define GLNVM_GENS_NVM_PRES_M\t\t\tBIT(0)\n+#define GLNVM_GENS_SR_SIZE_S\t\t\t5\n+#define GLNVM_GENS_SR_SIZE_M\t\t\tMAKEMASK(0x7, 5)\n+#define GLNVM_GENS_BANK1VAL_S\t\t\t8\n+#define GLNVM_GENS_BANK1VAL_M\t\t\tBIT(8)\n+#define GLNVM_GENS_ALT_PRST_S\t\t\t23\n+#define GLNVM_GENS_ALT_PRST_M\t\t\tBIT(23)\n+#define GLNVM_GENS_FL_AUTO_RD_S\t\t\t25\n+#define GLNVM_GENS_FL_AUTO_RD_M\t\t\tBIT(25)\n+\n+/* Flash Access Register */\n+#define GLNVM_FLA\t\t\t\t0x000B6108 /* Reset Source: POR */\n+#define GLNVM_FLA_LOCKED_S\t\t\t6\n+#define GLNVM_FLA_LOCKED_M\t\t\tBIT(6)\n+\n+/* Bit Bang registers */\n+#define RDASB_MSGCTL\t\t\t\t0x000B6820\n+#define RDASB_MSGCTL_HDR_DWS_S\t\t\t0\n+#define RDASB_MSGCTL_EXP_RDW_S\t\t\t8\n+#define RDASB_MSGCTL_CMDV_M\t\t\tBIT(31)\n+#define RDASB_RSPCTL\t\t\t\t0x000B6824\n+#define RDASB_RSPCTL_BAD_LENGTH_M\t\tBIT(30)\n+#define RDASB_RSPCTL_NOT_SUCCESS_M\t\tBIT(31)\n+#define RDASB_WHDR0\t\t\t\t0x000B68F4\n+#define RDASB_WHDR1\t\t\t\t0x000B68F8\n+#define RDASB_WHDR2\t\t\t\t0x000B68FC\n+#define RDASB_WHDR3\t\t\t\t0x000B6900\n+#define RDASB_WHDR4\t\t\t\t0x000B6904\n+#define RDASB_RHDR0\t\t\t\t0x000B6AFC\n+#define RDASB_RHDR0_RESPONSE_S\t\t\t27\n+#define RDASB_RHDR0_RESPONSE_M\t\t\tMAKEMASK(0x7, 27)\n+#define RDASB_RDATA0\t\t\t\t0x000B6B00\n+#define RDASB_RDATA1\t\t\t\t0x000B6B04\n+\n+/* SPI Registers */\n+#define SPISB_MSGCTL\t\t\t\t0x000B7020\n+#define SPISB_MSGCTL_HDR_DWS_S\t\t\t0\n+#define SPISB_MSGCTL_EXP_RDW_S\t\t\t8\n+#define SPISB_MSGCTL_MSG_MODE_S\t\t\t26\n+#define SPISB_MSGCTL_TOKEN_MODE_S\t\t28\n+#define SPISB_MSGCTL_BARCLR_S\t\t\t30\n+#define SPISB_MSGCTL_CMDV_S\t\t\t31\n+#define SPISB_MSGCTL_CMDV_M\t\t\tBIT(31)\n+#define SPISB_RSPCTL\t\t\t\t0x000B7024\n+#define SPISB_RSPCTL_BAD_LENGTH_M\t\tBIT(30)\n+#define SPISB_RSPCTL_NOT_SUCCESS_M\t\tBIT(31)\n+#define SPISB_WHDR0\t\t\t\t0x000B70F4\n+#define SPISB_WHDR0_DEST_SEL_S\t\t\t12\n+#define SPISB_WHDR0_OPCODE_SEL_S\t\t16\n+#define SPISB_WHDR0_TAG_S\t\t\t24\n+#define SPISB_WHDR1\t\t\t\t0x000B70F8\n+#define SPISB_WHDR2\t\t\t\t0x000B70FC\n+#define SPISB_RDATA\t\t\t\t0x000B7300\n+#define SPISB_WDATA\t\t\t\t0x000B7100\n+\n+/* Firmware Reset Count register */\n+#define GL_FWRESETCNT\t\t\t\t0x00083100 /* Reset Source: POR */\n+#define GL_FWRESETCNT_FWRESETCNT_S\t\t0\n+#define GL_FWRESETCNT_FWRESETCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+\n+/* Admin Command Interface (ACI) registers */\n+#define PF_HIDA(_i)\t\t\t(0x00085000 + ((_i) * 4))\n+#define PF_HIDA_2(_i)\t\t\t(0x00085020 + ((_i) * 4))\n+#define PF_HIBA(_i)\t\t\t(0x00084000 + ((_i) * 4))\n+#define PF_HICR\t\t\t\t0x00082048\n+\n+#define PF_HIDA_MAX_INDEX\t\t15\n+#define PF_HIBA_MAX_INDEX\t\t1023\n+\n+#define PF_HICR_EN\t\t\tBIT(0)\n+#define PF_HICR_C\t\t\tBIT(1)\n+#define PF_HICR_SV\t\t\tBIT(2)\n+#define PF_HICR_EV\t\t\tBIT(3)\n+\n+#define GL_HIDA(_i)\t\t\t(0x00082000 + ((_i) * 4))\n+#define GL_HIDA_2(_i)\t\t\t(0x00082020 + ((_i) * 4))\n+#define GL_HIBA(_i)\t\t\t(0x00081000 + ((_i) * 4))\n+#define GL_HICR\t\t\t\t0x00082040\n+\n+#define GL_HIDA_MAX_INDEX\t\t15\n+#define GL_HIBA_MAX_INDEX\t\t1023\n+\n+#define GL_HICR_C\t\t\tBIT(1)\n+#define GL_HICR_SV\t\t\tBIT(2)\n+#define GL_HICR_EV\t\t\tBIT(3)\n+\n+#define GL_HICR_EN\t\t\t0x00082044\n+\n+#define GL_HICR_EN_CHECK\t\tBIT(0)\n+\n+/* Admin Command Interface (ACI) defines */\n+/* Defines that help manage the driver vs FW API checks.\n+ */\n+#define IXGBE_FW_API_VER_BRANCH\t\t0x00\n+#define IXGBE_FW_API_VER_MAJOR\t\t0x01\n+#define IXGBE_FW_API_VER_MINOR\t\t0x05\n+#define IXGBE_FW_API_VER_DIFF_ALLOWED\t0x02\n+\n+#define IXGBE_ACI_DESC_SIZE\t\t32\n+#define IXGBE_ACI_DESC_SIZE_IN_DWORDS\tIXGBE_ACI_DESC_SIZE / BYTES_PER_DWORD\n+\n+#define IXGBE_ACI_MAX_BUFFER_SIZE\t\t4096    /* Size in bytes */\n+#define IXGBE_ACI_DESC_COOKIE_L_DWORD_OFFSET\t3\n+#define IXGBE_ACI_SEND_DELAY_TIME_MS\t\t10\n+#define IXGBE_ACI_SEND_MAX_EXECUTE\t\t3\n+/* [ms] timeout of waiting for sync response */\n+#define IXGBE_ACI_SYNC_RESPONSE_TIMEOUT\t\t100000\n+/* [ms] timeout of waiting for async response */\n+#define IXGBE_ACI_ASYNC_RESPONSE_TIMEOUT\t150000\n+/* [ms] timeout of waiting for resource release */\n+#define IXGBE_ACI_RELEASE_RES_TIMEOUT\t\t10000\n+\n+/* Timestamp spacing for Tools ACI: queue is active if spacing is within the range [LO..HI] */\n+#define IXGBE_TOOLS_ACI_ACTIVE_STAMP_SPACING_LO      0\n+#define IXGBE_TOOLS_ACI_ACTIVE_STAMP_SPACING_HI      200\n+\n+/* Timestamp spacing for Tools ACI: queue is expired if spacing is outside the range [LO..HI] */\n+#define IXGBE_TOOLS_ACI_EXPIRED_STAMP_SPACING_LO     -5\n+#define IXGBE_TOOLS_ACI_EXPIRED_STAMP_SPACING_HI     205\n+\n+/* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */\n+#define IXGBE_ACI_LG_BUF\t\t512\n+\n+/* Flags sub-structure\n+ * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |\n+ * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |\n+ */\n+\n+/* command flags and offsets */\n+#define IXGBE_ACI_FLAG_DD_S\t0\n+#define IXGBE_ACI_FLAG_CMP_S\t1\n+#define IXGBE_ACI_FLAG_ERR_S\t2\n+#define IXGBE_ACI_FLAG_VFE_S\t3\n+#define IXGBE_ACI_FLAG_LB_S\t9\n+#define IXGBE_ACI_FLAG_RD_S\t10\n+#define IXGBE_ACI_FLAG_VFC_S\t11\n+#define IXGBE_ACI_FLAG_BUF_S\t12\n+#define IXGBE_ACI_FLAG_SI_S\t13\n+#define IXGBE_ACI_FLAG_EI_S\t14\n+#define IXGBE_ACI_FLAG_FE_S\t15\n+\n+#define IXGBE_ACI_FLAG_DD\t\tBIT(IXGBE_ACI_FLAG_DD_S)  /* 0x1    */\n+#define IXGBE_ACI_FLAG_CMP\t\tBIT(IXGBE_ACI_FLAG_CMP_S) /* 0x2    */\n+#define IXGBE_ACI_FLAG_ERR\t\tBIT(IXGBE_ACI_FLAG_ERR_S) /* 0x4    */\n+#define IXGBE_ACI_FLAG_VFE\t\tBIT(IXGBE_ACI_FLAG_VFE_S) /* 0x8    */\n+#define IXGBE_ACI_FLAG_LB\t\tBIT(IXGBE_ACI_FLAG_LB_S)  /* 0x200  */\n+#define IXGBE_ACI_FLAG_RD\t\tBIT(IXGBE_ACI_FLAG_RD_S)  /* 0x400  */\n+#define IXGBE_ACI_FLAG_VFC\t\tBIT(IXGBE_ACI_FLAG_VFC_S) /* 0x800  */\n+#define IXGBE_ACI_FLAG_BUF\t\tBIT(IXGBE_ACI_FLAG_BUF_S) /* 0x1000 */\n+#define IXGBE_ACI_FLAG_SI\t\tBIT(IXGBE_ACI_FLAG_SI_S)  /* 0x2000 */\n+#define IXGBE_ACI_FLAG_EI\t\tBIT(IXGBE_ACI_FLAG_EI_S)  /* 0x4000 */\n+#define IXGBE_ACI_FLAG_FE\t\tBIT(IXGBE_ACI_FLAG_FE_S)  /* 0x8000 */\n+\n+/* Admin Command Interface (ACI) error codes */\n+enum ixgbe_aci_err {\n+\tIXGBE_ACI_RC_OK\t\t\t= 0,  /* Success */\n+\tIXGBE_ACI_RC_EPERM\t\t= 1,  /* Operation not permitted */\n+\tIXGBE_ACI_RC_ENOENT\t\t= 2,  /* No such element */\n+\tIXGBE_ACI_RC_ESRCH\t\t= 3,  /* Bad opcode */\n+\tIXGBE_ACI_RC_EINTR\t\t= 4,  /* Operation interrupted */\n+\tIXGBE_ACI_RC_EIO\t\t= 5,  /* I/O error */\n+\tIXGBE_ACI_RC_ENXIO\t\t= 6,  /* No such resource */\n+\tIXGBE_ACI_RC_E2BIG\t\t= 7,  /* Arg too long */\n+\tIXGBE_ACI_RC_EAGAIN\t\t= 8,  /* Try again */\n+\tIXGBE_ACI_RC_ENOMEM\t\t= 9,  /* Out of memory */\n+\tIXGBE_ACI_RC_EACCES\t\t= 10, /* Permission denied */\n+\tIXGBE_ACI_RC_EFAULT\t\t= 11, /* Bad address */\n+\tIXGBE_ACI_RC_EBUSY\t\t= 12, /* Device or resource busy */\n+\tIXGBE_ACI_RC_EEXIST\t\t= 13, /* Object already exists */\n+\tIXGBE_ACI_RC_EINVAL\t\t= 14, /* Invalid argument */\n+\tIXGBE_ACI_RC_ENOTTY\t\t= 15, /* Not a typewriter */\n+\tIXGBE_ACI_RC_ENOSPC\t\t= 16, /* No space left or allocation failure */\n+\tIXGBE_ACI_RC_ENOSYS\t\t= 17, /* Function not implemented */\n+\tIXGBE_ACI_RC_ERANGE\t\t= 18, /* Parameter out of range */\n+\tIXGBE_ACI_RC_EFLUSHED\t\t= 19, /* Cmd flushed due to prev cmd error */\n+\tIXGBE_ACI_RC_BAD_ADDR\t\t= 20, /* Descriptor contains a bad pointer */\n+\tIXGBE_ACI_RC_EMODE\t\t= 21, /* Op not allowed in current dev mode */\n+\tIXGBE_ACI_RC_EFBIG\t\t= 22, /* File too big */\n+\tIXGBE_ACI_RC_ESBCOMP\t\t= 23, /* SB-IOSF completion unsuccessful */\n+\tIXGBE_ACI_RC_ENOSEC\t\t= 24, /* Missing security manifest */\n+\tIXGBE_ACI_RC_EBADSIG\t\t= 25, /* Bad RSA signature */\n+\tIXGBE_ACI_RC_ESVN\t\t= 26, /* SVN number prohibits this package */\n+\tIXGBE_ACI_RC_EBADMAN\t\t= 27, /* Manifest hash mismatch */\n+\tIXGBE_ACI_RC_EBADBUF\t\t= 28, /* Buffer hash mismatches manifest */\n+\tIXGBE_ACI_RC_EACCES_BMCU\t= 29, /* BMC Update in progress */\n+};\n+\n+/* Admin Command Interface (ACI) opcodes */\n+enum ixgbe_aci_opc {\n+\tixgbe_aci_opc_get_ver\t\t\t\t= 0x0001,\n+\tixgbe_aci_opc_driver_ver\t\t\t= 0x0002,\n+\tixgbe_aci_opc_get_exp_err\t\t\t= 0x0005,\n+\n+\t/* resource ownership */\n+\tixgbe_aci_opc_req_res\t\t\t\t= 0x0008,\n+\tixgbe_aci_opc_release_res\t\t\t= 0x0009,\n+\n+\t/* device/function capabilities */\n+\tixgbe_aci_opc_list_func_caps\t\t\t= 0x000A,\n+\tixgbe_aci_opc_list_dev_caps\t\t\t= 0x000B,\n+\n+\t/* safe disable of RXEN */\n+\tixgbe_aci_opc_disable_rxen\t\t\t= 0x000C,\n+\n+\t/* FW events */\n+\tixgbe_aci_opc_get_fw_event\t\t\t= 0x0014,\n+\n+\t/* PHY commands */\n+\tixgbe_aci_opc_get_phy_caps\t\t\t= 0x0600,\n+\tixgbe_aci_opc_set_phy_cfg\t\t\t= 0x0601,\n+\tixgbe_aci_opc_restart_an\t\t\t= 0x0605,\n+\tixgbe_aci_opc_get_link_status\t\t\t= 0x0607,\n+\tixgbe_aci_opc_set_event_mask\t\t\t= 0x0613,\n+\tixgbe_aci_opc_get_link_topo\t\t\t= 0x06E0,\n+\tixgbe_aci_opc_get_link_topo_pin\t\t\t= 0x06E1,\n+\tixgbe_aci_opc_read_i2c\t\t\t\t= 0x06E2,\n+\tixgbe_aci_opc_write_i2c\t\t\t\t= 0x06E3,\n+\tixgbe_aci_opc_read_mdio\t\t\t\t= 0x06E4,\n+\tixgbe_aci_opc_write_mdio\t\t\t= 0x06E5,\n+\tixgbe_aci_opc_set_gpio_by_func\t\t\t= 0x06E6,\n+\tixgbe_aci_opc_get_gpio_by_func\t\t\t= 0x06E7,\n+\tixgbe_aci_opc_set_gpio\t\t\t\t= 0x06EC,\n+\tixgbe_aci_opc_get_gpio\t\t\t\t= 0x06ED,\n+\tixgbe_aci_opc_sff_eeprom\t\t\t= 0x06EE,\n+\tixgbe_aci_opc_prog_topo_dev_nvm\t\t\t= 0x06F2,\n+\tixgbe_aci_opc_read_topo_dev_nvm\t\t\t= 0x06F3,\n+\n+\t/* NVM commands */\n+\tixgbe_aci_opc_nvm_read\t\t\t\t= 0x0701,\n+\tixgbe_aci_opc_nvm_erase\t\t\t\t= 0x0702,\n+\tixgbe_aci_opc_nvm_write\t\t\t\t= 0x0703,\n+\tixgbe_aci_opc_nvm_cfg_read\t\t\t= 0x0704,\n+\tixgbe_aci_opc_nvm_cfg_write\t\t\t= 0x0705,\n+\tixgbe_aci_opc_nvm_checksum\t\t\t= 0x0706,\n+\tixgbe_aci_opc_nvm_write_activate\t\t= 0x0707,\n+\tixgbe_aci_opc_nvm_sr_dump\t\t\t= 0x0707,\n+\tixgbe_aci_opc_nvm_save_factory_settings\t\t= 0x0708,\n+\tixgbe_aci_opc_nvm_update_empr\t\t\t= 0x0709,\n+\tixgbe_aci_opc_nvm_pkg_data\t\t\t= 0x070A,\n+\tixgbe_aci_opc_nvm_pass_component_tbl\t\t= 0x070B,\n+\tixgbe_aci_opc_nvm_sanitization\t\t\t= 0x070C,\n+\n+\t/* Alternate Structure Commands */\n+\tixgbe_aci_opc_write_alt_direct\t\t\t= 0x0900,\n+\tixgbe_aci_opc_write_alt_indirect\t\t= 0x0901,\n+\tixgbe_aci_opc_read_alt_direct\t\t\t= 0x0902,\n+\tixgbe_aci_opc_read_alt_indirect\t\t\t= 0x0903,\n+\tixgbe_aci_opc_done_alt_write\t\t\t= 0x0904,\n+\tixgbe_aci_opc_clear_port_alt_write\t\t= 0x0906,\n+\n+\t/* debug commands */\n+\tixgbe_aci_opc_debug_dump_internals\t\t= 0xFF08,\n+\n+\t/* SystemDiagnostic commands */\n+\tixgbe_aci_opc_set_health_status_config\t\t= 0xFF20,\n+\tixgbe_aci_opc_get_supported_health_status_codes\t= 0xFF21,\n+\tixgbe_aci_opc_get_health_status\t\t\t= 0xFF22,\n+\tixgbe_aci_opc_clear_health_status\t\t= 0xFF23,\n+\n+};\n+\n+/* This macro is used to generate a compilation error if a structure\n+ * is not exactly the correct length. It gives a divide by zero error if the\n+ * structure is not of the correct size, otherwise it creates an enum that is\n+ * never used.\n+ */\n+#define IXGBE_CHECK_STRUCT_LEN(n, X) enum ixgbe_static_assert_enum_##X \\\n+\t{ ixgbe_static_assert_##X = (n) / ((sizeof(struct X) == (n)) ? 1 : 0) }\n+\n+/* This macro is used to generate a compilation error if a variable-length\n+ * structure is not exactly the correct length assuming a single element of\n+ * the variable-length object as the last element of the structure. It gives\n+ * a divide by zero error if the structure is not of the correct size,\n+ * otherwise it creates an enum that is never used.\n+ */\n+#define IXGBE_CHECK_VAR_LEN_STRUCT_LEN(n, X, T) enum ixgbe_static_assert_enum_##X \\\n+\t{ ixgbe_static_assert_##X = (n) / \\\n+\t  (((sizeof(struct X) + sizeof(T)) == (n)) ? 1 : 0) }\n+\n+/* This macro is used to ensure that parameter structures (i.e. structures\n+ * in the params union member of struct ixgbe_aci_desc) are 16 bytes in length.\n+ *\n+ * NOT intended to be used to check the size of an indirect command/response\n+ * additional data buffer (e.g. struct foo) which should just happen to be 16\n+ * bytes (instead, use IXGBE_CHECK_STRUCT_LEN(16, foo) for that).\n+ */\n+#define IXGBE_CHECK_PARAM_LEN(X)\tIXGBE_CHECK_STRUCT_LEN(16, X)\n+\n+struct ixgbe_aci_cmd_generic {\n+\t__le32 param0;\n+\t__le32 param1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_generic);\n+\n+/* Get version (direct 0x0001) */\n+struct ixgbe_aci_cmd_get_ver {\n+\t__le32 rom_ver;\n+\t__le32 fw_build;\n+\tu8 fw_branch;\n+\tu8 fw_major;\n+\tu8 fw_minor;\n+\tu8 fw_patch;\n+\tu8 api_branch;\n+\tu8 api_major;\n+\tu8 api_minor;\n+\tu8 api_patch;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_ver);\n+\n+#define IXGBE_DRV_VER_STR_LEN_E610\t32\n+\n+struct ixgbe_driver_ver {\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\tu8 build_ver;\n+\tu8 subbuild_ver;\n+\tu8 driver_string[IXGBE_DRV_VER_STR_LEN_E610];\n+};\n+\n+/* Send driver version (indirect 0x0002) */\n+struct ixgbe_aci_cmd_driver_ver {\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\tu8 build_ver;\n+\tu8 subbuild_ver;\n+\tu8 reserved[4];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_driver_ver);\n+\n+/* Get Expanded Error Code (0x0005, direct) */\n+struct ixgbe_aci_cmd_get_exp_err {\n+\t__le32 reason;\n+#define IXGBE_ACI_EXPANDED_ERROR_NOT_PROVIDED\t0xFFFFFFFF\n+\t__le32 identifier;\n+\tu8 rsvd[8];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_exp_err);\n+\n+/* FW update timeout definitions are in milliseconds */\n+#define IXGBE_NVM_TIMEOUT\t\t180000\n+#define IXGBE_CHANGE_LOCK_TIMEOUT\t1000\n+#define IXGBE_GLOBAL_CFG_LOCK_TIMEOUT\t3000\n+\n+enum ixgbe_aci_res_access_type {\n+\tIXGBE_RES_READ = 1,\n+\tIXGBE_RES_WRITE\n+};\n+\n+enum ixgbe_aci_res_ids {\n+\tIXGBE_NVM_RES_ID = 1,\n+\tIXGBE_SPD_RES_ID,\n+\tIXGBE_CHANGE_LOCK_RES_ID,\n+\tIXGBE_GLOBAL_CFG_LOCK_RES_ID\n+};\n+\n+/* Request resource ownership (direct 0x0008)\n+ * Release resource ownership (direct 0x0009)\n+ */\n+struct ixgbe_aci_cmd_req_res {\n+\t__le16 res_id;\n+#define IXGBE_ACI_RES_ID_NVM\t\t1\n+#define IXGBE_ACI_RES_ID_SDP\t\t2\n+#define IXGBE_ACI_RES_ID_CHNG_LOCK\t3\n+#define IXGBE_ACI_RES_ID_GLBL_LOCK\t4\n+\t__le16 access_type;\n+#define IXGBE_ACI_RES_ACCESS_READ\t1\n+#define IXGBE_ACI_RES_ACCESS_WRITE\t2\n+\n+\t/* Upon successful completion, FW writes this value and driver is\n+\t * expected to release resource before timeout. This value is provided\n+\t * in milliseconds.\n+\t */\n+\t__le32 timeout;\n+#define IXGBE_ACI_RES_NVM_READ_DFLT_TIMEOUT_MS\t3000\n+#define IXGBE_ACI_RES_NVM_WRITE_DFLT_TIMEOUT_MS\t180000\n+#define IXGBE_ACI_RES_CHNG_LOCK_DFLT_TIMEOUT_MS\t1000\n+#define IXGBE_ACI_RES_GLBL_LOCK_DFLT_TIMEOUT_MS\t3000\n+\t/* For SDP: pin ID of the SDP */\n+\t__le32 res_number;\n+\t/* Status is only used for IXGBE_ACI_RES_ID_GLBL_LOCK */\n+\t__le16 status;\n+#define IXGBE_ACI_RES_GLBL_SUCCESS\t\t0\n+#define IXGBE_ACI_RES_GLBL_IN_PROG\t\t1\n+#define IXGBE_ACI_RES_GLBL_DONE\t\t\t2\n+\tu8 reserved[2];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_req_res);\n+\n+/* Get function capabilities (indirect 0x000A)\n+ * Get device capabilities (indirect 0x000B)\n+ */\n+struct ixgbe_aci_cmd_list_caps {\n+\tu8 cmd_flags;\n+\tu8 pf_index;\n+\tu8 reserved[2];\n+\t__le32 count;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_list_caps);\n+\n+/* Device/Function buffer entry, repeated per reported capability */\n+struct ixgbe_aci_cmd_list_caps_elem {\n+\t__le16 cap;\n+#define IXGBE_ACI_CAPS_VALID_FUNCTIONS\t\t\t0x0005\n+#define IXGBE_ACI_MAX_VALID_FUNCTIONS\t\t\t0x8\n+#define IXGBE_ACI_CAPS_VMDQ\t\t\t\t0x0014\n+#define IXGBE_ACI_CAPS_VSI\t\t\t\t0x0017\n+#define IXGBE_ACI_CAPS_DCB\t\t\t\t0x0018\n+#define IXGBE_ACI_CAPS_RSS\t\t\t\t0x0040\n+#define IXGBE_ACI_CAPS_RXQS\t\t\t\t0x0041\n+#define IXGBE_ACI_CAPS_TXQS\t\t\t\t0x0042\n+#define IXGBE_ACI_CAPS_MSIX\t\t\t\t0x0043\n+#define IXGBE_ACI_CAPS_FD\t\t\t\t0x0045\n+#define IXGBE_ACI_CAPS_1588\t\t\t\t0x0046\n+#define IXGBE_ACI_CAPS_MAX_MTU\t\t\t\t0x0047\n+#define IXGBE_ACI_CAPS_NVM_VER\t\t\t\t0x0048\n+#define IXGBE_ACI_CAPS_OROM_VER\t\t\t\t0x004A\n+#define IXGBE_ACI_CAPS_INLINE_IPSEC\t\t\t0x0070\n+#define IXGBE_ACI_CAPS_NUM_ENABLED_PORTS\t\t0x0072\n+#define IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE\t\t0x0076\n+#define IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT\t0x0077\n+#define IXGBE_ACI_CAPS_NVM_MGMT\t\t\t\t0x0080\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0\t\t0x0081\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1\t\t0x0082\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2\t\t0x0083\n+#define IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3\t\t0x0084\n+#define IXGBE_ACI_CAPS_NEXT_CLUSTER_ID\t\t\t0x0096\n+\tu8 major_ver;\n+\tu8 minor_ver;\n+\t/* Number of resources described by this capability */\n+\t__le32 number;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 logical_id;\n+\t/* Only meaningful for some types of resources */\n+\t__le32 phys_id;\n+\t__le64 rsvd1;\n+\t__le64 rsvd2;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(32, ixgbe_aci_cmd_list_caps_elem);\n+\n+/* Disable RXEN (direct 0x000C) */\n+struct ixgbe_aci_cmd_disable_rxen {\n+\tu8 lport_num;\n+\tu8 reserved[15];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_disable_rxen);\n+\n+/* Get FW Event (indirect 0x0014) */\n+struct ixgbe_aci_cmd_get_fw_event {\n+\t__le16 fw_buf_status;\n+#define IXGBE_ACI_GET_FW_EVENT_STATUS_OBTAINED\tBIT(0)\n+#define IXGBE_ACI_GET_FW_EVENT_STATUS_PENDING\tBIT(1)\n+\tu8 rsvd[14];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_fw_event);\n+\n+/* Get PHY capabilities (indirect 0x0600) */\n+struct ixgbe_aci_cmd_get_phy_caps {\n+\tu8 lport_num;\n+\tu8 reserved;\n+\t__le16 param0;\n+\t/* 18.0 - Report qualified modules */\n+#define IXGBE_ACI_GET_PHY_RQM\t\tBIT(0)\n+\t/* 18.1 - 18.3 : Report mode\n+\t * 000b - Report topology capabilities, without media\n+\t * 001b - Report topology capabilities, with media\n+\t * 010b - Report Active configuration\n+\t * 011b - Report PHY Type and FEC mode capabilities\n+\t * 100b - Report Default capabilities\n+\t */\n+#define IXGBE_ACI_REPORT_MODE_S\t\t\t1\n+#define IXGBE_ACI_REPORT_MODE_M\t\t\t(7 << IXGBE_ACI_REPORT_MODE_S)\n+#define IXGBE_ACI_REPORT_TOPO_CAP_NO_MEDIA\t0\n+#define IXGBE_ACI_REPORT_TOPO_CAP_MEDIA\t\tBIT(1)\n+#define IXGBE_ACI_REPORT_ACTIVE_CFG\t\tBIT(2)\n+#define IXGBE_ACI_REPORT_DFLT_CFG\t\tBIT(3)\n+\t__le32 reserved1;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_phy_caps);\n+\n+/* This is #define of PHY type (Extended):\n+ * The first set of defines is for phy_type_low.\n+ */\n+#define IXGBE_PHY_TYPE_LOW_100BASE_TX\t\tBIT_ULL(0)\n+#define IXGBE_PHY_TYPE_LOW_100M_SGMII\t\tBIT_ULL(1)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_T\t\tBIT_ULL(2)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_SX\t\tBIT_ULL(3)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_LX\t\tBIT_ULL(4)\n+#define IXGBE_PHY_TYPE_LOW_1000BASE_KX\t\tBIT_ULL(5)\n+#define IXGBE_PHY_TYPE_LOW_1G_SGMII\t\tBIT_ULL(6)\n+#define IXGBE_PHY_TYPE_LOW_2500BASE_T\t\tBIT_ULL(7)\n+#define IXGBE_PHY_TYPE_LOW_2500BASE_X\t\tBIT_ULL(8)\n+#define IXGBE_PHY_TYPE_LOW_2500BASE_KX\t\tBIT_ULL(9)\n+#define IXGBE_PHY_TYPE_LOW_5GBASE_T\t\tBIT_ULL(10)\n+#define IXGBE_PHY_TYPE_LOW_5GBASE_KR\t\tBIT_ULL(11)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_T\t\tBIT_ULL(12)\n+#define IXGBE_PHY_TYPE_LOW_10G_SFI_DA\t\tBIT_ULL(13)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_SR\t\tBIT_ULL(14)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_LR\t\tBIT_ULL(15)\n+#define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1\tBIT_ULL(16)\n+#define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC\tBIT_ULL(17)\n+#define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C\t\tBIT_ULL(18)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_T\t\tBIT_ULL(19)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_CR\t\tBIT_ULL(20)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_CR_S\t\tBIT_ULL(21)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_CR1\t\tBIT_ULL(22)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_SR\t\tBIT_ULL(23)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_LR\t\tBIT_ULL(24)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_KR\t\tBIT_ULL(25)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_KR_S\t\tBIT_ULL(26)\n+#define IXGBE_PHY_TYPE_LOW_25GBASE_KR1\t\tBIT_ULL(27)\n+#define IXGBE_PHY_TYPE_LOW_25G_AUI_AOC_ACC\tBIT_ULL(28)\n+#define IXGBE_PHY_TYPE_LOW_25G_AUI_C2C\t\tBIT_ULL(29)\n+#define IXGBE_PHY_TYPE_LOW_MAX_INDEX\t\t29\n+/* The second set of defines is for phy_type_high. */\n+#define IXGBE_PHY_TYPE_HIGH_10BASE_T\t\tBIT_ULL(1)\n+#define IXGBE_PHY_TYPE_HIGH_10M_SGMII\t\tBIT_ULL(2)\n+#define IXGBE_PHY_TYPE_HIGH_2500M_SGMII\t\tBIT_ULL(56)\n+#define IXGBE_PHY_TYPE_HIGH_100M_USXGMII\tBIT_ULL(57)\n+#define IXGBE_PHY_TYPE_HIGH_1G_USXGMII\t\tBIT_ULL(58)\n+#define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII\tBIT_ULL(59)\n+#define IXGBE_PHY_TYPE_HIGH_5G_USXGMII\t\tBIT_ULL(60)\n+#define IXGBE_PHY_TYPE_HIGH_10G_USXGMII\t\tBIT_ULL(61)\n+#define IXGBE_PHY_TYPE_HIGH_MAX_INDEX\t\t61\n+\n+struct ixgbe_aci_cmd_get_phy_caps_data {\n+\t__le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\tu8 caps;\n+#define IXGBE_ACI_PHY_EN_TX_LINK_PAUSE\t\t\tBIT(0)\n+#define IXGBE_ACI_PHY_EN_RX_LINK_PAUSE\t\t\tBIT(1)\n+#define IXGBE_ACI_PHY_LOW_POWER_MODE\t\t\tBIT(2)\n+#define IXGBE_ACI_PHY_EN_LINK\t\t\t\tBIT(3)\n+#define IXGBE_ACI_PHY_AN_MODE\t\t\t\tBIT(4)\n+#define IXGBE_ACI_PHY_EN_MOD_QUAL\t\t\tBIT(5)\n+#define IXGBE_ACI_PHY_EN_LESM\t\t\t\tBIT(6)\n+#define IXGBE_ACI_PHY_EN_AUTO_FEC\t\t\tBIT(7)\n+#define IXGBE_ACI_PHY_CAPS_MASK\t\t\t\tMAKEMASK(0xff, 0)\n+\tu8 low_power_ctrl_an;\n+#define IXGBE_ACI_PHY_EN_D3COLD_LOW_POWER_AUTONEG\tBIT(0)\n+#define IXGBE_ACI_PHY_AN_EN_CLAUSE28\t\t\tBIT(1)\n+#define IXGBE_ACI_PHY_AN_EN_CLAUSE73\t\t\tBIT(2)\n+#define IXGBE_ACI_PHY_AN_EN_CLAUSE37\t\t\tBIT(3)\n+\t__le16 eee_cap;\n+#define IXGBE_ACI_PHY_EEE_EN_100BASE_TX\t\t\tBIT(0)\n+#define IXGBE_ACI_PHY_EEE_EN_1000BASE_T\t\t\tBIT(1)\n+#define IXGBE_ACI_PHY_EEE_EN_10GBASE_T\t\t\tBIT(2)\n+#define IXGBE_ACI_PHY_EEE_EN_1000BASE_KX\t\tBIT(3)\n+#define IXGBE_ACI_PHY_EEE_EN_10GBASE_KR\t\t\tBIT(4)\n+#define IXGBE_ACI_PHY_EEE_EN_25GBASE_KR\t\t\tBIT(5)\n+#define IXGBE_ACI_PHY_EEE_EN_10BASE_T\t\t\tBIT(11)\n+\t__le16 eeer_value;\n+\tu8 phy_id_oui[4]; /* PHY/Module ID connected on the port */\n+\tu8 phy_fw_ver[8];\n+\tu8 link_fec_options;\n+#define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_EN\t\tBIT(0)\n+#define IXGBE_ACI_PHY_FEC_10G_KR_40G_KR4_REQ\t\tBIT(1)\n+#define IXGBE_ACI_PHY_FEC_25G_RS_528_REQ\t\tBIT(2)\n+#define IXGBE_ACI_PHY_FEC_25G_KR_REQ\t\t\tBIT(3)\n+#define IXGBE_ACI_PHY_FEC_25G_RS_544_REQ\t\tBIT(4)\n+#define IXGBE_ACI_PHY_FEC_25G_RS_CLAUSE91_EN\t\tBIT(6)\n+#define IXGBE_ACI_PHY_FEC_25G_KR_CLAUSE74_EN\t\tBIT(7)\n+#define IXGBE_ACI_PHY_FEC_MASK\t\t\t\tMAKEMASK(0xdf, 0)\n+\tu8 module_compliance_enforcement;\n+#define IXGBE_ACI_MOD_ENFORCE_STRICT_MODE\t\tBIT(0)\n+\tu8 extended_compliance_code;\n+#define IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE\t\t3\n+\tu8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE];\n+#define IXGBE_ACI_MOD_TYPE_BYTE0_SFP_PLUS\t\t0xA0\n+#define IXGBE_ACI_MOD_TYPE_BYTE0_QSFP_PLUS\t\t0x80\n+#define IXGBE_ACI_MOD_TYPE_IDENT\t\t\t1\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_PASSIVE\tBIT(0)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_SFP_PLUS_CU_ACTIVE\tBIT(1)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_SR\t\tBIT(4)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LR\t\tBIT(5)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_LRM\t\tBIT(6)\n+#define IXGBE_ACI_MOD_TYPE_BYTE1_10G_BASE_ER\t\tBIT(7)\n+#define IXGBE_ACI_MOD_TYPE_BYTE2_SFP_PLUS\t\t0xA0\n+#define IXGBE_ACI_MOD_TYPE_BYTE2_QSFP_PLUS\t\t0x86\n+\tu8 qualified_module_count;\n+\tu8 rsvd2[7];\t/* Bytes 47:41 reserved */\n+#define IXGBE_ACI_QUAL_MOD_COUNT_MAX\t\t\t16\n+\tstruct {\n+\t\tu8 v_oui[3];\n+\t\tu8 rsvd3;\n+\t\tu8 v_part[16];\n+\t\t__le32 v_rev;\n+\t\t__le64 rsvd4;\n+\t} qual_modules[IXGBE_ACI_QUAL_MOD_COUNT_MAX];\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(560, ixgbe_aci_cmd_get_phy_caps_data);\n+\n+/* Set PHY capabilities (direct 0x0601)\n+ * NOTE: This command must be followed by setup link and restart auto-neg\n+ */\n+struct ixgbe_aci_cmd_set_phy_cfg {\n+\tu8 reserved[8];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_phy_cfg);\n+\n+/* Set PHY config command data structure */\n+struct ixgbe_aci_cmd_set_phy_cfg_data {\n+\t__le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\tu8 caps;\n+#define IXGBE_ACI_PHY_ENA_VALID_MASK\t\tMAKEMASK(0xef, 0)\n+#define IXGBE_ACI_PHY_ENA_TX_PAUSE_ABILITY\tBIT(0)\n+#define IXGBE_ACI_PHY_ENA_RX_PAUSE_ABILITY\tBIT(1)\n+#define IXGBE_ACI_PHY_ENA_LOW_POWER\t\tBIT(2)\n+#define IXGBE_ACI_PHY_ENA_LINK\t\t\tBIT(3)\n+#define IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT\tBIT(5)\n+#define IXGBE_ACI_PHY_ENA_LESM\t\t\tBIT(6)\n+#define IXGBE_ACI_PHY_ENA_AUTO_FEC\t\tBIT(7)\n+\tu8 low_power_ctrl_an;\n+\t__le16 eee_cap; /* Value from ixgbe_aci_get_phy_caps */\n+\t__le16 eeer_value; /* Use defines from ixgbe_aci_get_phy_caps */\n+\tu8 link_fec_opt; /* Use defines from ixgbe_aci_get_phy_caps */\n+\tu8 module_compliance_enforcement;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(24, ixgbe_aci_cmd_set_phy_cfg_data);\n+\n+/* Restart AN command data structure (direct 0x0605)\n+ * Also used for response, with only the lport_num field present.\n+ */\n+struct ixgbe_aci_cmd_restart_an {\n+\tu8 reserved[2];\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_RESTART_AN_LINK_RESTART\tBIT(1)\n+#define IXGBE_ACI_RESTART_AN_LINK_ENABLE\tBIT(2)\n+\tu8 reserved2[13];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_restart_an);\n+\n+#pragma pack(1)\n+/* Get link status (indirect 0x0607), also used for Link Status Event */\n+struct ixgbe_aci_cmd_get_link_status {\n+\tu8 reserved[2];\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_LSE_M\t\t\t\t0x3\n+#define IXGBE_ACI_LSE_NOP\t\t\t0x0\n+#define IXGBE_ACI_LSE_DIS\t\t\t0x2\n+#define IXGBE_ACI_LSE_ENA\t\t\t0x3\n+\t/* only response uses this flag */\n+#define IXGBE_ACI_LSE_IS_ENABLED\t\t0x1\n+\tu8 reserved2[5];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_status);\n+\n+/* Get link status response data structure, also used for Link Status Event */\n+struct ixgbe_aci_cmd_get_link_status_data {\n+\tu8 topo_media_conflict;\n+#define IXGBE_ACI_LINK_TOPO_CONFLICT\t\tBIT(0)\n+#define IXGBE_ACI_LINK_MEDIA_CONFLICT\t\tBIT(1)\n+#define IXGBE_ACI_LINK_TOPO_CORRUPT\t\tBIT(2)\n+#define IXGBE_ACI_LINK_TOPO_UNREACH_PRT\t\tBIT(4)\n+#define IXGBE_ACI_LINK_TOPO_UNDRUTIL_PRT\tBIT(5)\n+#define IXGBE_ACI_LINK_TOPO_UNDRUTIL_MEDIA\tBIT(6)\n+#define IXGBE_ACI_LINK_TOPO_UNSUPP_MEDIA\tBIT(7)\n+\tu8 link_cfg_err;\n+#define IXGBE_ACI_LINK_CFG_ERR\t\t\t\tBIT(0)\n+#define IXGBE_ACI_LINK_CFG_COMPLETED\t\t\tBIT(1)\n+#define IXGBE_ACI_LINK_ACT_PORT_OPT_INVAL\t\tBIT(2)\n+#define IXGBE_ACI_LINK_FEAT_ID_OR_CONFIG_ID_INVAL\tBIT(3)\n+#define IXGBE_ACI_LINK_TOPO_CRITICAL_SDP_ERR\t\tBIT(4)\n+#define IXGBE_ACI_LINK_MODULE_POWER_UNSUPPORTED\t\tBIT(5)\n+#define IXGBE_ACI_LINK_EXTERNAL_PHY_LOAD_FAILURE\tBIT(6)\n+#define IXGBE_ACI_LINK_INVAL_MAX_POWER_LIMIT\t\tBIT(7)\n+\tu8 link_info;\n+#define IXGBE_ACI_LINK_UP\t\tBIT(0)\t/* Link Status */\n+#define IXGBE_ACI_LINK_FAULT\t\tBIT(1)\n+#define IXGBE_ACI_LINK_FAULT_TX\t\tBIT(2)\n+#define IXGBE_ACI_LINK_FAULT_RX\t\tBIT(3)\n+#define IXGBE_ACI_LINK_FAULT_REMOTE\tBIT(4)\n+#define IXGBE_ACI_LINK_UP_PORT\t\tBIT(5)\t/* External Port Link Status */\n+#define IXGBE_ACI_MEDIA_AVAILABLE\tBIT(6)\n+#define IXGBE_ACI_SIGNAL_DETECT\t\tBIT(7)\n+\tu8 an_info;\n+#define IXGBE_ACI_AN_COMPLETED\t\tBIT(0)\n+#define IXGBE_ACI_LP_AN_ABILITY\t\tBIT(1)\n+#define IXGBE_ACI_PD_FAULT\t\tBIT(2)\t/* Parallel Detection Fault */\n+#define IXGBE_ACI_FEC_EN\t\tBIT(3)\n+#define IXGBE_ACI_PHY_LOW_POWER\t\tBIT(4)\t/* Low Power State */\n+#define IXGBE_ACI_LINK_PAUSE_TX\t\tBIT(5)\n+#define IXGBE_ACI_LINK_PAUSE_RX\t\tBIT(6)\n+#define IXGBE_ACI_QUALIFIED_MODULE\tBIT(7)\n+\tu8 ext_info;\n+#define IXGBE_ACI_LINK_PHY_TEMP_ALARM\tBIT(0)\n+#define IXGBE_ACI_LINK_EXCESSIVE_ERRORS\tBIT(1)\t/* Excessive Link Errors */\n+\t/* Port Tx Suspended */\n+#define IXGBE_ACI_LINK_TX_S\t\t2\n+#define IXGBE_ACI_LINK_TX_M\t\t(0x03 << IXGBE_ACI_LINK_TX_S)\n+#define IXGBE_ACI_LINK_TX_ACTIVE\t0\n+#define IXGBE_ACI_LINK_TX_DRAINED\t1\n+#define IXGBE_ACI_LINK_TX_FLUSHED\t3\n+\tu8 lb_status;\n+#define IXGBE_ACI_LINK_LB_PHY_LCL\tBIT(0)\n+#define IXGBE_ACI_LINK_LB_PHY_RMT\tBIT(1)\n+#define IXGBE_ACI_LINK_LB_MAC_LCL\tBIT(2)\n+#define IXGBE_ACI_LINK_LB_PHY_IDX_S\t3\n+#define IXGBE_ACI_LINK_LB_PHY_IDX_M\t(0x7 << IXGBE_ACI_LB_PHY_IDX_S)\n+\t__le16 max_frame_size;\n+\tu8 cfg;\n+#define IXGBE_ACI_LINK_25G_KR_FEC_EN\t\tBIT(0)\n+#define IXGBE_ACI_LINK_25G_RS_528_FEC_EN\tBIT(1)\n+#define IXGBE_ACI_LINK_25G_RS_544_FEC_EN\tBIT(2)\n+#define IXGBE_ACI_FEC_MASK\t\t\tMAKEMASK(0x7, 0)\n+\t/* Pacing Config */\n+#define IXGBE_ACI_CFG_PACING_S\t\t3\n+#define IXGBE_ACI_CFG_PACING_M\t\t(0xF << IXGBE_ACI_CFG_PACING_S)\n+#define IXGBE_ACI_CFG_PACING_TYPE_M\tBIT(7)\n+#define IXGBE_ACI_CFG_PACING_TYPE_AVG\t0\n+#define IXGBE_ACI_CFG_PACING_TYPE_FIXED\tIXGBE_ACI_CFG_PACING_TYPE_M\n+\t/* External Device Power Ability */\n+\tu8 power_desc;\n+#define IXGBE_ACI_PWR_CLASS_M\t\t\t0x3F\n+#define IXGBE_ACI_LINK_PWR_BASET_LOW_HIGH\t0\n+#define IXGBE_ACI_LINK_PWR_BASET_HIGH\t\t1\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_1\t\t0\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_2\t\t1\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_3\t\t2\n+#define IXGBE_ACI_LINK_PWR_QSFP_CLASS_4\t\t3\n+\t__le16 link_speed;\n+#define IXGBE_ACI_LINK_SPEED_M\t\t\t0x7FF\n+#define IXGBE_ACI_LINK_SPEED_10MB\t\tBIT(0)\n+#define IXGBE_ACI_LINK_SPEED_100MB\t\tBIT(1)\n+#define IXGBE_ACI_LINK_SPEED_1000MB\t\tBIT(2)\n+#define IXGBE_ACI_LINK_SPEED_2500MB\t\tBIT(3)\n+#define IXGBE_ACI_LINK_SPEED_5GB\t\tBIT(4)\n+#define IXGBE_ACI_LINK_SPEED_10GB\t\tBIT(5)\n+#define IXGBE_ACI_LINK_SPEED_20GB\t\tBIT(6)\n+#define IXGBE_ACI_LINK_SPEED_25GB\t\tBIT(7)\n+#define IXGBE_ACI_LINK_SPEED_40GB\t\tBIT(8)\n+#define IXGBE_ACI_LINK_SPEED_50GB\t\tBIT(9)\n+#define IXGBE_ACI_LINK_SPEED_100GB\t\tBIT(10)\n+#define IXGBE_ACI_LINK_SPEED_200GB\t\tBIT(11)\n+#define IXGBE_ACI_LINK_SPEED_UNKNOWN\t\tBIT(15)\n+\t__le16 reserved3; /* Aligns next field to 8-byte boundary */\n+\tu8 ext_fec_status;\n+#define IXGBE_ACI_LINK_RS_272_FEC_EN\tBIT(0) /* RS 272 FEC enabled */\n+\tu8 reserved4;\n+\t__le64 phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\t/* Get link status version 2 link partner data */\n+\t__le64 lp_phy_type_low; /* Use values from IXGBE_PHY_TYPE_LOW_* */\n+\t__le64 lp_phy_type_high; /* Use values from IXGBE_PHY_TYPE_HIGH_* */\n+\tu8 lp_fec_adv;\n+#define IXGBE_ACI_LINK_LP_10G_KR_FEC_CAP\tBIT(0)\n+#define IXGBE_ACI_LINK_LP_25G_KR_FEC_CAP\tBIT(1)\n+#define IXGBE_ACI_LINK_LP_RS_528_FEC_CAP\tBIT(2)\n+#define IXGBE_ACI_LINK_LP_50G_KR_272_FEC_CAP\tBIT(3)\n+#define IXGBE_ACI_LINK_LP_100G_KR_272_FEC_CAP\tBIT(4)\n+#define IXGBE_ACI_LINK_LP_200G_KR_272_FEC_CAP\tBIT(5)\n+\tu8 lp_fec_req;\n+#define IXGBE_ACI_LINK_LP_10G_KR_FEC_REQ\tBIT(0)\n+#define IXGBE_ACI_LINK_LP_25G_KR_FEC_REQ\tBIT(1)\n+#define IXGBE_ACI_LINK_LP_RS_528_FEC_REQ\tBIT(2)\n+#define IXGBE_ACI_LINK_LP_KR_272_FEC_REQ\tBIT(3)\n+\tu8 lp_flowcontrol;\n+#define IXGBE_ACI_LINK_LP_PAUSE_ADV\t\tBIT(0)\n+#define IXGBE_ACI_LINK_LP_ASM_DIR_ADV\t\tBIT(1)\n+\tu8 reserved5[5];\n+};\n+#pragma pack()\n+\n+IXGBE_CHECK_STRUCT_LEN(56, ixgbe_aci_cmd_get_link_status_data);\n+\n+/* Set event mask command (direct 0x0613) */\n+struct ixgbe_aci_cmd_set_event_mask {\n+\tu8\treserved[8];\n+\t__le16\tevent_mask;\n+#define IXGBE_ACI_LINK_EVENT_UPDOWN\t\tBIT(1)\n+#define IXGBE_ACI_LINK_EVENT_MEDIA_NA\t\tBIT(2)\n+#define IXGBE_ACI_LINK_EVENT_LINK_FAULT\t\tBIT(3)\n+#define IXGBE_ACI_LINK_EVENT_PHY_TEMP_ALARM\tBIT(4)\n+#define IXGBE_ACI_LINK_EVENT_EXCESSIVE_ERRORS\tBIT(5)\n+#define IXGBE_ACI_LINK_EVENT_SIGNAL_DETECT\tBIT(6)\n+#define IXGBE_ACI_LINK_EVENT_AN_COMPLETED\tBIT(7)\n+#define IXGBE_ACI_LINK_EVENT_MODULE_QUAL_FAIL\tBIT(8)\n+#define IXGBE_ACI_LINK_EVENT_PORT_TX_SUSPENDED\tBIT(9)\n+#define IXGBE_ACI_LINK_EVENT_TOPO_CONFLICT\tBIT(10)\n+#define IXGBE_ACI_LINK_EVENT_MEDIA_CONFLICT\tBIT(11)\n+#define IXGBE_ACI_LINK_EVENT_PHY_FW_LOAD_FAIL\tBIT(12)\n+\tu8\treserved1[6];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_event_mask);\n+\n+struct ixgbe_aci_cmd_link_topo_params {\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define IXGBE_ACI_LINK_TOPO_PORT_NUM_VALID\tBIT(0)\n+\tu8 node_type_ctx;\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_S\t\t0\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_M\t\t(0xF << IXGBE_ACI_LINK_TOPO_NODE_TYPE_S)\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_PHY\t0\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPIO_CTRL\t1\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MUX_CTRL\t2\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED_CTRL\t3\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_LED\t4\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_THERMAL\t5\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_CAGE\t6\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_MEZZ\t7\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_ID_EEPROM\t8\n+#define IXGBE_ACI_LINK_TOPO_NODE_TYPE_GPS\t11\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_S\t\t4\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_M\t\t\\\n+\t\t\t\t(0xF << IXGBE_ACI_LINK_TOPO_NODE_CTX_S)\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_GLOBAL\t\t\t0\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_BOARD\t\t\t1\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_PORT\t\t\t2\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE\t\t\t3\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE\t\t4\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_DIRECT_BUS_ACCESS\t\t5\n+#define IXGBE_ACI_LINK_TOPO_NODE_CTX_NODE_HANDLE_BUS_ADDRESS\t6\n+\tu8 index;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(4, ixgbe_aci_cmd_link_topo_params);\n+\n+struct ixgbe_aci_cmd_link_topo_addr {\n+\tstruct ixgbe_aci_cmd_link_topo_params topo_params;\n+\t__le16 handle;\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_S\t0\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_M\t(0x3FF << IXGBE_ACI_LINK_TOPO_HANDLE_S)\n+/* Used to decode the handle field */\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_M\t\tBIT(9)\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_LOM\t\tBIT(9)\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_BRD_TYPE_MEZZ\t0\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S\t\t0\n+/* In case of a Mezzanine type */\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_NODE_M\t\\\n+\t\t\t\t(0x3F << IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S)\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_S\t6\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_M\t\\\n+\t\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_HANDLE_MEZZ_S)\n+/* In case of a LOM type */\n+#define IXGBE_ACI_LINK_TOPO_HANDLE_LOM_NODE_M\t\\\n+\t\t\t\t(0x1FF << IXGBE_ACI_LINK_TOPO_HANDLE_NODE_S)\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(6, ixgbe_aci_cmd_link_topo_addr);\n+\n+/* Get Link Topology Handle (direct, 0x06E0) */\n+struct ixgbe_aci_cmd_get_link_topo {\n+\tstruct ixgbe_aci_cmd_link_topo_addr addr;\n+\tu8 node_part_num;\n+#define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_PCA9575\t\t0x21\n+#define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_GEN_GPS\t\t0x48\n+#define IXGBE_ACI_GET_LINK_TOPO_NODE_NR_E610_PTC\t0x49\n+\tu8 rsvd[9];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_topo);\n+\n+/* Get Link Topology Pin (direct, 0x06E1) */\n+struct ixgbe_aci_cmd_get_link_topo_pin {\n+\tstruct ixgbe_aci_cmd_link_topo_addr addr;\n+\tu8 input_io_params;\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_S\t0\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_M\t\\\n+\t\t\t\t(0x1F << IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_S)\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_GPIO\t0\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RESET_N\t1\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_INT_N\t2\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_PRESENT_N\t3\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_DIS\t4\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_MODSEL_N\t5\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_LPMODE\t6\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_TX_FAULT\t7\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RX_LOSS\t8\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS0\t\t9\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RS1\t\t10\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_EEPROM_WP\t11\n+/* 12 repeats intentionally due to two different uses depending on context */\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_LED\t\t12\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_RED_LED\t12\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_GREEN_LED\t13\n+#define IXGBE_ACI_LINK_TOPO_IO_FUNC_BLUE_LED\t14\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_S\t5\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_M\t\\\n+\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_S)\n+#define IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_GPIO\t3\n+/* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */\n+\tu8 output_io_params;\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_FUNC_S\t0\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_FUNC_M\t\\\n+\t\t\t(0x1F << \\ IXGBE_ACI_LINK_TOPO_INPUT_IO_FUNC_NUM_S)\n+/* Use IXGBE_ACI_LINK_TOPO_IO_FUNC_* for the non-numerical options */\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_TYPE_S\t5\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_IO_TYPE_M\t\\\n+\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_INPUT_IO_TYPE_S)\n+/* Use IXGBE_ACI_LINK_TOPO_NODE_TYPE_* for the type values */\n+\tu8 output_io_flags;\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_SPEED_S\t0\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_SPEED_M\t\\\n+\t\t\t(0x7 << IXGBE_ACI_LINK_TOPO_OUTPUT_SPEED_S)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_INT_S\t3\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_INT_M\t\\\n+\t\t\t(0x3 << IXGBE_ACI_LINK_TOPO_OUTPUT_INT_S)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_POLARITY\tBIT(5)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_VALUE\tBIT(6)\n+#define IXGBE_ACI_LINK_TOPO_OUTPUT_DRIVEN\tBIT(7)\n+\tu8 rsvd[7];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_link_topo_pin);\n+/* Read/Write I2C (direct, 0x06E2/0x06E3) */\n+struct ixgbe_aci_cmd_i2c {\n+\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr;\n+\t__le16 i2c_addr;\n+\tu8 i2c_params;\n+#define IXGBE_ACI_I2C_DATA_SIZE_S\t\t0\n+#define IXGBE_ACI_I2C_DATA_SIZE_M\t\t(0xF << IXGBE_ACI_I2C_DATA_SIZE_S)\n+#define IXGBE_ACI_I2C_ADDR_TYPE_M\t\tBIT(4)\n+#define IXGBE_ACI_I2C_ADDR_TYPE_7BIT\t\t0\n+#define IXGBE_ACI_I2C_ADDR_TYPE_10BIT\t\tIXGBE_ACI_I2C_ADDR_TYPE_M\n+#define IXGBE_ACI_I2C_DATA_OFFSET_S\t\t5\n+#define IXGBE_ACI_I2C_DATA_OFFSET_M\t\t(0x3 << IXGBE_ACI_I2C_DATA_OFFSET_S)\n+#define IXGBE_ACI_I2C_USE_REPEATED_START\tBIT(7)\n+\tu8 rsvd;\n+\t__le16 i2c_bus_addr;\n+#define IXGBE_ACI_I2C_ADDR_7BIT_MASK\t\t0x7F\n+#define IXGBE_ACI_I2C_ADDR_10BIT_MASK\t\t0x3FF\n+\tu8 i2c_data[4]; /* Used only by write command, reserved in read. */\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_i2c);\n+\n+/* Read I2C Response (direct, 0x06E2) */\n+struct ixgbe_aci_cmd_read_i2c_resp {\n+\tu8 i2c_data[16];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_i2c_resp);\n+\n+/* Read/Write MDIO (direct, 0x06E4/0x06E5) */\n+struct ixgbe_aci_cmd_mdio {\n+\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr;\n+\tu8 mdio_device_addr;\n+#define IXGBE_ACI_MDIO_DEV_S\t\t0\n+#define IXGBE_ACI_MDIO_DEV_M\t\t(0x1F << IXGBE_ACI_MDIO_DEV_S)\n+#define IXGBE_ACI_MDIO_CLAUSE_22\tBIT(5)\n+#define IXGBE_ACI_MDIO_CLAUSE_45\tBIT(6)\n+\tu8 mdio_bus_address;\n+#define IXGBE_ACI_MDIO_BUS_ADDR_S 0\n+#define IXGBE_ACI_MDIO_BUS_ADDR_M (0x1F << IXGBE_ACI_MDIO_BUS_ADDR_S)\n+\t__le16 offset;\n+\t__le16 data; /* Input in write cmd, output in read cmd. */\n+\tu8 rsvd1[4];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_mdio);\n+\n+/* Set/Get GPIO By Function (direct, 0x06E6/0x06E7) */\n+struct ixgbe_aci_cmd_gpio_by_func {\n+\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr;\n+\tu8 io_func_num;\n+#define IXGBE_ACI_GPIO_FUNC_S\t0\n+#define IXGBE_ACI_GPIO_FUNC_M\t(0x1F << IXGBE_ACI_GPIO_IO_FUNC_NUM_S)\n+\tu8 io_value; /* Input in write cmd, output in read cmd. */\n+#define IXGBE_ACI_GPIO_ON\tBIT(0)\n+#define IXGBE_ACI_GPIO_OFF\t0\n+\tu8 rsvd[8];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_gpio_by_func);\n+\n+/* Set/Get GPIO (direct, 0x06EC/0x06ED) */\n+struct ixgbe_aci_cmd_gpio {\n+\t__le16 gpio_ctrl_handle;\n+#define IXGBE_ACI_GPIO_HANDLE_S\t0\n+#define IXGBE_ACI_GPIO_HANDLE_M\t(0x3FF << IXGBE_ACI_GPIO_HANDLE_S)\n+\tu8 gpio_num;\n+\tu8 gpio_val;\n+\tu8 rsvd[12];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_gpio);\n+\n+/* Read/Write SFF EEPROM command (indirect 0x06EE) */\n+struct ixgbe_aci_cmd_sff_eeprom {\n+\tu8 lport_num;\n+\tu8 lport_num_valid;\n+#define IXGBE_ACI_SFF_PORT_NUM_VALID\t\tBIT(0)\n+\t__le16 i2c_bus_addr;\n+#define IXGBE_ACI_SFF_I2CBUS_7BIT_M\t\t0x7F\n+#define IXGBE_ACI_SFF_I2CBUS_10BIT_M\t\t0x3FF\n+#define IXGBE_ACI_SFF_I2CBUS_TYPE_M\t\tBIT(10)\n+#define IXGBE_ACI_SFF_I2CBUS_TYPE_7BIT\t\t0\n+#define IXGBE_ACI_SFF_I2CBUS_TYPE_10BIT\t\tIXGBE_ACI_SFF_I2CBUS_TYPE_M\n+#define IXGBE_ACI_SFF_PAGE_BANK_CTRL_S\t\t11\n+#define IXGBE_ACI_SFF_PAGE_BANK_CTRL_M\t\t(0x3 << IXGBE_ACI_SFF_PAGE_BANK_CTRL_S)\n+#define IXGBE_ACI_SFF_NO_PAGE_BANK_UPDATE\t0\n+#define IXGBE_ACI_SFF_UPDATE_PAGE\t\t1\n+#define IXGBE_ACI_SFF_UPDATE_BANK\t\t2\n+#define IXGBE_ACI_SFF_UPDATE_PAGE_BANK\t\t3\n+#define IXGBE_ACI_SFF_IS_WRITE\t\t\tBIT(15)\n+\t__le16 i2c_offset;\n+\tu8 module_bank;\n+\tu8 module_page;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_sff_eeprom);\n+\n+/* Program Topology Device NVM (direct, 0x06F2) */\n+struct ixgbe_aci_cmd_prog_topo_dev_nvm {\n+\tstruct ixgbe_aci_cmd_link_topo_params topo_params;\n+\tu8 rsvd[12];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_prog_topo_dev_nvm);\n+\n+/* Read Topology Device NVM (direct, 0x06F3) */\n+struct ixgbe_aci_cmd_read_topo_dev_nvm {\n+\tstruct ixgbe_aci_cmd_link_topo_params topo_params;\n+\t__le32 start_address;\n+#define IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE 8\n+\tu8 data_read[IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_topo_dev_nvm);\n+\n+/* NVM Read command (indirect 0x0701)\n+ * NVM Erase commands (direct 0x0702)\n+ * NVM Write commands (indirect 0x0703)\n+ * NVM Write Activate commands (direct 0x0707)\n+ * NVM Shadow RAM Dump commands (direct 0x0707)\n+ */\n+struct ixgbe_aci_cmd_nvm {\n+#define IXGBE_ACI_NVM_MAX_OFFSET\t0xFFFFFF\n+\t__le16 offset_low;\n+\tu8 offset_high; /* For Write Activate offset_high is used as flags2 */\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_NVM_LAST_CMD\t\tBIT(0)\n+#define IXGBE_ACI_NVM_PCIR_REQ\t\tBIT(0)\t/* Used by NVM Write reply */\n+#define IXGBE_ACI_NVM_PRESERVATION_S\t1 /* Used by NVM Write Activate only */\n+#define IXGBE_ACI_NVM_PRESERVATION_M\t(3 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_NO_PRESERVATION\t(0 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_PRESERVE_ALL\tBIT(1)\n+#define IXGBE_ACI_NVM_FACTORY_DEFAULT\t(2 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_PRESERVE_SELECTED\t(3 << IXGBE_ACI_NVM_PRESERVATION_S)\n+#define IXGBE_ACI_NVM_ACTIV_SEL_NVM\tBIT(3) /* Write Activate/SR Dump only */\n+#define IXGBE_ACI_NVM_ACTIV_SEL_OROM\tBIT(4)\n+#define IXGBE_ACI_NVM_ACTIV_SEL_NETLIST\tBIT(5)\n+#define IXGBE_ACI_NVM_SPECIAL_UPDATE\tBIT(6)\n+#define IXGBE_ACI_NVM_REVERT_LAST_ACTIV\tBIT(6) /* Write Activate only */\n+#define IXGBE_ACI_NVM_ACTIV_SEL_MASK\tMAKEMASK(0x7, 3)\n+#define IXGBE_ACI_NVM_FLASH_ONLY\t\tBIT(7)\n+#define IXGBE_ACI_NVM_RESET_LVL_M\t\tMAKEMASK(0x3, 0) /* Write reply only */\n+#define IXGBE_ACI_NVM_POR_FLAG\t\t0\n+#define IXGBE_ACI_NVM_PERST_FLAG\t1\n+#define IXGBE_ACI_NVM_EMPR_FLAG\t\t2\n+#define IXGBE_ACI_NVM_EMPR_ENA\t\tBIT(0) /* Write Activate reply only */\n+\t/* For Write Activate, several flags are sent as part of a separate\n+\t * flags2 field using a separate byte. For simplicity of the software\n+\t * interface, we pass the flags as a 16 bit value so these flags are\n+\t * all offset by 8 bits\n+\t */\n+#define IXGBE_ACI_NVM_ACTIV_REQ_EMPR\tBIT(8) /* NVM Write Activate only */\n+\t__le16 module_typeid;\n+\t__le16 length;\n+#define IXGBE_ACI_NVM_ERASE_LEN\t0xFFFF\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+/* NVM Module_Type ID, needed offset and read_len for struct ixgbe_aci_cmd_nvm. */\n+#define IXGBE_ACI_NVM_SECTOR_UNIT\t\t4096 /* In Bytes */\n+#define IXGBE_ACI_NVM_WORD_UNIT\t\t\t2 /* In Bytes */\n+\n+#define IXGBE_ACI_NVM_START_POINT\t\t0\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_OFFSET\t\t0x90\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_RD_LEN\t\t2 /* In Bytes */\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_M\t\tMAKEMASK(0x7FFF, 0)\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_S\t\t15\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_M\t\tBIT(15)\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_SECTOR\t1\n+\n+#define IXGBE_ACI_NVM_LLDP_CFG_PTR_OFFSET\t0x46\n+#define IXGBE_ACI_NVM_LLDP_CFG_HEADER_LEN\t2 /* In Bytes */\n+#define IXGBE_ACI_NVM_LLDP_CFG_PTR_RD_LEN\t2 /* In Bytes */\n+\n+#define IXGBE_ACI_NVM_LLDP_PRESERVED_MOD_ID\t\t0x129\n+#define IXGBE_ACI_NVM_CUR_LLDP_PERSIST_RD_OFFSET\t2 /* In Bytes */\n+#define IXGBE_ACI_NVM_LLDP_STATUS_M\t\t\tMAKEMASK(0xF, 0)\n+#define IXGBE_ACI_NVM_LLDP_STATUS_M_LEN\t\t\t4 /* In Bits */\n+#define IXGBE_ACI_NVM_LLDP_STATUS_RD_LEN\t\t4 /* In Bytes */\n+\n+#define IXGBE_ACI_NVM_MINSREV_MOD_ID\t\t0x130\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm);\n+\n+/* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the\n+ * type field is excluded from the section when reading and writing from\n+ * a module using the module_typeid field with these AQ commands.\n+ */\n+struct ixgbe_aci_cmd_nvm_minsrev {\n+\t__le16 length;\n+\t__le16 validity;\n+#define IXGBE_ACI_NVM_MINSREV_NVM_VALID\t\tBIT(0)\n+#define IXGBE_ACI_NVM_MINSREV_OROM_VALID\tBIT(1)\n+\t__le16 nvm_minsrev_l;\n+\t__le16 nvm_minsrev_h;\n+\t__le16 orom_minsrev_l;\n+\t__le16 orom_minsrev_h;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(12, ixgbe_aci_cmd_nvm_minsrev);\n+\n+/* Used for 0x0704 as well as for 0x0705 commands */\n+struct ixgbe_aci_cmd_nvm_cfg {\n+\tu8\tcmd_flags;\n+#define IXGBE_ACI_ANVM_MULTIPLE_ELEMS\tBIT(0)\n+#define IXGBE_ACI_ANVM_IMMEDIATE_FIELD\tBIT(1)\n+#define IXGBE_ACI_ANVM_NEW_CFG\t\tBIT(2)\n+\tu8\treserved;\n+\t__le16 count;\n+\t__le16 id;\n+\tu8 reserved1[2];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_cfg);\n+\n+struct ixgbe_aci_cmd_nvm_cfg_data {\n+\t__le16 field_id;\n+\t__le16 field_options;\n+\t__le16 field_value;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(6, ixgbe_aci_cmd_nvm_cfg_data);\n+\n+/* NVM Checksum Command (direct, 0x0706) */\n+struct ixgbe_aci_cmd_nvm_checksum {\n+\tu8 flags;\n+#define IXGBE_ACI_NVM_CHECKSUM_VERIFY\tBIT(0)\n+#define IXGBE_ACI_NVM_CHECKSUM_RECALC\tBIT(1)\n+\tu8 rsvd;\n+\t__le16 checksum; /* Used only by response */\n+#define IXGBE_ACI_NVM_CHECKSUM_CORRECT\t0xBABA\n+\tu8 rsvd2[12];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_checksum);\n+\n+/* Used for NVM Sanitization command - 0x070C */\n+struct ixgbe_aci_cmd_nvm_sanitization {\n+\tu8 cmd_flags;\n+#define IXGBE_ACI_SANITIZE_REQ_READ\t\t\t0\n+#define IXGBE_ACI_SANITIZE_REQ_OPERATE\t\t\tBIT(0)\n+\n+#define IXGBE_ACI_SANITIZE_READ_SUBJECT_NVM_BITS\t0\n+#define IXGBE_ACI_SANITIZE_READ_SUBJECT_NVM_STATE\tBIT(1)\n+#define IXGBE_ACI_SANITIZE_OPERATE_SUBJECT_CLEAR\t0\n+\tu8 values;\n+#define IXGBE_ACI_SANITIZE_NVM_BITS_HOST_CLEAN_SUPPORT\tBIT(0)\n+#define IXGBE_ACI_SANITIZE_NVM_BITS_BMC_CLEAN_SUPPORT\tBIT(2)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_DONE\tBIT(0)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_HOST_CLEAN_SUCCESS\tBIT(1)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_DONE\tBIT(2)\n+#define IXGBE_ACI_SANITIZE_NVM_STATE_BMC_CLEAN_SUCCESS\tBIT(3)\n+#define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE\tBIT(0)\n+#define IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS\tBIT(1)\n+#define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE\tBIT(2)\n+#define IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS\tBIT(3)\n+\tu8 reserved[14];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_sanitization);\n+\n+/* Write/Read Alternate - Direct (direct 0x0900/0x0902) */\n+struct ixgbe_aci_cmd_read_write_alt_direct {\n+\t__le32 dword0_addr;\n+\t__le32 dword0_value;\n+\t__le32 dword1_addr;\n+\t__le32 dword1_value;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_write_alt_direct);\n+\n+/* Write/Read Alternate - Indirect (indirect 0x0901/0x0903) */\n+struct ixgbe_aci_cmd_read_write_alt_indirect {\n+\t__le32 base_dword_addr;\n+\t__le32 num_dwords;\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_read_write_alt_indirect);\n+\n+/* Done Alternate Write (direct 0x0904) */\n+struct ixgbe_aci_cmd_done_alt_write {\n+\tu8 flags;\n+#define IXGBE_ACI_CMD_UEFI_BIOS_MODE\tBIT(0)\n+#define IXGBE_ACI_RESP_RESET_NEEDED\tBIT(1)\n+\tu8 reserved[15];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_done_alt_write);\n+\n+/* Clear Port Alternate Write (direct 0x0906) */\n+struct ixgbe_aci_cmd_clear_port_alt_write {\n+\tu8 reserved[16];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_clear_port_alt_write);\n+\n+/* Get CGU abilities command response data structure (indirect 0x0C61) */\n+struct ixgbe_aci_cmd_get_cgu_abilities {\n+\tu8 num_inputs;\n+\tu8 num_outputs;\n+\tu8 pps_dpll_idx;\n+\tu8 synce_dpll_idx;\n+\t__le32 max_in_freq;\n+\t__le32 max_in_phase_adj;\n+\t__le32 max_out_freq;\n+\t__le32 max_out_phase_adj;\n+\tu8 cgu_part_num;\n+\tu8 rsvd[3];\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(24, ixgbe_aci_cmd_get_cgu_abilities);\n+\n+#define IXGBE_ACI_NODE_HANDLE_VALID\tBIT(10)\n+#define IXGBE_ACI_NODE_HANDLE\t\tMAKEMASK(0x3FF, 0)\n+#define IXGBE_ACI_DRIVING_CLK_NUM_SHIFT\t10\n+#define IXGBE_ACI_DRIVING_CLK_NUM\tMAKEMASK(0x3F, IXGBE_ACI_DRIVING_CLK_NUM_SHIFT)\n+\n+/* Set CGU input config (direct 0x0C62) */\n+struct ixgbe_aci_cmd_set_cgu_input_config {\n+\tu8 input_idx;\n+\tu8 flags1;\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ\tBIT(6)\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY\tBIT(7)\n+\tu8 flags2;\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_INPUT_EN\t\tBIT(5)\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_ESYNC_EN\t\tBIT(6)\n+\tu8 rsvd;\n+\t__le32 freq;\n+\t__le32 phase_delay;\n+\tu8 rsvd2[2];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_input_config);\n+\n+/* Get CGU input config response descriptor structure (direct 0x0C63) */\n+struct ixgbe_aci_cmd_get_cgu_input_config {\n+\tu8 input_idx;\n+\tu8 status;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_LOS\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_SCM_FAIL\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_CFM_FAIL\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_GST_FAIL\tBIT(3)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_PFM_FAIL\tBIT(4)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL\tBIT(6)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_CAP\tBIT(7)\n+\tu8 type;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_READ_ONLY\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_GPS\t\tBIT(4)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_EXTERNAL\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_PHY\t\tBIT(6)\n+\tu8 flags1;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_1PPS_SUPP\t\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP\tBIT(3)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_ANYFREQ\t\tBIT(7)\n+\t__le32 freq;\n+\t__le32 phase_delay;\n+\tu8 flags2;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_INPUT_EN\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_ESYNC_EN\t\tBIT(6)\n+\tu8 rsvd[1];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_input_config);\n+\n+/* Set CGU output config (direct 0x0C64) */\n+struct ixgbe_aci_cmd_set_cgu_output_config {\n+\tu8 output_idx;\n+\tu8 flags;\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_OUT_EN\t\tBIT(0)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_ESYNC_EN\t\tBIT(1)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_FREQ\t\tBIT(2)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_PHASE\t\tBIT(3)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_SRC_SEL\tBIT(4)\n+\tu8 src_sel;\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_DPLL_SRC_SEL\t\tMAKEMASK(0x1F, 0)\n+\tu8 rsvd;\n+\t__le32 freq;\n+\t__le32 phase_delay;\n+\tu8 rsvd2[2];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_output_config);\n+\n+/* Get CGU output config (direct 0x0C65) */\n+struct ixgbe_aci_cmd_get_cgu_output_config {\n+\tu8 output_idx;\n+\tu8 flags;\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_OUT_EN\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_EN\t\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_ABILITY\t\tBIT(2)\n+\tu8 src_sel;\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT\t0\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL \\\n+\tMAKEMASK(0x1F, IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT\t5\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE \\\n+\tMAKEMASK(0x7, IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)\n+\tu8 rsvd;\n+\t__le32 freq;\n+\t__le32 src_freq;\n+\tu8 rsvd2[2];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_output_config);\n+\n+/* Get CGU DPLL status (direct 0x0C66) */\n+struct ixgbe_aci_cmd_get_cgu_dpll_status {\n+\tu8 dpll_num;\n+\tu8 ref_state;\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_LOS\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_SCM\t\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_CFM\t\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_GST\t\tBIT(3)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_PFM\t\tBIT(4)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_FAST_LOCK_EN\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_ESYNC\t\tBIT(6)\n+\t__le16 dpll_state;\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_LOCK\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO\t\t\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO_READY\t\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_FLHIT\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_PSLHIT\t\tBIT(7)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT\t8\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SEL\t\t\\\n+\tMAKEMASK(0x1F, IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT\t\t13\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE \t\t\\\n+\tMAKEMASK(0x7, IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT)\n+\t__le32 phase_offset_h;\n+\t__le32 phase_offset_l;\n+\tu8 eec_mode;\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_1\t\t0xA\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_2\t\t0xB\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN\t\t0xF\n+\tu8 rsvd[1];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_dpll_status);\n+\n+/* Set CGU DPLL config (direct 0x0C67) */\n+struct ixgbe_aci_cmd_set_cgu_dpll_config {\n+\tu8 dpll_num;\n+\tu8 ref_state;\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_LOS\tBIT(0)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_SCM\tBIT(1)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_CFM\tBIT(2)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_GST\tBIT(3)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_PFM\tBIT(4)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN\tBIT(5)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC\tBIT(6)\n+\tu8 rsvd;\n+\tu8 config;\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_CLK_REF_SEL\tMAKEMASK(0x1F, 0)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_MODE\t\tMAKEMASK(0x7, 5)\n+\tu8 rsvd2[8];\n+\tu8 eec_mode;\n+\tu8 rsvd3[1];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_dpll_config);\n+\n+/* Set CGU reference priority (direct 0x0C68) */\n+struct ixgbe_aci_cmd_set_cgu_ref_prio {\n+\tu8 dpll_num;\n+\tu8 ref_idx;\n+\tu8 ref_priority;\n+\tu8 rsvd[11];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_ref_prio);\n+\n+/* Get CGU reference priority (direct 0x0C69) */\n+struct ixgbe_aci_cmd_get_cgu_ref_prio {\n+\tu8 dpll_num;\n+\tu8 ref_idx;\n+\tu8 ref_priority; /* Valid only in response */\n+\tu8 rsvd[13];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_ref_prio);\n+\n+/* Get CGU info (direct 0x0C6A) */\n+struct ixgbe_aci_cmd_get_cgu_info {\n+\t__le32 cgu_id;\n+\t__le32 cgu_cfg_ver;\n+\t__le32 cgu_fw_ver;\n+\tu8 node_part_num;\n+\tu8 dev_rev;\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_info);\n+\n+/* Debug Dump Internal Data (indirect 0xFF08) */\n+struct ixgbe_aci_cmd_debug_dump_internals {\n+\t__le16 cluster_id; /* Expresses next cluster ID in response */\n+#define IXGBE_ACI_DBG_DUMP_CLUSTER_ID_LINK\t\t0\n+#define IXGBE_ACI_DBG_DUMP_CLUSTER_ID_FULL_CSR_SPACE\t1\n+\t__le16 table_id; /* Used only for non-memory clusters */\n+\t__le32 idx; /* In table entries for tables, in bytes for memory */\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_debug_dump_internals);\n+\n+/* Set Health Status (direct 0xFF20) */\n+struct ixgbe_aci_cmd_set_health_status_config {\n+\tu8 event_source;\n+#define IXGBE_ACI_HEALTH_STATUS_SET_PF_SPECIFIC_MASK\tBIT(0)\n+#define IXGBE_ACI_HEALTH_STATUS_SET_ALL_PF_MASK\t\tBIT(1)\n+#define IXGBE_ACI_HEALTH_STATUS_SET_GLOBAL_MASK\t\tBIT(2)\n+\tu8 reserved[15];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_health_status_config);\n+\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_UNKNOWN_MOD_STRICT\t\t0x101\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_TYPE\t\t\t0x102\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_QUAL\t\t\t0x103\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_COMM\t\t\t0x104\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_CONFLICT\t\t0x105\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_NOT_PRESENT\t\t0x106\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_MOD_UNDERUTILIZED\t\t0x107\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_UNKNOWN_MOD_LENIENT\t\t0x108\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MOD_DIAGNOSTIC_FEATURE\t0x109\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_INVALID_LINK_CFG\t\t0x10B\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PORT_ACCESS\t\t\t0x10C\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PORT_UNREACHABLE\t\t0x10D\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_PORT_SPEED_MOD_LIMITED\t0x10F\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PARALLEL_FAULT\t\t0x110\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_PORT_SPEED_PHY_LIMITED\t0x111\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NETLIST_TOPO\t\t0x112\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NETLIST\t\t\t0x113\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_TOPO_CONFLICT\t\t0x114\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LINK_HW_ACCESS\t\t0x115\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LINK_RUNTIME\t\t0x116\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_DNL_INIT\t\t\t0x117\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PHY_NVM_PROG\t\t0x120\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_PHY_FW_LOAD\t\t\t0x121\n+#define IXGBE_ACI_HEALTH_STATUS_INFO_RECOVERY\t\t\t0x500\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_FLASH_ACCESS\t\t0x501\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_AUTH\t\t\t0x502\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_AUTH\t\t\t0x503\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_DDP_AUTH\t\t\t0x504\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_COMPAT\t\t\t0x505\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_COMPAT\t\t\t0x506\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_NVM_SEC_VIOLATION\t\t0x507\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_OROM_SEC_VIOLATION\t\t0x508\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_DCB_MIB\t\t\t0x509\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_MNG_TIMEOUT\t\t\t0x50A\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_BMC_RESET\t\t\t0x50B\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LAST_MNG_FAIL\t\t0x50C\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_RESOURCE_ALLOC_FAIL\t\t0x50D\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_FW_LOOP\t\t\t0x1000\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_FW_PFR_FAIL\t\t\t0x1001\n+#define IXGBE_ACI_HEALTH_STATUS_ERR_LAST_FAIL_AQ\t\t0x1002\n+\n+/* Get Health Status codes (indirect 0xFF21) */\n+struct ixgbe_aci_cmd_get_supported_health_status_codes {\n+\t__le16 health_code_count;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_supported_health_status_codes);\n+\n+/* Get Health Status (indirect 0xFF22) */\n+struct ixgbe_aci_cmd_get_health_status {\n+\t__le16 health_status_count;\n+\tu8 reserved[6];\n+\t__le32 addr_high;\n+\t__le32 addr_low;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_health_status);\n+\n+/* Get Health Status event buffer entry, (0xFF22)\n+ * repeated per reported health status\n+ */\n+struct ixgbe_aci_cmd_health_status_elem {\n+\t__le16 health_status_code;\n+\t__le16 event_source;\n+#define IXGBE_ACI_HEALTH_STATUS_PF\t\t(0x1)\n+#define IXGBE_ACI_HEALTH_STATUS_PORT\t\t(0x2)\n+#define IXGBE_ACI_HEALTH_STATUS_GLOBAL\t\t(0x3)\n+\t__le32 internal_data1;\n+#define IXGBE_ACI_HEALTH_STATUS_UNDEFINED_DATA\t(0xDEADBEEF)\n+\t__le32 internal_data2;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(12, ixgbe_aci_cmd_health_status_elem);\n+\n+/* Clear Health Status (direct 0xFF23) */\n+struct ixgbe_aci_cmd_clear_health_status {\n+\t__le32 reserved[4];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_clear_health_status);\n+\n+/**\n+ * struct ixgbe_aq_desc - Admin Command (AC) descriptor\n+ * @flags: IXGBE_ACI_FLAG_* flags\n+ * @opcode: Admin command opcode\n+ * @datalen: length in bytes of indirect/external data buffer\n+ * @retval: return value from firmware\n+ * @cookie_high: opaque data high-half\n+ * @cookie_low: opaque data low-half\n+ * @params: command-specific parameters\n+ *\n+ * Descriptor format for commands the driver posts via the Admin Command Interface\n+ * (ACI). The firmware writes back onto the command descriptor and returns\n+ * the result of the command. Asynchronous events that are not an immediate\n+ * result of the command are written to the Admin Command Interface (ACI) using\n+ * the same descriptor format. Descriptors are in little-endian notation with\n+ * 32-bit words.\n+ */\n+struct ixgbe_aci_desc {\n+\t__le16 flags;\n+\t__le16 opcode;\n+\t__le16 datalen;\n+\t__le16 retval;\n+\t__le32 cookie_high;\n+\t__le32 cookie_low;\n+\tunion {\n+\t\tu8 raw[16];\n+\t\tstruct ixgbe_aci_cmd_generic generic;\n+\t\tstruct ixgbe_aci_cmd_get_ver get_ver;\n+\t\tstruct ixgbe_aci_cmd_driver_ver driver_ver;\n+\t\tstruct ixgbe_aci_cmd_get_exp_err exp_err;\n+\t\tstruct ixgbe_aci_cmd_req_res res_owner;\n+\t\tstruct ixgbe_aci_cmd_list_caps get_cap;\n+\t\tstruct ixgbe_aci_cmd_disable_rxen disable_rxen;\n+\t\tstruct ixgbe_aci_cmd_get_fw_event get_fw_event;\n+\t\tstruct ixgbe_aci_cmd_get_phy_caps get_phy;\n+\t\tstruct ixgbe_aci_cmd_set_phy_cfg set_phy;\n+\t\tstruct ixgbe_aci_cmd_restart_an restart_an;\n+\t\tstruct ixgbe_aci_cmd_get_link_status get_link_status;\n+\t\tstruct ixgbe_aci_cmd_set_event_mask set_event_mask;\n+\t\tstruct ixgbe_aci_cmd_get_link_topo get_link_topo;\n+\t\tstruct ixgbe_aci_cmd_get_link_topo_pin get_link_topo_pin;\n+\t\tstruct ixgbe_aci_cmd_i2c read_write_i2c;\n+\t\tstruct ixgbe_aci_cmd_read_i2c_resp read_i2c_resp;\n+\t\tstruct ixgbe_aci_cmd_mdio read_write_mdio;\n+\t\tstruct ixgbe_aci_cmd_mdio read_mdio;\n+\t\tstruct ixgbe_aci_cmd_mdio write_mdio;\n+\t\tstruct ixgbe_aci_cmd_gpio_by_func read_write_gpio_by_func;\n+\t\tstruct ixgbe_aci_cmd_gpio read_write_gpio;\n+\t\tstruct ixgbe_aci_cmd_sff_eeprom read_write_sff_param;\n+\t\tstruct ixgbe_aci_cmd_prog_topo_dev_nvm prog_topo_dev_nvm;\n+\t\tstruct ixgbe_aci_cmd_read_topo_dev_nvm read_topo_dev_nvm;\n+\t\tstruct ixgbe_aci_cmd_nvm nvm;\n+\t\tstruct ixgbe_aci_cmd_nvm_cfg nvm_cfg;\n+\t\tstruct ixgbe_aci_cmd_nvm_checksum nvm_checksum;\n+\t\tstruct ixgbe_aci_cmd_read_write_alt_direct read_write_alt_direct;\n+\t\tstruct ixgbe_aci_cmd_read_write_alt_indirect read_write_alt_indirect;\n+\t\tstruct ixgbe_aci_cmd_done_alt_write done_alt_write;\n+\t\tstruct ixgbe_aci_cmd_clear_port_alt_write clear_port_alt_write;\n+\t\tstruct ixgbe_aci_cmd_debug_dump_internals debug_dump;\n+\t\tstruct ixgbe_aci_cmd_set_health_status_config\n+\t\t\tset_health_status_config;\n+\t\tstruct ixgbe_aci_cmd_get_supported_health_status_codes\n+\t\t\tget_supported_health_status_codes;\n+\t\tstruct ixgbe_aci_cmd_get_health_status get_health_status;\n+\t\tstruct ixgbe_aci_cmd_clear_health_status clear_health_status;\n+\t\tstruct ixgbe_aci_cmd_nvm_sanitization nvm_sanitization;\n+\t} params;\n+};\n+\n+/* LKV-specific adapter context structures */\n+\n+struct ixgbe_link_status {\n+\t/* Refer to ixgbe_aci_phy_type for bits definition */\n+\tu64 phy_type_low;\n+\tu64 phy_type_high;\n+\tu8 topo_media_conflict;\n+\tu16 max_frame_size;\n+\tu16 link_speed;\n+\tu16 req_speeds;\n+\tu8 link_cfg_err;\n+\tu8 lse_ena;\t/* Link Status Event notification */\n+\tu8 link_info;\n+\tu8 an_info;\n+\tu8 ext_info;\n+\tu8 fec_info;\n+\tu8 pacing;\n+\t/* Refer to #define from module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE] of\n+\t * ixgbe_aci_get_phy_caps structure\n+\t */\n+\tu8 module_type[IXGBE_ACI_MODULE_TYPE_TOTAL_BYTE];\n+};\n+\n+/* Common HW capabilities for SW use */\n+struct ixgbe_hw_common_caps {\n+\t/* Write CSR protection */\n+\tu64 wr_csr_prot;\n+\tu32 switching_mode;\n+\t/* switching mode supported - EVB switching (including cloud) */\n+#define IXGBE_NVM_IMAGE_TYPE_EVB\t\t0x0\n+\n+\t/* Manageability mode & supported protocols over MCTP */\n+\tu32 mgmt_mode;\n+#define IXGBE_MGMT_MODE_PASS_THRU_MODE_M\t0xF\n+#define IXGBE_MGMT_MODE_CTL_INTERFACE_M\t\t0xF0\n+#define IXGBE_MGMT_MODE_REDIR_SB_INTERFACE_M\t0xF00\n+\n+\tu32 mgmt_protocols_mctp;\n+#define IXGBE_MGMT_MODE_PROTO_RSVD\tBIT(0)\n+#define IXGBE_MGMT_MODE_PROTO_PLDM\tBIT(1)\n+#define IXGBE_MGMT_MODE_PROTO_OEM\tBIT(2)\n+#define IXGBE_MGMT_MODE_PROTO_NC_SI\tBIT(3)\n+\n+\tu32 os2bmc;\n+\tu32 valid_functions;\n+\t/* DCB capabilities */\n+\tu32 active_tc_bitmap;\n+\tu32 maxtc;\n+\n+\t/* RSS related capabilities */\n+\tu32 rss_table_size;\t\t/* 512 for PFs and 64 for VFs */\n+\tu32 rss_table_entry_width;\t/* RSS Entry width in bits */\n+\n+\t/* Tx/Rx queues */\n+\tu32 num_rxq;\t\t\t/* Number/Total Rx queues */\n+\tu32 rxq_first_id;\t\t/* First queue ID for Rx queues */\n+\tu32 num_txq;\t\t\t/* Number/Total Tx queues */\n+\tu32 txq_first_id;\t\t/* First queue ID for Tx queues */\n+\n+\t/* MSI-X vectors */\n+\tu32 num_msix_vectors;\n+\tu32 msix_vector_first_id;\n+\n+\t/* Max MTU for function or device */\n+\tu32 max_mtu;\n+\n+\t/* WOL related */\n+\tu32 num_wol_proxy_fltr;\n+\tu32 wol_proxy_vsi_seid;\n+\n+\t/* LED/SDP pin count */\n+\tu32 led_pin_num;\n+\tu32 sdp_pin_num;\n+\n+\t/* LED/SDP - Supports up to 12 LED pins and 8 SDP signals */\n+#define IXGBE_MAX_SUPPORTED_GPIO_LED\t12\n+#define IXGBE_MAX_SUPPORTED_GPIO_SDP\t8\n+\tu8 led[IXGBE_MAX_SUPPORTED_GPIO_LED];\n+\tu8 sdp[IXGBE_MAX_SUPPORTED_GPIO_SDP];\n+\t/* VMDQ */\n+\tu8 vmdq;\t\t\t/* VMDQ supported */\n+\n+\t/* EVB capabilities */\n+\tu8 evb_802_1_qbg;\t\t/* Edge Virtual Bridging */\n+\tu8 evb_802_1_qbh;\t\t/* Bridge Port Extension */\n+\n+\tu8 dcb;\n+\tu8 iscsi;\n+\tu8 ieee_1588;\n+\tu8 mgmt_cem;\n+\n+\t/* WoL and APM support */\n+#define IXGBE_WOL_SUPPORT_M\t\tBIT(0)\n+#define IXGBE_ACPI_PROG_MTHD_M\t\tBIT(1)\n+#define IXGBE_PROXY_SUPPORT_M\t\tBIT(2)\n+\tu8 apm_wol_support;\n+\tu8 acpi_prog_mthd;\n+\tu8 proxy_support;\n+\tbool sec_rev_disabled;\n+\tbool update_disabled;\n+\tbool nvm_unified_update;\n+\tbool netlist_auth;\n+#define IXGBE_NVM_MGMT_SEC_REV_DISABLED\t\tBIT(0)\n+#define IXGBE_NVM_MGMT_UPDATE_DISABLED\t\tBIT(1)\n+#define IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT\tBIT(3)\n+#define IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT\tBIT(5)\n+\tbool no_drop_policy_support;\n+\t/* PCIe reset avoidance */\n+\tbool pcie_reset_avoidance; /* false: not supported, true: supported */\n+\t/* Post update reset restriction */\n+\tbool reset_restrict_support; /* false: not supported, true: supported */\n+\n+\t/* External topology device images within the NVM */\n+#define IXGBE_EXT_TOPO_DEV_IMG_COUNT\t4\n+\tu32 ext_topo_dev_img_ver_high[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+\tu32 ext_topo_dev_img_ver_low[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+\tu8 ext_topo_dev_img_part_num[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+#define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S\t8\n+#define IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M\t\\\n+\t\tMAKEMASK(0xFF, IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S)\n+\tbool ext_topo_dev_img_load_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+#define IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN\tBIT(0)\n+\tbool ext_topo_dev_img_prog_en[IXGBE_EXT_TOPO_DEV_IMG_COUNT];\n+#define IXGBE_EXT_TOPO_DEV_IMG_PROG_EN\tBIT(1)\n+\tbool next_cluster_id_support;\n+};\n+\n+/* IEEE 1588 TIME_SYNC specific info */\n+/* Function specific definitions */\n+#define IXGBE_TS_FUNC_ENA_M\t\tBIT(0)\n+#define IXGBE_TS_SRC_TMR_OWND_M\t\tBIT(1)\n+#define IXGBE_TS_TMR_ENA_M\t\tBIT(2)\n+#define IXGBE_TS_TMR_IDX_OWND_S\t\t4\n+#define IXGBE_TS_TMR_IDX_OWND_M\t\tBIT(4)\n+#define IXGBE_TS_CLK_FREQ_S\t\t16\n+#define IXGBE_TS_CLK_FREQ_M\t\tMAKEMASK(0x7, IXGBE_TS_CLK_FREQ_S)\n+#define IXGBE_TS_CLK_SRC_S\t\t20\n+#define IXGBE_TS_CLK_SRC_M\t\tBIT(20)\n+#define IXGBE_TS_TMR_IDX_ASSOC_S\t24\n+#define IXGBE_TS_TMR_IDX_ASSOC_M\tBIT(24)\n+\n+/* TIME_REF clock rate specification */\n+enum ixgbe_time_ref_freq {\n+\tIXGBE_TIME_REF_FREQ_25_000\t= 0,\n+\tIXGBE_TIME_REF_FREQ_122_880\t= 1,\n+\tIXGBE_TIME_REF_FREQ_125_000\t= 2,\n+\tIXGBE_TIME_REF_FREQ_153_600\t= 3,\n+\tIXGBE_TIME_REF_FREQ_156_250\t= 4,\n+\tIXGBE_TIME_REF_FREQ_245_760\t= 5,\n+\n+\tNUM_IXGBE_TIME_REF_FREQ\n+};\n+\n+struct ixgbe_ts_func_info {\n+\t/* Function specific info */\n+\tenum ixgbe_time_ref_freq time_ref;\n+\tu8 clk_freq;\n+\tu8 clk_src;\n+\tu8 tmr_index_assoc;\n+\tu8 ena;\n+\tu8 tmr_index_owned;\n+\tu8 src_tmr_owned;\n+\tu8 tmr_ena;\n+};\n+\n+/* Device specific definitions */\n+#define IXGBE_TS_TMR0_OWNR_M\t\t0x7\n+#define IXGBE_TS_TMR0_OWND_M\t\tBIT(3)\n+#define IXGBE_TS_TMR1_OWNR_S\t\t4\n+#define IXGBE_TS_TMR1_OWNR_M\t\tMAKEMASK(0x7, IXGBE_TS_TMR1_OWNR_S)\n+#define IXGBE_TS_TMR1_OWND_M\t\tBIT(7)\n+#define IXGBE_TS_DEV_ENA_M\t\tBIT(24)\n+#define IXGBE_TS_TMR0_ENA_M\t\tBIT(25)\n+#define IXGBE_TS_TMR1_ENA_M\t\tBIT(26)\n+\n+struct ixgbe_ts_dev_info {\n+\t/* Device specific info */\n+\tu32 ena_ports;\n+\tu32 tmr_own_map;\n+\tu32 tmr0_owner;\n+\tu32 tmr1_owner;\n+\tu8 tmr0_owned;\n+\tu8 tmr1_owned;\n+\tu8 ena;\n+\tu8 tmr0_ena;\n+\tu8 tmr1_ena;\n+};\n+\n+#pragma pack(1)\n+struct ixgbe_orom_civd_info {\n+\tu8 signature[4];\t/* Must match ASCII '$CIV' characters */\n+\tu8 checksum;\t\t/* Simple modulo 256 sum of all structure bytes must equal 0 */\n+\t__le32 combo_ver;\t/* Combo Image Version number */\n+\tu8 combo_name_len;\t/* Length of the unicode combo image version string, max of 32 */\n+\t__le16 combo_name[32];\t/* Unicode string representing the Combo Image version */\n+};\n+#pragma pack()\n+\n+/* Function specific capabilities */\n+struct ixgbe_hw_func_caps {\n+\tstruct ixgbe_hw_common_caps common_cap;\n+\tu32 guar_num_vsi;\n+\tstruct ixgbe_ts_func_info ts_func_info;\n+\tbool no_drop_policy_ena;\n+};\n+\n+/* Device wide capabilities */\n+struct ixgbe_hw_dev_caps {\n+\tstruct ixgbe_hw_common_caps common_cap;\n+\tu32 num_vsi_allocd_to_host;\t/* Excluding EMP VSI */\n+\tu32 num_flow_director_fltr;\t/* Number of FD filters available */\n+\tstruct ixgbe_ts_dev_info ts_dev_info;\n+\tu32 num_funcs;\n+};\n+\n+/* ACI event information */\n+struct ixgbe_aci_event {\n+\tstruct ixgbe_aci_desc desc;\n+\tu16 msg_len;\n+\tu16 buf_len;\n+\tu8 *msg_buf;\n+};\n+\n+struct ixgbe_aci_info {\n+\tenum ixgbe_aci_err last_status;\t/* last status of sent admin command */\n+\tstruct ixgbe_lock lock;\t\t/* admin command interface lock */\n+};\n+\n+/* Minimum Security Revision information */\n+struct ixgbe_minsrev_info {\n+\tu32 nvm;\n+\tu32 orom;\n+\tu8 nvm_valid : 1;\n+\tu8 orom_valid : 1;\n+};\n+\n+/* Enumeration of which flash bank is desired to read from, either the active\n+ * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from\n+ * code which just wants to read the active or inactive flash bank.\n+ */\n+enum ixgbe_bank_select {\n+\tIXGBE_ACTIVE_FLASH_BANK,\n+\tIXGBE_INACTIVE_FLASH_BANK,\n+};\n+\n+/* Option ROM version information */\n+struct ixgbe_orom_info {\n+\tu8 major;\t\t\t/* Major version of OROM */\n+\tu8 patch;\t\t\t/* Patch version of OROM */\n+\tu16 build;\t\t\t/* Build version of OROM */\n+\tu32 srev;\t\t\t/* Security revision */\n+};\n+\n+/* NVM version information */\n+struct ixgbe_nvm_info {\n+\tu32 eetrack;\n+\tu32 srev;\n+\tu8 major;\n+\tu8 minor;\n+};\n+\n+/* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules\n+ * of the flash image.\n+ */\n+enum ixgbe_flash_bank {\n+\tIXGBE_INVALID_FLASH_BANK,\n+\tIXGBE_1ST_FLASH_BANK,\n+\tIXGBE_2ND_FLASH_BANK,\n+};\n+\n+/* information for accessing NVM, OROM, and Netlist flash banks */\n+struct ixgbe_bank_info {\n+\tu32 nvm_ptr;\t\t\t\t/* Pointer to 1st NVM bank */\n+\tu32 nvm_size;\t\t\t\t/* Size of NVM bank */\n+\tu32 orom_ptr;\t\t\t\t/* Pointer to 1st OROM bank */\n+\tu32 orom_size;\t\t\t\t/* Size of OROM bank */\n+\tu32 netlist_ptr;\t\t\t/* Pointer to 1st Netlist bank */\n+\tu32 netlist_size;\t\t\t/* Size of Netlist bank */\n+\tenum ixgbe_flash_bank nvm_bank;\t\t/* Active NVM bank */\n+\tenum ixgbe_flash_bank orom_bank;\t/* Active OROM bank */\n+\tenum ixgbe_flash_bank netlist_bank;\t/* Active Netlist bank */\n+};\n+\n+/* Flash Chip Information */\n+struct ixgbe_flash_info {\n+\tstruct ixgbe_orom_info orom;\t\t/* Option ROM version info */\n+\tstruct ixgbe_nvm_info nvm;\t\t/* NVM version information */\n+\tstruct ixgbe_bank_info banks;\t\t/* Flash Bank information */\n+\tu16 sr_words;\t\t\t\t/* Shadow RAM size in words */\n+\tu32 flash_size;\t\t\t\t/* Size of available flash in bytes */\n+\tu8 blank_nvm_mode;\t\t\t/* is NVM empty (no FW present) */\n+};\n+\n+#define IXGBE_NVM_CMD_READ\t\t0x0000000B\n+#define IXGBE_NVM_CMD_WRITE\t\t0x0000000C\n+\n+/* NVM Access command */\n+struct ixgbe_nvm_access_cmd {\n+\tu32 command;\t\t/* NVM command: READ or WRITE */\n+\tu32 offset;\t\t\t/* Offset to read/write, in bytes */\n+\tu32 data_size;\t\t/* Size of data field, in bytes */\n+};\n+\n+/* NVM Access data */\n+struct ixgbe_nvm_access_data {\n+\tu32 regval;\t\t\t/* Storage for register value */\n+};\n+\n+#endif /* _IXGBE_TYPE_E610_H_ */\ndiff --git a/drivers/net/ixgbe/base/meson.build b/drivers/net/ixgbe/base/meson.build\nindex f6497014da..6d72c11504 100644\n--- a/drivers/net/ixgbe/base/meson.build\n+++ b/drivers/net/ixgbe/base/meson.build\n@@ -9,8 +9,10 @@ sources = [\n         'ixgbe_dcb_82598.c',\n         'ixgbe_dcb_82599.c',\n         'ixgbe_dcb.c',\n+        'ixgbe_e610.c',\n         'ixgbe_hv_vf.c',\n         'ixgbe_mbx.c',\n+        'ixgbe_osdep.c',\n         'ixgbe_phy.c',\n         'ixgbe_vf.c',\n         'ixgbe_x540.c',\n",
    "prefixes": [
        "v1",
        "22/22"
    ]
}