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GET /api/patches/139753/?format=api
{ "id": 139753, "url": "http://patchwork.dpdk.org/api/patches/139753/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240430202144.49899-8-andrew.boyer@amd.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240430202144.49899-8-andrew.boyer@amd.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240430202144.49899-8-andrew.boyer@amd.com", "date": "2024-04-30T20:21:42", "name": "[v2,7/9] crypto/ionic: add datapath", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c75d0f07b3c7d28efdd4869dedc854f3e38ed8f4", "submitter": { "id": 2861, "url": "http://patchwork.dpdk.org/api/people/2861/?format=api", "name": "Andrew Boyer", "email": "Andrew.Boyer@amd.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240430202144.49899-8-andrew.boyer@amd.com/mbox/", "series": [ { "id": 31850, "url": "http://patchwork.dpdk.org/api/series/31850/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31850", "date": "2024-04-30T20:21:35", "name": "crypto/ionic: introduce AMD Pensando ionic crypto driver", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31850/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139753/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/139753/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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"X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This defines the main crypto operation enqueue and dequeue handlers.\n\nSigned-off-by: Andrew Boyer <andrew.boyer@amd.com>\n---\n doc/guides/cryptodevs/features/ionic.ini | 8 +\n doc/guides/cryptodevs/ionic.rst | 11 +\n drivers/crypto/ionic/ionic_crypto.h | 17 ++\n drivers/crypto/ionic/ionic_crypto_caps.c | 30 +++\n drivers/crypto/ionic/ionic_crypto_main.c | 222 ++++++++++++++++-\n drivers/crypto/ionic/ionic_crypto_ops.c | 295 +++++++++++++++++++++++\n 6 files changed, 581 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/ionic.ini b/doc/guides/cryptodevs/features/ionic.ini\nindex 62b7e9e8f2..d3e00bd795 100644\n--- a/doc/guides/cryptodevs/features/ionic.ini\n+++ b/doc/guides/cryptodevs/features/ionic.ini\n@@ -4,6 +4,12 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Symmetric crypto = Y\n+HW Accelerated = Y\n+In Place SGL = Y\n+OOP SGL In LB Out = Y\n+OOP SGL In SGL Out = Y\n+OOP LB In LB Out = Y\n \n ;\n ; Supported crypto algorithms of 'ionic' crypto driver.\n@@ -19,6 +25,8 @@\n ; Supported AEAD algorithms of 'ionic' crypto driver.\n ;\n [AEAD]\n+AES GCM (128) = Y\n+AES GCM (256) = Y\n \n ;\n ; Supported Asymmetric algorithms of the 'ionic' crypto driver.\ndiff --git a/doc/guides/cryptodevs/ionic.rst b/doc/guides/cryptodevs/ionic.rst\nindex c9173deb2f..9d557f7cc2 100644\n--- a/doc/guides/cryptodevs/ionic.rst\n+++ b/doc/guides/cryptodevs/ionic.rst\n@@ -26,3 +26,14 @@ Runtime Configuration\n \n None\n \n+Features\n+--------\n+\n+The ionic crypto PMD has support for:\n+\n+Symmetric Crypto Algorithms\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+AEAD algorithms:\n+\n+* ``RTE_CRYPTO_AEAD_AES_GCM``\ndiff --git a/drivers/crypto/ionic/ionic_crypto.h b/drivers/crypto/ionic/ionic_crypto.h\nindex f50c4b4291..e05b458926 100644\n--- a/drivers/crypto/ionic/ionic_crypto.h\n+++ b/drivers/crypto/ionic/ionic_crypto.h\n@@ -27,6 +27,8 @@\n #define IOCPT_MIN_RING_DESC\t\t16\n #define IOCPT_ADMINQ_LENGTH\t\t16\t/* must be a power of two */\n \n+#define IOCPT_CRYPTOQ_WAIT\t\t10\t/* 1s */\n+\n extern int iocpt_logtype;\n #define RTE_LOGTYPE_IOCPT iocpt_logtype\n \n@@ -155,6 +157,14 @@ struct iocpt_admin_q {\n \tuint16_t flags;\n };\n \n+struct iocpt_crypto_q {\n+\t/* cacheline0, cacheline1 */\n+\tIOCPT_COMMON_FIELDS;\n+\n+\t/* cacheline2 */\n+\tuint16_t flags;\n+};\n+\n #define IOCPT_S_F_INITED\tBIT(0)\n \n struct iocpt_session_priv {\n@@ -212,6 +222,7 @@ struct iocpt_dev {\n \trte_spinlock_t adminq_service_lock;\n \n \tstruct iocpt_admin_q *adminq;\n+\tstruct iocpt_crypto_q **cryptoqs;\n \n \tstruct rte_bitmap *sess_bm;\t/* SET bit indicates index is free */\n \n@@ -259,6 +270,8 @@ int iocpt_remove(struct rte_device *rte_dev);\n \n void iocpt_configure(struct iocpt_dev *dev);\n int iocpt_assign_ops(struct rte_cryptodev *cdev);\n+int iocpt_start(struct iocpt_dev *dev);\n+void iocpt_stop(struct iocpt_dev *dev);\n void iocpt_deinit(struct iocpt_dev *dev);\n \n int iocpt_dev_identify(struct iocpt_dev *dev);\n@@ -268,6 +281,10 @@ void iocpt_dev_reset(struct iocpt_dev *dev);\n \n int iocpt_adminq_post_wait(struct iocpt_dev *dev, struct iocpt_admin_ctx *ctx);\n \n+int iocpt_cryptoq_alloc(struct iocpt_dev *dev, uint32_t socket_id,\n+\tuint32_t index, uint16_t ndescs);\n+void iocpt_cryptoq_free(struct iocpt_crypto_q *cptq);\n+\n int iocpt_session_init(struct iocpt_session_priv *priv);\n int iocpt_session_update(struct iocpt_session_priv *priv);\n void iocpt_session_deinit(struct iocpt_session_priv *priv);\ndiff --git a/drivers/crypto/ionic/ionic_crypto_caps.c b/drivers/crypto/ionic/ionic_crypto_caps.c\nindex c22681fabc..da5a69be3d 100644\n--- a/drivers/crypto/ionic/ionic_crypto_caps.c\n+++ b/drivers/crypto/ionic/ionic_crypto_caps.c\n@@ -7,6 +7,36 @@\n #include \"ionic_crypto.h\"\n \n static const struct rte_cryptodev_capabilities iocpt_sym_caps[] = {\n+\t{\t/* AES GCM */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_AEAD,\n+\t\t\t{.aead = {\n+\t\t\t\t.algo = RTE_CRYPTO_AEAD_AES_GCM,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 32,\n+\t\t\t\t\t.increment = 16\n+\t\t\t\t},\n+\t\t\t\t.digest_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.aad_size = {\n+\t\t\t\t\t.min = 0,\n+\t\t\t\t\t.max = 1024,\n+\t\t\t\t\t.increment = 1\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 12,\n+\t\t\t\t\t.max = 12,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t}\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n \tRTE_CRYPTODEV_END_OF_CAPABILITIES_LIST()\n };\n \ndiff --git a/drivers/crypto/ionic/ionic_crypto_main.c b/drivers/crypto/ionic/ionic_crypto_main.c\nindex cc893ad8e9..7693377831 100644\n--- a/drivers/crypto/ionic/ionic_crypto_main.c\n+++ b/drivers/crypto/ionic/ionic_crypto_main.c\n@@ -29,6 +29,15 @@ iocpt_cq_init(struct iocpt_cq *cq, uint16_t num_descs)\n \treturn 0;\n }\n \n+static void\n+iocpt_cq_reset(struct iocpt_cq *cq)\n+{\n+\tcq->tail_idx = 0;\n+\tcq->done_color = 1;\n+\n+\tmemset(cq->base, 0, sizeof(struct iocpt_nop_comp) * cq->num_descs);\n+}\n+\n static void\n iocpt_cq_map(struct iocpt_cq *cq, void *base, rte_iova_t base_pa)\n {\n@@ -89,6 +98,13 @@ iocpt_q_init(struct iocpt_queue *q, uint8_t type, uint32_t index,\n \treturn 0;\n }\n \n+static void\n+iocpt_q_reset(struct iocpt_queue *q)\n+{\n+\tq->head_idx = 0;\n+\tq->tail_idx = 0;\n+}\n+\n static void\n iocpt_q_map(struct iocpt_queue *q, void *base, rte_iova_t base_pa)\n {\n@@ -348,12 +364,154 @@ iocpt_commonq_alloc(struct iocpt_dev *dev,\n \treturn err;\n }\n \n+int\n+iocpt_cryptoq_alloc(struct iocpt_dev *dev, uint32_t socket_id, uint32_t index,\n+\t\tuint16_t num_descs)\n+{\n+\tstruct iocpt_crypto_q *cptq;\n+\tuint16_t flags = 0;\n+\tint err;\n+\n+\t/* CryptoQ always supports scatter-gather */\n+\tflags |= IOCPT_Q_F_SG;\n+\n+\tIOCPT_PRINT(DEBUG, \"cptq %u num_descs %u num_segs %u\",\n+\t\tindex, num_descs, 1);\n+\n+\terr = iocpt_commonq_alloc(dev,\n+\t\tIOCPT_QTYPE_CRYPTOQ,\n+\t\tsizeof(struct iocpt_crypto_q),\n+\t\tsocket_id,\n+\t\tindex,\n+\t\t\"crypto\",\n+\t\tflags,\n+\t\tnum_descs,\n+\t\t1,\n+\t\tsizeof(struct iocpt_crypto_desc),\n+\t\tsizeof(struct iocpt_crypto_comp),\n+\t\tsizeof(struct iocpt_crypto_sg_desc),\n+\t\t(struct iocpt_common_q **)&cptq);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\tcptq->flags = flags;\n+\n+\tdev->cryptoqs[index] = cptq;\n+\n+\treturn 0;\n+}\n+\n struct ionic_doorbell *\n iocpt_db_map(struct iocpt_dev *dev, struct iocpt_queue *q)\n {\n \treturn dev->db_pages + q->hw_type;\n }\n \n+static int\n+iocpt_cryptoq_init(struct iocpt_crypto_q *cptq)\n+{\n+\tstruct iocpt_queue *q = &cptq->q;\n+\tstruct iocpt_dev *dev = cptq->dev;\n+\tstruct iocpt_cq *cq = &cptq->cq;\n+\tstruct iocpt_admin_ctx ctx = {\n+\t\t.pending_work = true,\n+\t\t.cmd.q_init = {\n+\t\t\t.opcode = IOCPT_CMD_Q_INIT,\n+\t\t\t.type = IOCPT_QTYPE_CRYPTOQ,\n+\t\t\t.ver = dev->qtype_info[IOCPT_QTYPE_CRYPTOQ].version,\n+\t\t\t.index = rte_cpu_to_le_32(q->index),\n+\t\t\t.flags = rte_cpu_to_le_16(IOCPT_QINIT_F_ENA |\n+\t\t\t\t\t\tIOCPT_QINIT_F_SG),\n+\t\t\t.intr_index = rte_cpu_to_le_16(IONIC_INTR_NONE),\n+\t\t\t.ring_size = rte_log2_u32(q->num_descs),\n+\t\t\t.ring_base = rte_cpu_to_le_64(q->base_pa),\n+\t\t\t.cq_ring_base = rte_cpu_to_le_64(cq->base_pa),\n+\t\t\t.sg_ring_base = rte_cpu_to_le_64(q->sg_base_pa),\n+\t\t},\n+\t};\n+\tint err;\n+\n+\tIOCPT_PRINT(DEBUG, \"cptq_init.index %d\", q->index);\n+\tIOCPT_PRINT(DEBUG, \"cptq_init.ring_base %#jx\", q->base_pa);\n+\tIOCPT_PRINT(DEBUG, \"cptq_init.ring_size %d\",\n+\t\tctx.cmd.q_init.ring_size);\n+\tIOCPT_PRINT(DEBUG, \"cptq_init.ver %u\", ctx.cmd.q_init.ver);\n+\n+\tiocpt_q_reset(q);\n+\tiocpt_cq_reset(cq);\n+\n+\terr = iocpt_adminq_post_wait(dev, &ctx);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\tq->hw_type = ctx.comp.q_init.hw_type;\n+\tq->hw_index = rte_le_to_cpu_32(ctx.comp.q_init.hw_index);\n+\tq->db = iocpt_db_map(dev, q);\n+\n+\tIOCPT_PRINT(DEBUG, \"cptq->hw_type %d\", q->hw_type);\n+\tIOCPT_PRINT(DEBUG, \"cptq->hw_index %d\", q->hw_index);\n+\tIOCPT_PRINT(DEBUG, \"cptq->db %p\", q->db);\n+\n+\tcptq->flags |= IOCPT_Q_F_INITED;\n+\n+\treturn 0;\n+}\n+\n+static void\n+iocpt_cryptoq_deinit(struct iocpt_crypto_q *cptq)\n+{\n+\tstruct iocpt_dev *dev = cptq->dev;\n+\tstruct iocpt_admin_ctx ctx = {\n+\t\t.pending_work = true,\n+\t\t.cmd.q_control = {\n+\t\t\t.opcode = IOCPT_CMD_Q_CONTROL,\n+\t\t\t.type = IOCPT_QTYPE_CRYPTOQ,\n+\t\t\t.index = rte_cpu_to_le_32(cptq->q.index),\n+\t\t\t.oper = IOCPT_Q_DISABLE,\n+\t\t},\n+\t};\n+\tunsigned long sleep_usec = 100UL * 1000;\n+\tuint32_t sleep_cnt, sleep_max = IOCPT_CRYPTOQ_WAIT;\n+\tint err;\n+\n+\tfor (sleep_cnt = 0; sleep_cnt < sleep_max; sleep_cnt++) {\n+\t\tctx.pending_work = true;\n+\n+\t\terr = iocpt_adminq_post_wait(dev, &ctx);\n+\t\tif (err != -EAGAIN)\n+\t\t\tbreak;\n+\n+\t\trte_delay_us_block(sleep_usec);\n+\t}\n+\n+\tif (err != 0)\n+\t\tIOCPT_PRINT(ERR, \"Deinit queue %u returned %d after %u ms\",\n+\t\t\tcptq->q.index, err, sleep_cnt * 100);\n+\telse\n+\t\tIOCPT_PRINT(DEBUG, \"Deinit queue %u returned %d after %u ms\",\n+\t\t\tcptq->q.index, err, sleep_cnt * 100);\n+\n+\tcptq->flags &= ~IOCPT_Q_F_INITED;\n+}\n+\n+void\n+iocpt_cryptoq_free(struct iocpt_crypto_q *cptq)\n+{\n+\tif (cptq == NULL)\n+\t\treturn;\n+\n+\tif (cptq->base_z != NULL) {\n+\t\trte_memzone_free(cptq->base_z);\n+\t\tcptq->base_z = NULL;\n+\t\tcptq->base = NULL;\n+\t\tcptq->base_pa = 0;\n+\t}\n+\n+\tiocpt_q_free(&cptq->q);\n+\n+\trte_free(cptq);\n+}\n+\n static int\n iocpt_adminq_alloc(struct iocpt_dev *dev)\n {\n@@ -421,6 +579,14 @@ iocpt_alloc_objs(struct iocpt_dev *dev)\n \n \tIOCPT_PRINT(DEBUG, \"Crypto: %s\", dev->name);\n \n+\tdev->cryptoqs = rte_calloc_socket(\"iocpt\",\n+\t\t\t\tdev->max_qps, sizeof(*dev->cryptoqs),\n+\t\t\t\tRTE_CACHE_LINE_SIZE, dev->socket_id);\n+\tif (dev->cryptoqs == NULL) {\n+\t\tIOCPT_PRINT(ERR, \"Cannot allocate tx queues array\");\n+\t\treturn -ENOMEM;\n+\t}\n+\n \trte_spinlock_init(&dev->adminq_lock);\n \trte_spinlock_init(&dev->adminq_service_lock);\n \n@@ -428,7 +594,7 @@ iocpt_alloc_objs(struct iocpt_dev *dev)\n \tif (err != 0) {\n \t\tIOCPT_PRINT(ERR, \"Cannot allocate admin queue\");\n \t\terr = -ENOMEM;\n-\t\tgoto err_out;\n+\t\tgoto err_free_cryptoqs;\n \t}\n \n \tdev->info_sz = RTE_ALIGN(sizeof(*dev->info), rte_mem_page_size());\n@@ -473,7 +639,9 @@ iocpt_alloc_objs(struct iocpt_dev *dev)\n err_free_adminq:\n \tiocpt_adminq_free(dev->adminq);\n \tdev->adminq = NULL;\n-err_out:\n+err_free_cryptoqs:\n+\trte_free(dev->cryptoqs);\n+\tdev->cryptoqs = NULL;\n \treturn err;\n }\n \n@@ -502,6 +670,43 @@ iocpt_configure(struct iocpt_dev *dev)\n \tRTE_SET_USED(dev);\n }\n \n+int\n+iocpt_start(struct iocpt_dev *dev)\n+{\n+\tuint32_t i;\n+\tint err;\n+\n+\tIOCPT_PRINT(DEBUG, \"Starting %u queues\",\n+\t\tdev->crypto_dev->data->nb_queue_pairs);\n+\n+\tfor (i = 0; i < dev->crypto_dev->data->nb_queue_pairs; i++) {\n+\t\terr = iocpt_cryptoq_init(dev->cryptoqs[i]);\n+\t\tif (err != 0)\n+\t\t\treturn err;\n+\t}\n+\n+\tdev->state |= IOCPT_DEV_F_UP;\n+\n+\treturn 0;\n+}\n+\n+void\n+iocpt_stop(struct iocpt_dev *dev)\n+{\n+\tuint32_t i;\n+\n+\tIOCPT_PRINT_CALL();\n+\n+\tdev->state &= ~IOCPT_DEV_F_UP;\n+\n+\tfor (i = 0; i < dev->crypto_dev->data->nb_queue_pairs; i++) {\n+\t\tstruct iocpt_crypto_q *cptq = dev->cryptoqs[i];\n+\n+\t\tif (cptq->flags & IOCPT_Q_F_INITED)\n+\t\t\t(void)iocpt_cryptoq_deinit(cptq);\n+\t}\n+}\n+\n void\n iocpt_deinit(struct iocpt_dev *dev)\n {\n@@ -518,8 +723,16 @@ iocpt_deinit(struct iocpt_dev *dev)\n static void\n iocpt_free_objs(struct iocpt_dev *dev)\n {\n+\tvoid **queue_pairs = dev->crypto_dev->data->queue_pairs;\n+\tuint32_t i;\n+\n \tIOCPT_PRINT_CALL();\n \n+\tfor (i = 0; i < dev->crypto_dev->data->nb_queue_pairs; i++) {\n+\t\tiocpt_cryptoq_free(queue_pairs[i]);\n+\t\tqueue_pairs[i] = NULL;\n+\t}\n+\n \tif (dev->sess_bm != NULL) {\n \t\trte_bitmap_free(dev->sess_bm);\n \t\trte_free(dev->sess_bm);\n@@ -531,6 +744,11 @@ iocpt_free_objs(struct iocpt_dev *dev)\n \t\tdev->adminq = NULL;\n \t}\n \n+\tif (dev->cryptoqs != NULL) {\n+\t\trte_free(dev->cryptoqs);\n+\t\tdev->cryptoqs = NULL;\n+\t}\n+\n \tif (dev->info != NULL) {\n \t\trte_memzone_free(dev->info_z);\n \t\tdev->info_z = NULL;\ndiff --git a/drivers/crypto/ionic/ionic_crypto_ops.c b/drivers/crypto/ionic/ionic_crypto_ops.c\nindex e6b3402b63..28b099dea2 100644\n--- a/drivers/crypto/ionic/ionic_crypto_ops.c\n+++ b/drivers/crypto/ionic/ionic_crypto_ops.c\n@@ -21,6 +21,22 @@ iocpt_op_config(struct rte_cryptodev *cdev,\n \treturn 0;\n }\n \n+static int\n+iocpt_op_start(struct rte_cryptodev *cdev)\n+{\n+\tstruct iocpt_dev *dev = cdev->data->dev_private;\n+\n+\treturn iocpt_start(dev);\n+}\n+\n+static void\n+iocpt_op_stop(struct rte_cryptodev *cdev)\n+{\n+\tstruct iocpt_dev *dev = cdev->data->dev_private;\n+\n+\treturn iocpt_stop(dev);\n+}\n+\n static int\n iocpt_op_close(struct rte_cryptodev *cdev)\n {\n@@ -48,6 +64,53 @@ iocpt_op_info_get(struct rte_cryptodev *cdev, struct rte_cryptodev_info *info)\n \tinfo->min_mbuf_tailroom_req = 0;\n }\n \n+static int\n+iocpt_op_queue_release(struct rte_cryptodev *cdev, uint16_t queue_id)\n+{\n+\tstruct iocpt_crypto_q *cptq = cdev->data->queue_pairs[queue_id];\n+\n+\tIOCPT_PRINT(DEBUG, \"queue_id %u\", queue_id);\n+\n+\tassert(!(cptq->flags & IOCPT_Q_F_INITED));\n+\n+\tiocpt_cryptoq_free(cptq);\n+\n+\tcdev->data->queue_pairs[queue_id] = NULL;\n+\n+\treturn 0;\n+}\n+\n+static int\n+iocpt_op_queue_setup(struct rte_cryptodev *cdev, uint16_t queue_id,\n+\t\tconst struct rte_cryptodev_qp_conf *qp_conf,\n+\t\tint socket_id)\n+{\n+\tstruct iocpt_dev *dev = cdev->data->dev_private;\n+\tint err;\n+\n+\tif (cdev->data->queue_pairs[queue_id] != NULL)\n+\t\tiocpt_op_queue_release(cdev, queue_id);\n+\n+\tif (qp_conf->nb_descriptors < (1 << IOCPT_QSIZE_MIN_LG2) ||\n+\t qp_conf->nb_descriptors > (1 << IOCPT_QSIZE_MAX_LG2)) {\n+\t\tIOCPT_PRINT(ERR, \"invalid nb_descriptors %u, use range %u..%u\",\n+\t\t\tqp_conf->nb_descriptors,\n+\t\t\t1 << IOCPT_QSIZE_MIN_LG2, 1 << IOCPT_QSIZE_MAX_LG2);\n+\t\treturn -ERANGE;\n+\t}\n+\n+\tIOCPT_PRINT(DEBUG, \"queue_id %u\", queue_id);\n+\n+\terr = iocpt_cryptoq_alloc(dev, socket_id, queue_id,\n+\t\t\t\tqp_conf->nb_descriptors);\n+\tif (err != 0)\n+\t\treturn err;\n+\n+\tcdev->data->queue_pairs[queue_id] = dev->cryptoqs[queue_id];\n+\n+\treturn 0;\n+}\n+\n static unsigned int\n iocpt_op_get_session_size(struct rte_cryptodev *cdev __rte_unused)\n {\n@@ -167,11 +230,238 @@ iocpt_op_session_clear(struct rte_cryptodev *cdev __rte_unused,\n \tiocpt_session_clear(sess);\n }\n \n+static inline void\n+iocpt_fill_sge(struct iocpt_crypto_sg_elem *arr, uint8_t idx,\n+\t\tuint64_t addr, uint16_t len)\n+{\n+\tarr[idx].addr = rte_cpu_to_le_64(addr);\n+\tarr[idx].len = rte_cpu_to_le_16(len);\n+}\n+\n+static __rte_always_inline int\n+iocpt_enq_one_aead(struct iocpt_crypto_q *cptq,\n+\t\tstruct iocpt_session_priv *priv, struct rte_crypto_op *op)\n+{\n+\tstruct rte_crypto_sym_op *sym_op = op->sym;\n+\tstruct iocpt_queue *q = &cptq->q;\n+\tstruct iocpt_crypto_desc *desc, *desc_base = q->base;\n+\tstruct iocpt_crypto_sg_desc *sg_desc, *sg_desc_base = q->sg_base;\n+\tstruct iocpt_crypto_sg_elem *src, *dst;\n+\trte_iova_t aad_addr, digest_addr, iv_addr, seg_addr;\n+\tuint32_t data_len, data_offset, seg_len;\n+\tuint8_t nsge_src = 0, nsge_dst = 0, flags = 0;\n+\tstruct rte_mbuf *m;\n+\n+\tdesc = &desc_base[q->head_idx];\n+\tsg_desc = &sg_desc_base[q->head_idx];\n+\tsrc = sg_desc->src_elems;\n+\tdst = sg_desc->dst_elems;\n+\n+\t/* Fill the first SGE with the IV / Nonce */\n+\tiv_addr = rte_crypto_op_ctophys_offset(op, priv->iv_offset);\n+\tiocpt_fill_sge(src, nsge_src++, iv_addr, priv->iv_length);\n+\n+\t/* Fill the second SGE with the AAD, if applicable */\n+\tif (priv->aad_length > 0) {\n+\t\taad_addr = sym_op->aead.aad.phys_addr;\n+\t\tiocpt_fill_sge(src, nsge_src++, aad_addr, priv->aad_length);\n+\t\tflags |= IOCPT_DESC_F_AAD_VALID;\n+\t}\n+\n+\tm = sym_op->m_src;\n+\tdata_len = sym_op->aead.data.length;\n+\n+\t/* Fast-forward through mbuf chain to account for data offset */\n+\tdata_offset = sym_op->aead.data.offset;\n+\twhile (m != NULL && data_offset >= m->data_len) {\n+\t\tdata_offset -= m->data_len;\n+\t\tm = m->next;\n+\t}\n+\n+\t/* Fill the next SGEs with the payload segments */\n+\twhile (m != NULL && data_len > 0) {\n+\t\tseg_addr = rte_mbuf_data_iova(m) + data_offset;\n+\t\tseg_len = RTE_MIN(m->data_len - data_offset, data_len);\n+\t\tdata_offset = 0;\n+\t\tdata_len -= seg_len;\n+\n+\t\t/* Use -1 to save room for digest */\n+\t\tif (nsge_src >= IOCPT_CRYPTO_MAX_SG_ELEMS - 1)\n+\t\t\treturn -ERANGE;\n+\n+\t\tiocpt_fill_sge(src, nsge_src++, seg_addr, seg_len);\n+\n+\t\tm = m->next;\n+\t}\n+\n+\t/* AEAD AES-GCM: digest == authentication tag */\n+\tdigest_addr = sym_op->aead.digest.phys_addr;\n+\tiocpt_fill_sge(src, nsge_src++, digest_addr, priv->digest_length);\n+\n+\t/* Process Out-Of-Place destination SGL */\n+\tif (sym_op->m_dst != NULL) {\n+\t\t/* Put the AAD here, too */\n+\t\tif (priv->aad_length > 0)\n+\t\t\tiocpt_fill_sge(dst, nsge_dst++,\n+\t\t\t\tsym_op->aead.aad.phys_addr, priv->aad_length);\n+\n+\t\tm = sym_op->m_dst;\n+\t\tdata_len = sym_op->aead.data.length;\n+\n+\t\t/* Fast-forward through chain to account for data offset */\n+\t\tdata_offset = sym_op->aead.data.offset;\n+\t\twhile (m != NULL && data_offset >= m->data_len) {\n+\t\t\tdata_offset -= m->data_len;\n+\t\t\tm = m->next;\n+\t\t}\n+\n+\t\t/* Fill in the SGEs with the payload segments */\n+\t\twhile (m != NULL && data_len > 0) {\n+\t\t\tseg_addr = rte_mbuf_data_iova(m) + data_offset;\n+\t\t\tseg_len = RTE_MIN(m->data_len - data_offset, data_len);\n+\t\t\tdata_offset = 0;\n+\t\t\tdata_len -= seg_len;\n+\n+\t\t\tif (nsge_dst >= IOCPT_CRYPTO_MAX_SG_ELEMS)\n+\t\t\t\treturn -ERANGE;\n+\n+\t\t\tiocpt_fill_sge(dst, nsge_dst++, seg_addr, seg_len);\n+\n+\t\t\tm = m->next;\n+\t\t}\n+\t}\n+\n+\tdesc->opcode = priv->op;\n+\tdesc->flags = flags;\n+\tdesc->num_src_dst_sgs = iocpt_encode_nsge_src_dst(nsge_src, nsge_dst);\n+\tdesc->session_tag = rte_cpu_to_le_32(priv->index);\n+\n+\top->status = RTE_CRYPTO_OP_STATUS_NOT_PROCESSED;\n+\tq->info[q->head_idx] = op;\n+\tq->head_idx = Q_NEXT_TO_POST(q, 1);\n+\n+\treturn 0;\n+}\n+\n+static uint16_t\n+iocpt_enqueue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tstruct iocpt_crypto_q *cptq = qp;\n+\tstruct rte_crypto_op *op;\n+\tstruct iocpt_session_priv *priv;\n+\tuint16_t avail, count;\n+\tint err;\n+\n+\tavail = iocpt_q_space_avail(&cptq->q);\n+\tif (unlikely(nb_ops > avail))\n+\t\tnb_ops = avail;\n+\n+\tcount = 0;\n+\twhile (likely(count < nb_ops)) {\n+\t\top = ops[count];\n+\n+\t\tif (unlikely(op->sess_type != RTE_CRYPTO_OP_WITH_SESSION)) {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tpriv = CRYPTODEV_GET_SYM_SESS_PRIV(op->sym->session);\n+\t\tif (unlikely(priv == NULL)) {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\terr = iocpt_enq_one_aead(cptq, priv, op);\n+\t\tif (unlikely(err != 0)) {\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tcount++;\n+\t}\n+\n+\tif (likely(count > 0))\n+\t\tiocpt_q_flush(&cptq->q);\n+\n+\treturn count;\n+}\n+\n+static uint16_t\n+iocpt_dequeue_sym(void *qp, struct rte_crypto_op **ops, uint16_t nb_ops)\n+{\n+\tstruct iocpt_crypto_q *cptq = qp;\n+\tstruct iocpt_queue *q = &cptq->q;\n+\tstruct iocpt_cq *cq = &cptq->cq;\n+\tstruct rte_crypto_op *op;\n+\tstruct iocpt_crypto_comp *cq_desc_base = cq->base;\n+\tvolatile struct iocpt_crypto_comp *cq_desc;\n+\tuint16_t count = 0;\n+\n+\tcq_desc = &cq_desc_base[cq->tail_idx];\n+\n+\t/* First walk the CQ to update any completed op's status\n+\t * NB: These can arrive out of order!\n+\t */\n+\twhile ((cq_desc->color & 0x1) == cq->done_color) {\n+\t\tcq->tail_idx = Q_NEXT_TO_SRVC(cq, 1);\n+\t\tif (unlikely(cq->tail_idx == 0))\n+\t\t\tcq->done_color = !cq->done_color;\n+\n+\t\top = q->info[rte_le_to_cpu_16(cq_desc->comp_index)];\n+\n+\t\t/* Process returned CQ descriptor status */\n+\t\tif (unlikely(cq_desc->status)) {\n+\t\t\tswitch (cq_desc->status) {\n+\t\t\tcase IOCPT_COMP_SYMM_AUTH_VERIFY_ERROR:\n+\t\t\t\top->status = RTE_CRYPTO_OP_STATUS_AUTH_FAILED;\n+\t\t\t\tbreak;\n+\t\t\tcase IOCPT_COMP_INVAL_OPCODE_ERROR:\n+\t\t\tcase IOCPT_COMP_UNSUPP_OPCODE_ERROR:\n+\t\t\tcase IOCPT_COMP_SYMM_SRC_SG_ERROR:\n+\t\t\tcase IOCPT_COMP_SYMM_DST_SG_ERROR:\n+\t\t\tcase IOCPT_COMP_SYMM_SRC_DST_LEN_MISMATCH:\n+\t\t\tcase IOCPT_COMP_SYMM_KEY_IDX_ERROR:\n+\t\t\t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n+\t\t\t\tbreak;\n+\t\t\tdefault:\n+\t\t\t\top->status = RTE_CRYPTO_OP_STATUS_ERROR;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t} else\n+\t\t\top->status = RTE_CRYPTO_OP_STATUS_SUCCESS;\n+\n+\t\tcq_desc = &cq_desc_base[cq->tail_idx];\n+\t}\n+\n+\t/* Next walk the SQ to pop off completed ops in-order */\n+\twhile (count < nb_ops) {\n+\t\top = q->info[q->tail_idx];\n+\n+\t\t/* No more completions */\n+\t\tif (op == NULL ||\n+\t\t op->status == RTE_CRYPTO_OP_STATUS_NOT_PROCESSED)\n+\t\t\tbreak;\n+\n+\t\tops[count] = op;\n+\t\tq->info[q->tail_idx] = NULL;\n+\n+\t\tq->tail_idx = Q_NEXT_TO_SRVC(q, 1);\n+\t\tcount++;\n+\t}\n+\n+\treturn count;\n+}\n+\n static struct rte_cryptodev_ops iocpt_ops = {\n \t.dev_configure = iocpt_op_config,\n+\t.dev_start = iocpt_op_start,\n+\t.dev_stop = iocpt_op_stop,\n \t.dev_close = iocpt_op_close,\n \t.dev_infos_get = iocpt_op_info_get,\n \n+\t.queue_pair_setup = iocpt_op_queue_setup,\n+\t.queue_pair_release = iocpt_op_queue_release,\n+\n \t.sym_session_get_size = iocpt_op_get_session_size,\n \t.sym_session_configure = iocpt_op_session_cfg,\n \t.sym_session_clear = iocpt_op_session_clear,\n@@ -185,5 +475,10 @@ iocpt_assign_ops(struct rte_cryptodev *cdev)\n \tcdev->dev_ops = &iocpt_ops;\n \tcdev->feature_flags = dev->features;\n \n+\tif (dev->features & RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO) {\n+\t\tcdev->enqueue_burst = iocpt_enqueue_sym;\n+\t\tcdev->dequeue_burst = iocpt_dequeue_sym;\n+\t}\n+\n \treturn 0;\n }\n", "prefixes": [ "v2", "7/9" ] }