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GET /api/patches/139774/?format=api
{ "id": 139774, "url": "http://patchwork.dpdk.org/api/patches/139774/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240501175100.1192839-2-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240501175100.1192839-2-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240501175100.1192839-2-abdullah.sevincer@intel.com", "date": "2024-05-01T17:50:58", "name": "[v1,1/3] event/dlb2: add support for HW delayed token", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "a0e3793c9f98dfae8f4399978c4e1da177b2b7a8", "submitter": { "id": 2843, "url": "http://patchwork.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240501175100.1192839-2-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 31858, "url": "http://patchwork.dpdk.org/api/series/31858/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31858", "date": "2024-05-01T17:50:57", "name": "*** DLB2 Enhancements ***", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31858/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139774/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/139774/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 56BB443F5D;\n\tWed, 1 May 2024 19:51:12 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 55EC0402C5;\n\tWed, 1 May 2024 19:51:08 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.7])\n by mails.dpdk.org (Postfix) with ESMTP id 954DE4021E\n for <dev@dpdk.org>; Wed, 1 May 2024 19:51:05 +0200 (CEST)", "from orviesa005.jf.intel.com ([10.64.159.145])\n by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 May 2024 10:51:05 -0700", "from txanpdk02.an.intel.com ([10.123.117.76])\n by orviesa005.jf.intel.com with ESMTP; 01 May 2024 10:51:05 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714585866; x=1746121866;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=4MR65LkYxR58s+TQ+nYc7+cV1JLpSuum3vVHtrnKJiA=;\n b=N3HuEvAemuRL9Ec1s+XEJXrNq/b/e5sIjPgN1grDHUp0JnStYeImNc3k\n 2waU+LZFaM2TjJZVYtyaOQvX5e5vFO0M2R/CfB9ArtnaDcjVwxAM7hkot\n odH8mgJXfaqqwWIisAchPNOutdkeGqHFt52LhTxjHLc4LMqBRkPQhwVQL\n LVwLQwxdoSYhTrRtcbGXHpvSG6/O6v4AGbTmbQoFueS/FMhZy45jfZpEB\n F0IAcFLPCpbS9U+4sq6D1NNXnIgZ7bQvRgPV0brNFdmHuPo3Ia/68WBb3\n 6OuWkLdv/ct3jQkPw7YtChumjHK/RktniaIKnt7nUyfjHBM2lImjy2iNg g==;", "X-CSE-ConnectionGUID": [ "kI/gje6+Ra+L+p+CbSV35A==", "zi2wOWEDRquaxHvkJxYnuA==" ], "X-CSE-MsgGUID": [ "5Mid9PTqRfKyQ/SgN5HMqg==", "KG4MVYzQTw2Zb5qmEjep4A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11061\"; a=\"35714478\"", "E=Sophos;i=\"6.07,246,1708416000\"; d=\"scan'208\";a=\"35714478\"", "E=Sophos;i=\"6.07,246,1708416000\"; d=\"scan'208\";a=\"31662324\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, mike.ximing.chen@intel.com,\n tirthendu.sarkar@intel.com,\n pravin.pathak@intel.com, shivani.doneria@intel.com,\n Abdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v1 1/3] event/dlb2: add support for HW delayed token", "Date": "Wed, 1 May 2024 12:50:58 -0500", "Message-Id": "<20240501175100.1192839-2-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240501175100.1192839-1-abdullah.sevincer@intel.com>", "References": "<20240501175100.1192839-1-abdullah.sevincer@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "In DLB 2.5, hardware assist is available, complementing the Delayed\ntoken POP software implementation. When it is enabled, the feature\nworks as follows:\n\nIt stops CQ scheduling when the inflight limit associated with the CQ\nis reached. So the feature is activated only if the core is\ncongested. If the core can handle multiple atomic flows, DLB will not\ntry to switch them. This is an improvement over SW implementation\nwhich always switches the flows.\n\nThe feature will resume CQ scheduling when the number of pending\ncompletions fall below a configured threshold. To emulate older 2.0\nbehavior, this threshold is set to 1 by old APIs. SW sets CQ to\nauto-pop mode for token return, as tokens withholding is not\nnecessary now. As HW counts completions and not tokens, events equal\nto HL (History List) entries will be scheduled to DLB before the\nfeature activates and stops CQ scheduling.\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n drivers/event/dlb2/dlb2.c | 58 ++++++++++++-\n drivers/event/dlb2/dlb2_iface.c | 3 +\n drivers/event/dlb2/dlb2_iface.h | 4 +-\n drivers/event/dlb2/dlb2_priv.h | 5 ++\n drivers/event/dlb2/dlb2_user.h | 24 ++++++\n drivers/event/dlb2/pf/base/dlb2_regs.h | 9 ++\n drivers/event/dlb2/pf/base/dlb2_resource.c | 95 +++++++++++++++++++++-\n drivers/event/dlb2/pf/base/dlb2_resource.h | 19 +++++\n drivers/event/dlb2/pf/dlb2_pf.c | 21 +++++\n drivers/event/dlb2/rte_pmd_dlb2.c | 29 +++++++\n drivers/event/dlb2/rte_pmd_dlb2.h | 40 +++++++++\n drivers/event/dlb2/version.map | 3 +\n 12 files changed, 306 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 628ddef649..f0faf054b1 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -879,8 +879,11 @@ dlb2_hw_reset_sched_domain(const struct rte_eventdev *dev, bool reconfig)\n \tdlb2_iface_domain_reset(dlb2);\n \n \t/* Free all dynamically allocated port memory */\n-\tfor (i = 0; i < dlb2->num_ports; i++)\n+\tfor (i = 0; i < dlb2->num_ports; i++) {\n \t\tdlb2_free_qe_mem(&dlb2->ev_ports[i].qm_port);\n+\t\tif (!reconfig)\n+\t\t\tmemset(&dlb2->ev_ports[i], 0, sizeof(struct dlb2_eventdev_port));\n+\t}\n \n \t/* If reconfiguring, mark the device's queues and ports as \"previously\n \t * configured.\" If the user doesn't reconfigure them, the PMD will\n@@ -1525,7 +1528,7 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \tstruct dlb2_hw_dev *handle = &dlb2->qm_instance;\n \tstruct dlb2_create_ldb_port_args cfg = { {0} };\n \tint ret;\n-\tstruct dlb2_port *qm_port = NULL;\n+\tstruct dlb2_port *qm_port = &ev_port->qm_port;\n \tchar mz_name[RTE_MEMZONE_NAMESIZE];\n \tuint32_t qm_port_id;\n \tuint16_t ldb_credit_high_watermark = 0;\n@@ -1554,6 +1557,11 @@ dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,\n \tcfg.cq_depth = rte_align32pow2(dequeue_depth);\n \tcfg.cq_depth_threshold = 1;\n \n+\tif (dlb2->version == DLB2_HW_V2_5 && qm_port->enable_inflight_ctrl) {\n+\t\tcfg.enable_inflight_ctrl = 1;\n+\t\tcfg.inflight_threshold = qm_port->inflight_threshold;\n+\t}\n+\n \tcfg.cq_history_list_size = cfg.cq_depth;\n \n \tcfg.cos_id = ev_port->cos_id;\n@@ -4321,6 +4329,52 @@ dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,\n \t\treturn dlb2_get_ldb_queue_depth(dlb2, queue);\n }\n \n+int\n+dlb2_set_port_param(struct dlb2_eventdev *dlb2,\n+\t\t int port_id,\n+\t\t uint64_t param_flags,\n+\t\t void *param_val)\n+{\n+\tstruct dlb2_port_param *port_param = (struct dlb2_port_param *)param_val;\n+\tstruct dlb2_port *port = &dlb2->ev_ports[port_id].qm_port;\n+\tstruct dlb2_hw_dev *handle = &dlb2->qm_instance;\n+\tint ret = 0, bit = 0;\n+\n+\twhile (param_flags) {\n+\t\tuint64_t param = rte_bit_relaxed_test_and_clear64(bit++, ¶m_flags);\n+\n+\t\tif (!param)\n+\t\t\tcontinue;\n+\t\tswitch (param) {\n+\t\tcase DLB2_FLOW_MIGRATION_THRESHOLD:\n+\t\t\tif (dlb2->version == DLB2_HW_V2_5) {\n+\t\t\t\tstruct dlb2_cq_inflight_ctrl_args args = {0};\n+\t\t\t\targs.enable = true;\n+\t\t\t\targs.port_id = port->id;\n+\t\t\t\targs.threshold = port_param->inflight_threshold;\n+\n+\t\t\t\tif (dlb2->ev_ports[port_id].setup_done)\n+\t\t\t\t\tret = dlb2_iface_set_cq_inflight_ctrl(handle, &args);\n+\t\t\t\tif (ret < 0) {\n+\t\t\t\t\tDLB2_LOG_ERR(\"dlb2: can not set port parameters\\n\");\n+\t\t\t\t\treturn -EINVAL;\n+\t\t\t\t}\n+\t\t\t\tport->enable_inflight_ctrl = true;\n+\t\t\t\tport->inflight_threshold = args.threshold;\n+\t\t\t} else {\n+\t\t\t\tDLB2_LOG_ERR(\"dlb2: FLOW_MIGRATION_THRESHOLD is only supported for 2.5 HW\\n\");\n+\t\t\t\treturn -EINVAL;\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDLB2_LOG_ERR(\"dlb2: Unsupported flag\\n\");\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n static bool\n dlb2_queue_is_empty(struct dlb2_eventdev *dlb2,\n \t\t struct dlb2_eventdev_queue *queue)\ndiff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb2/dlb2_iface.c\nindex 100db434d0..b829da2454 100644\n--- a/drivers/event/dlb2/dlb2_iface.c\n+++ b/drivers/event/dlb2/dlb2_iface.c\n@@ -77,5 +77,8 @@ int (*dlb2_iface_get_dir_queue_depth)(struct dlb2_hw_dev *handle,\n int (*dlb2_iface_enable_cq_weight)(struct dlb2_hw_dev *handle,\n \t\t\t\t struct dlb2_enable_cq_weight_args *args);\n \n+int (*dlb2_iface_set_cq_inflight_ctrl)(struct dlb2_hw_dev *handle,\n+\t\t\t\t struct dlb2_cq_inflight_ctrl_args *args);\n+\n int (*dlb2_iface_set_cos_bw)(struct dlb2_hw_dev *handle,\n \t\t\t struct dlb2_set_cos_bw_args *args);\ndiff --git a/drivers/event/dlb2/dlb2_iface.h b/drivers/event/dlb2/dlb2_iface.h\nindex dc0c446ce8..55b6bdcf84 100644\n--- a/drivers/event/dlb2/dlb2_iface.h\n+++ b/drivers/event/dlb2/dlb2_iface.h\n@@ -72,10 +72,12 @@ extern int (*dlb2_iface_get_ldb_queue_depth)(struct dlb2_hw_dev *handle,\n extern int (*dlb2_iface_get_dir_queue_depth)(struct dlb2_hw_dev *handle,\n \t\t\t\tstruct dlb2_get_dir_queue_depth_args *args);\n \n-\n extern int (*dlb2_iface_enable_cq_weight)(struct dlb2_hw_dev *handle,\n \t\t\t\t\t struct dlb2_enable_cq_weight_args *args);\n \n+extern int (*dlb2_iface_set_cq_inflight_ctrl)(struct dlb2_hw_dev *handle,\n+\t\t\t\t\t struct dlb2_cq_inflight_ctrl_args *args);\n+\n extern int (*dlb2_iface_set_cos_bw)(struct dlb2_hw_dev *handle,\n \t\t\t\t struct dlb2_set_cos_bw_args *args);\n \ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex 49f1c6691d..d6828aa482 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -389,6 +389,8 @@ struct dlb2_port {\n \tbool use_avx512;\n \tuint32_t cq_weight;\n \tbool is_producer; /* True if port is of type producer */\n+\tuint16_t inflight_threshold; /* DLB2.5 HW inflight threshold */\n+\tbool enable_inflight_ctrl; /*DLB2.5 enable HW inflight control */\n };\n \n /* Per-process per-port mmio and memory pointers */\n@@ -718,6 +720,9 @@ int dlb2_secondary_eventdev_probe(struct rte_eventdev *dev,\n uint32_t dlb2_get_queue_depth(struct dlb2_eventdev *dlb2,\n \t\t\t struct dlb2_eventdev_queue *queue);\n \n+int dlb2_set_port_param(struct dlb2_eventdev *dlb2, int port_id,\n+\t\t\tuint64_t flags, void *val);\n+\n int dlb2_parse_params(const char *params,\n \t\t const char *name,\n \t\t struct dlb2_devargs *dlb2_args,\ndiff --git a/drivers/event/dlb2/dlb2_user.h b/drivers/event/dlb2/dlb2_user.h\nindex 8739e2a5ac..ca09c65ac4 100644\n--- a/drivers/event/dlb2/dlb2_user.h\n+++ b/drivers/event/dlb2/dlb2_user.h\n@@ -472,6 +472,8 @@ struct dlb2_create_ldb_port_args {\n \t__u16 cq_history_list_size;\n \t__u8 cos_id;\n \t__u8 cos_strict;\n+\t__u8 enable_inflight_ctrl;\n+\t__u16 inflight_threshold;\n };\n \n /*\n@@ -717,6 +719,28 @@ struct dlb2_enable_cq_weight_args {\n \t__u32 limit;\n };\n \n+/*\n+ * DLB2_DOMAIN_CMD_SET_CQ_INFLIGHT_CTRL: Set Per-CQ inflight control for\n+ * {ATM,UNO,ORD} QEs.\n+ *\n+ * Input parameters:\n+ * - port_id: Load-balanced port ID.\n+ * - enable: True if inflight control is enabled. False otherwise\n+ * - threshold: Per CQ inflight threshold.\n+ *\n+ * Output parameters:\n+ * - response.status: Detailed error code. In certain cases, such as if the\n+ *\tioctl request arg is invalid, the driver won't set status.\n+ */\n+struct dlb2_cq_inflight_ctrl_args {\n+\t/* Output parameters */\n+\tstruct dlb2_cmd_response response;\n+\t/* Input parameters */\n+\t__u32 port_id;\n+\t__u16 enable;\n+\t__u16 threshold;\n+};\n+\n /*\n * Mapping sizes for memory mapping the consumer queue (CQ) memory space, and\n * producer port (PP) MMIO space.\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_regs.h b/drivers/event/dlb2/pf/base/dlb2_regs.h\nindex 7167f3d2ff..b639a5b659 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_regs.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_regs.h\n@@ -3238,6 +3238,15 @@\n #define DLB2_LSP_CQ_LDB_INFL_LIM_LIMIT_LOC\t0\n #define DLB2_LSP_CQ_LDB_INFL_LIM_RSVD0_LOC\t12\n \n+#define DLB2_LSP_CQ_LDB_INFL_THRESH(x) \\\n+\t(0x90580000 + (x) * 0x1000)\n+#define DLB2_LSP_CQ_LDB_INFL_THRESH_RST 0x0\n+\n+#define DLB2_LSP_CQ_LDB_INFL_THRESH_THRESH\t0x00000FFF\n+#define DLB2_LSP_CQ_LDB_INFL_THRESH_RSVD0\t0xFFFFF000\n+#define DLB2_LSP_CQ_LDB_INFL_THRESH_THRESH_LOC\t0\n+#define DLB2_LSP_CQ_LDB_INFL_THRESH_RSVD0_LOC\t12\n+\n #define DLB2_V2LSP_CQ_LDB_TKN_CNT(x) \\\n \t(0xa0580000 + (x) * 0x1000)\n #define DLB2_V2_5LSP_CQ_LDB_TKN_CNT(x) \\\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c\nindex 7ce3e3531c..051d7e51c3 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.c\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c\n@@ -3062,10 +3062,14 @@ static void __dlb2_domain_reset_ldb_port_registers(struct dlb2_hw *hw,\n \t\t DLB2_CHP_LDB_CQ_DEPTH(hw->ver, port->id.phys_id),\n \t\t DLB2_CHP_LDB_CQ_DEPTH_RST);\n \n-\tif (hw->ver != DLB2_HW_V2)\n+\tif (hw->ver != DLB2_HW_V2) {\n \t\tDLB2_CSR_WR(hw,\n \t\t\t DLB2_LSP_CFG_CQ_LDB_WU_LIMIT(port->id.phys_id),\n \t\t\t DLB2_LSP_CFG_CQ_LDB_WU_LIMIT_RST);\n+\t\tDLB2_CSR_WR(hw,\n+\t\t\t DLB2_LSP_CQ_LDB_INFL_THRESH(port->id.phys_id),\n+\t\t\t DLB2_LSP_CQ_LDB_INFL_THRESH_RST);\n+\t}\n \n \tDLB2_CSR_WR(hw,\n \t\t DLB2_LSP_CQ_LDB_INFL_LIM(hw->ver, port->id.phys_id),\n@@ -4446,6 +4450,20 @@ static int dlb2_ldb_port_configure_cq(struct dlb2_hw *hw,\n \treg = 0;\n \tDLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(hw->ver, port->id.phys_id), reg);\n \n+\tif (hw->ver == DLB2_HW_V2_5) {\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, args->enable_inflight_ctrl,\n+\t\t\t\tDLB2_LSP_CFG_CTRL_GENERAL_0_ENAB_IF_THRESH_V2_5);\n+\t\tDLB2_CSR_WR(hw, DLB2_V2_5LSP_CFG_CTRL_GENERAL_0, reg);\n+\n+\t\tif (args->enable_inflight_ctrl) {\n+\t\t\treg = 0;\n+\t\t\tDLB2_BITS_SET(reg, args->inflight_threshold,\n+\t\t\t\t\tDLB2_LSP_CQ_LDB_INFL_THRESH_THRESH);\n+\t\t\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_INFL_THRESH(port->id.phys_id), reg);\n+\t\t}\n+\t}\n+\n \treturn 0;\n }\n \n@@ -5464,6 +5482,35 @@ dlb2_get_domain_used_ldb_port(u32 id,\n \treturn NULL;\n }\n \n+static struct dlb2_ldb_port *\n+dlb2_get_domain_ldb_port(u32 id,\n+\t\t\t bool vdev_req,\n+\t\t\t struct dlb2_hw_domain *domain)\n+{\n+\tstruct dlb2_list_entry *iter __attribute__((unused));\n+\tstruct dlb2_ldb_port *port;\n+\tint i;\n+\n+\tif (id >= DLB2_MAX_NUM_LDB_PORTS)\n+\t\treturn NULL;\n+\n+\tfor (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {\n+\t\tDLB2_DOM_LIST_FOR(domain->used_ldb_ports[i], port, iter) {\n+\t\t\tif ((!vdev_req && port->id.phys_id == id) ||\n+\t\t\t (vdev_req && port->id.virt_id == id))\n+\t\t\t\treturn port;\n+\t\t}\n+\n+\t\tDLB2_DOM_LIST_FOR(domain->avail_ldb_ports[i], port, iter) {\n+\t\t\tif ((!vdev_req && port->id.phys_id == id) ||\n+\t\t\t (vdev_req && port->id.virt_id == id))\n+\t\t\t\treturn port;\n+\t\t}\n+\t}\n+\n+\treturn NULL;\n+}\n+\n static void dlb2_ldb_port_change_qid_priority(struct dlb2_hw *hw,\n \t\t\t\t\t struct dlb2_ldb_port *port,\n \t\t\t\t\t int slot,\n@@ -6816,3 +6863,49 @@ int dlb2_hw_set_cos_bandwidth(struct dlb2_hw *hw, u32 cos_id, u8 bandwidth)\n \n \treturn 0;\n }\n+\n+int dlb2_hw_set_cq_inflight_ctrl(struct dlb2_hw *hw, u32 domain_id,\n+\t\tstruct dlb2_cq_inflight_ctrl_args *args,\n+\t\tstruct dlb2_cmd_response *resp,\n+\t\tbool vdev_req,\n+\t\tunsigned int vdev_id)\n+{\n+\tstruct dlb2_hw_domain *domain;\n+\tstruct dlb2_ldb_port *port;\n+\tu32 reg = 0;\n+\tint id;\n+\n+\tdomain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);\n+\tif (!domain) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: domain not found\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tid = args->port_id;\n+\n+\tport = dlb2_get_domain_ldb_port(id, vdev_req, domain);\n+\tif (!port) {\n+\t\tDLB2_HW_ERR(hw,\n+\t\t\t \"[%s():%d] Internal error: port not found\\n\",\n+\t\t\t __func__, __LINE__);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tDLB2_BITS_SET(reg, args->enable,\n+\t\t DLB2_LSP_CFG_CTRL_GENERAL_0_ENAB_IF_THRESH_V2_5);\n+\tDLB2_CSR_WR(hw, DLB2_V2_5LSP_CFG_CTRL_GENERAL_0, reg);\n+\n+\tif (args->enable) {\n+\t\treg = 0;\n+\t\tDLB2_BITS_SET(reg, args->threshold,\n+\t\t\t DLB2_LSP_CQ_LDB_INFL_THRESH_THRESH);\n+\t\tDLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_INFL_THRESH(port->id.phys_id),\n+\t\t\t reg);\n+\t}\n+\n+\tresp->status = 0;\n+\n+\treturn 0;\n+}\ndiff --git a/drivers/event/dlb2/pf/base/dlb2_resource.h b/drivers/event/dlb2/pf/base/dlb2_resource.h\nindex 71bd6148f1..17cc745824 100644\n--- a/drivers/event/dlb2/pf/base/dlb2_resource.h\n+++ b/drivers/event/dlb2/pf/base/dlb2_resource.h\n@@ -1956,4 +1956,23 @@ int dlb2_hw_enable_cq_weight(struct dlb2_hw *hw,\n \t\t\t bool vdev_request,\n \t\t\t unsigned int vdev_id);\n \n+/**\n+ * This function configures the inflight control threshold for a cq.\n+ *\n+ * This must be called after creating the port.\n+ *\n+ * Return:\n+ * Returns 0 upon success, < 0 otherwise. If an error occurs, resp->status is\n+ * assigned a detailed error code from enum dlb2_error. If successful, resp->id\n+ * contains the queue ID.\n+ *\n+ * Errors:\n+ * EINVAL - The domain or port is not configured.\n+ */\n+int dlb2_hw_set_cq_inflight_ctrl(struct dlb2_hw *hw, u32 domain_id,\n+\t\tstruct dlb2_cq_inflight_ctrl_args *args,\n+\t\tstruct dlb2_cmd_response *resp,\n+\t\tbool vdev_req,\n+\t\tunsigned int vdev_id);\n+\n #endif /* __DLB2_RESOURCE_H */\ndiff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c\nindex 3d15250e11..249ed7ede9 100644\n--- a/drivers/event/dlb2/pf/dlb2_pf.c\n+++ b/drivers/event/dlb2/pf/dlb2_pf.c\n@@ -665,6 +665,26 @@ dlb2_pf_set_cos_bandwidth(struct dlb2_hw_dev *handle,\n \treturn ret;\n }\n \n+static int\n+dlb2_pf_set_cq_inflight_ctrl(struct dlb2_hw_dev *handle,\n+\t\t\t struct dlb2_cq_inflight_ctrl_args *args)\n+{\n+\tstruct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;\n+\tstruct dlb2_cmd_response response = {0};\n+\tint ret = 0;\n+\n+\tDLB2_INFO(dev->dlb2_device, \"Entering %s()\\n\", __func__);\n+\n+\tret = dlb2_hw_set_cq_inflight_ctrl(&dlb2_dev->hw, handle->domain_id,\n+\t\t\t\t\t args, &response, false, 0);\n+\targs->response = response;\n+\n+\tDLB2_INFO(dev->dlb2_device, \"Exiting %s() with ret=%d\\n\",\n+\t\t __func__, ret);\n+\n+\treturn ret;\n+}\n+\n static void\n dlb2_pf_iface_fn_ptrs_init(void)\n {\n@@ -691,6 +711,7 @@ dlb2_pf_iface_fn_ptrs_init(void)\n \tdlb2_iface_get_sn_occupancy = dlb2_pf_get_sn_occupancy;\n \tdlb2_iface_enable_cq_weight = dlb2_pf_enable_cq_weight;\n \tdlb2_iface_set_cos_bw = dlb2_pf_set_cos_bandwidth;\n+\tdlb2_iface_set_cq_inflight_ctrl = dlb2_pf_set_cq_inflight_ctrl;\n }\n \n /* PCI DEV HOOKS */\ndiff --git a/drivers/event/dlb2/rte_pmd_dlb2.c b/drivers/event/dlb2/rte_pmd_dlb2.c\nindex 43990e46ac..c72a42b466 100644\n--- a/drivers/event/dlb2/rte_pmd_dlb2.c\n+++ b/drivers/event/dlb2/rte_pmd_dlb2.c\n@@ -33,7 +33,36 @@ rte_pmd_dlb2_set_token_pop_mode(uint8_t dev_id,\n \tif (port_id >= dlb2->num_ports || dlb2->ev_ports[port_id].setup_done)\n \t\treturn -EINVAL;\n \n+\tif (dlb2->version == DLB2_HW_V2_5 && mode == DELAYED_POP) {\n+\t\tdlb2->ev_ports[port_id].qm_port.enable_inflight_ctrl = true;\n+\t\tdlb2->ev_ports[port_id].qm_port.inflight_threshold = 1;\n+\t\tmode = AUTO_POP;\n+\t}\n+\n \tdlb2->ev_ports[port_id].qm_port.token_pop_mode = mode;\n \n \treturn 0;\n }\n+\n+int\n+rte_pmd_dlb2_set_port_param(uint8_t dev_id,\n+\t\t\t uint8_t port_id,\n+\t\t\t uint64_t flags,\n+\t\t\t void *val)\n+{\n+\tstruct dlb2_eventdev *dlb2;\n+\tstruct rte_eventdev *dev;\n+\n+\tif (val == NULL)\n+\t\treturn -EINVAL;\n+\n+\tRTE_EVENTDEV_VALID_DEVID_OR_ERR_RET(dev_id, -EINVAL);\n+\tdev = &rte_eventdevs[dev_id];\n+\n+\tdlb2 = dlb2_pmd_priv(dev);\n+\n+\tif (port_id >= dlb2->num_ports)\n+\t\treturn -EINVAL;\n+\n+\treturn dlb2_set_port_param(dlb2, port_id, flags, val);\n+}\ndiff --git a/drivers/event/dlb2/rte_pmd_dlb2.h b/drivers/event/dlb2/rte_pmd_dlb2.h\nindex 334c6c356d..6e78dfb5a5 100644\n--- a/drivers/event/dlb2/rte_pmd_dlb2.h\n+++ b/drivers/event/dlb2/rte_pmd_dlb2.h\n@@ -67,6 +67,46 @@ rte_pmd_dlb2_set_token_pop_mode(uint8_t dev_id,\n \t\t\t\tuint8_t port_id,\n \t\t\t\tenum dlb2_token_pop_mode mode);\n \n+/** Set inflight threshold for flow migration */\n+#define DLB2_FLOW_MIGRATION_THRESHOLD RTE_BIT64(0)\n+\n+/** Set port history list */\n+#define DLB2_SET_PORT_HL RTE_BIT64(1)\n+\n+struct dlb2_port_param {\n+\tuint16_t inflight_threshold : 12;\n+};\n+\n+/*!\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change, or be removed, without prior notice\n+ *\n+ * Configure various port parameters.\n+ * AUTO_POP. This function must be called before calling rte_event_port_setup()\n+ * for the port, but after calling rte_event_dev_configure().\n+ *\n+ * @param dev_id\n+ * The identifier of the event device.\n+ * @param port_id\n+ * The identifier of the event port.\n+ * @param flags\n+ * Bitmask of the parameters being set.\n+ * @param val\n+ * Structure coantaining the values of parameters being set.\n+ *\n+ * @return\n+ * - 0: Success\n+ * - EINVAL: Invalid dev_id, port_id, or mode\n+ * - EINVAL: The DLB2 is not configured, is already running, or the port is\n+ * already setup\n+ */\n+__rte_experimental\n+int\n+rte_pmd_dlb2_set_port_param(uint8_t dev_id,\n+\t\t\t uint8_t port_id,\n+\t\t\t uint64_t flags,\n+\t\t\t void *val);\n+\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/drivers/event/dlb2/version.map b/drivers/event/dlb2/version.map\nindex 1d0a0a75d7..5078e4960a 100644\n--- a/drivers/event/dlb2/version.map\n+++ b/drivers/event/dlb2/version.map\n@@ -5,6 +5,9 @@ DPDK_24 {\n EXPERIMENTAL {\n \tglobal:\n \n+\t# added in 24.07\n+\trte_pmd_dlb2_set_port_param;\n+\n \t# added in 20.11\n \trte_pmd_dlb2_set_token_pop_mode;\n };\n", "prefixes": [ "v1", "1/3" ] }