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GET /api/patches/139776/?format=api
{ "id": 139776, "url": "http://patchwork.dpdk.org/api/patches/139776/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240501175100.1192839-4-abdullah.sevincer@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240501175100.1192839-4-abdullah.sevincer@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240501175100.1192839-4-abdullah.sevincer@intel.com", "date": "2024-05-01T17:51:00", "name": "[v1,3/3] event/dlb2: enhance DLB credit handling", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "33708deb0cb90be2df8f53f6fdef7240cf611eb5", "submitter": { "id": 2843, "url": "http://patchwork.dpdk.org/api/people/2843/?format=api", "name": "Sevincer, Abdullah", "email": "abdullah.sevincer@intel.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240501175100.1192839-4-abdullah.sevincer@intel.com/mbox/", "series": [ { "id": 31858, "url": "http://patchwork.dpdk.org/api/series/31858/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31858", "date": "2024-05-01T17:50:57", "name": "*** DLB2 Enhancements ***", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31858/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139776/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/139776/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1AC3E43F5D;\n\tWed, 1 May 2024 19:51:28 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 837A4402E3;\n\tWed, 1 May 2024 19:51:11 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.7])\n by mails.dpdk.org (Postfix) with ESMTP id CE420402BC\n for <dev@dpdk.org>; Wed, 1 May 2024 19:51:08 +0200 (CEST)", "from orviesa005.jf.intel.com ([10.64.159.145])\n by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 May 2024 10:51:09 -0700", "from txanpdk02.an.intel.com ([10.123.117.76])\n by orviesa005.jf.intel.com with ESMTP; 01 May 2024 10:51:08 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714585869; x=1746121869;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=kiSkaVTlmtJVEVGh+JisKBOCc/olipYs9f4dupCT16g=;\n b=PzhN3ZoB3RFmEXwhp0mTlIjKfZpiINIKnVtEcOk3ZCG82dZHRITYXW/P\n g3cvsl32URRFueldrdxXz6Q4B1usvIzo8JMeyC7oDuYJcN1X4P7dzsc0q\n dKK6QjiG3+zvpbo4eUdDK7eNFw7avjSpnFSpYSEDF5sgGuvmcmNH9QYFU\n ytUJ+f4mqZJ5fYFIqu/GTazS2k0pFnj/cUA12+TXfU/q7oqYW5iNaPwJX\n Hfw3n5hGHyiGVaGITChhzPUf32nGkqvOAGCwQCKhcR4LjcCEZ1LFPVJux\n WQ3VpxViQ73hVsheWqsXgGuqLZ6mF8ga3NMnbf6YRGl6+2NfiB0dvrGMC A==;", "X-CSE-ConnectionGUID": [ "px+u8ICWTpaWBoMTgQtxXA==", "NNz4X2FgT0iiHmLHEUZLyA==" ], "X-CSE-MsgGUID": [ "nwBEvBsLSIy60ILHviQ/Dg==", "Mth9oaiYT12Bcy1psORL5Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11061\"; a=\"35714483\"", "E=Sophos;i=\"6.07,246,1708416000\"; d=\"scan'208\";a=\"35714483\"", "E=Sophos;i=\"6.07,246,1708416000\"; d=\"scan'208\";a=\"31662348\"" ], "X-ExtLoop1": "1", "From": "Abdullah Sevincer <abdullah.sevincer@intel.com>", "To": "dev@dpdk.org", "Cc": "jerinj@marvell.com, mike.ximing.chen@intel.com,\n tirthendu.sarkar@intel.com,\n pravin.pathak@intel.com, shivani.doneria@intel.com,\n Abdullah Sevincer <abdullah.sevincer@intel.com>", "Subject": "[PATCH v1 3/3] event/dlb2: enhance DLB credit handling", "Date": "Wed, 1 May 2024 12:51:00 -0500", "Message-Id": "<20240501175100.1192839-4-abdullah.sevincer@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240501175100.1192839-1-abdullah.sevincer@intel.com>", "References": "<20240501175100.1192839-1-abdullah.sevincer@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit improves DLB credit handling scenarios when\nports hold on to credits but can't release them due to insufficient\naccumulation (less than 2 * credit quanta).\n\nWorker ports now release all accumulated credits when back-to-back\nzero poll count reaches preset threshold.\n\nProducer ports release all accumulated credits if enqueue fails for a\nconsecutive number of retries.\n\nIn a multi-producer system, some producer(s) may exit early while\nholding on to credits. Now these are released during port unlink\nwhich needs to be performed by the application.\n\ntest-eventdev is modified to call rte_event_port_unlink() to release\nany accumulated credits by producer ports.\n\nSigned-off-by: Abdullah Sevincer <abdullah.sevincer@intel.com>\n---\n app/test-eventdev/test_perf_common.c | 20 +--\n drivers/event/dlb2/dlb2.c | 203 +++++++++++++++++++++------\n drivers/event/dlb2/dlb2_priv.h | 1 +\n drivers/event/dlb2/meson.build | 12 ++\n drivers/event/dlb2/meson_options.txt | 6 +\n 5 files changed, 194 insertions(+), 48 deletions(-)\n create mode 100644 drivers/event/dlb2/meson_options.txt", "diff": "diff --git a/app/test-eventdev/test_perf_common.c b/app/test-eventdev/test_perf_common.c\nindex 93e6132de8..b3a12e12ac 100644\n--- a/app/test-eventdev/test_perf_common.c\n+++ b/app/test-eventdev/test_perf_common.c\n@@ -854,6 +854,7 @@ perf_producer_wrapper(void *arg)\n \tstruct rte_event_dev_info dev_info;\n \tstruct prod_data *p = arg;\n \tstruct test_perf *t = p->t;\n+\tint ret = 0;\n \n \trte_event_dev_info_get(p->dev_id, &dev_info);\n \tif (!t->opt->prod_enq_burst_sz) {\n@@ -870,29 +871,32 @@ perf_producer_wrapper(void *arg)\n \t */\n \tif (t->opt->prod_type == EVT_PROD_TYPE_SYNT &&\n \t\t\tt->opt->prod_enq_burst_sz == 1)\n-\t\treturn perf_producer(arg);\n+\t\tret = perf_producer(arg);\n \telse if (t->opt->prod_type == EVT_PROD_TYPE_SYNT &&\n \t\t\tt->opt->prod_enq_burst_sz > 1) {\n \t\tif (dev_info.max_event_port_enqueue_depth == 1)\n \t\t\tevt_err(\"This event device does not support burst mode\");\n \t\telse\n-\t\t\treturn perf_producer_burst(arg);\n+\t\t\tret = perf_producer_burst(arg);\n \t}\n \telse if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR &&\n \t\t\t!t->opt->timdev_use_burst)\n-\t\treturn perf_event_timer_producer(arg);\n+\t\tret = perf_event_timer_producer(arg);\n \telse if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_TIMER_ADPTR &&\n \t\t\tt->opt->timdev_use_burst)\n-\t\treturn perf_event_timer_producer_burst(arg);\n+\t\tret = perf_event_timer_producer_burst(arg);\n \telse if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_CRYPTO_ADPTR) {\n \t\tif (t->opt->prod_enq_burst_sz > 1)\n-\t\t\treturn perf_event_crypto_producer_burst(arg);\n+\t\t\tret = perf_event_crypto_producer_burst(arg);\n \t\telse\n-\t\t\treturn perf_event_crypto_producer(arg);\n+\t\t\tret = perf_event_crypto_producer(arg);\n \t} else if (t->opt->prod_type == EVT_PROD_TYPE_EVENT_DMA_ADPTR)\n-\t\treturn perf_event_dma_producer(arg);\n+\t\tret = perf_event_dma_producer(arg);\n \n-\treturn 0;\n+\t/* Unlink port to release any acquired HW resources*/\n+\trte_event_port_unlink(p->dev_id, p->port_id, &p->queue_id, 1);\n+\n+\treturn ret;\n }\n \n static inline uint64_t\ndiff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 56db9bc937..b4217e2a50 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -43,7 +43,47 @@\n * to DLB can go ahead of relevant application writes like updates to buffers\n * being sent with event\n */\n+#ifndef DLB2_BYPASS_FENCE_ON_PP\n #define DLB2_BYPASS_FENCE_ON_PP 0 /* 1 == Bypass fence, 0 == do not bypass */\n+#endif\n+\n+/* HW credit checks can only be turned off for DLB2 device if following\n+ * is true for each created eventdev\n+ * LDB credits <= DIR credits + minimum CQ Depth\n+ * (CQ Depth is minimum of all ports configured within eventdev)\n+ * This needs to be true for all eventdevs created on any DLB2 device\n+ * managed by this driver.\n+ * DLB2.5 does not any such restriction as it has single credit pool\n+ */\n+#ifndef DLB_HW_CREDITS_CHECKS\n+#define DLB_HW_CREDITS_CHECKS 1\n+#endif\n+\n+/*\n+ * SW credit checks can only be turned off if application has a way to\n+ * limit input events to the eventdev below assigned credit limit\n+ */\n+#ifndef DLB_SW_CREDITS_CHECKS\n+#define DLB_SW_CREDITS_CHECKS 1\n+#endif\n+\n+/*\n+ * To avoid deadlock situations, by default, per port new_event_threshold\n+ * check is disabled. nb_events_limit is still checked while allocating\n+ * new event credits.\n+ */\n+#define ENABLE_PORT_THRES_CHECK 1\n+/*\n+ * To avoid deadlock, ports holding to credits will release them after these\n+ * many consecutive zero dequeues\n+ */\n+#define DLB2_ZERO_DEQ_CREDIT_RETURN_THRES 16384\n+\n+/*\n+ * To avoid deadlock, ports holding to credits will release them after these\n+ * many consecutive enqueue failures\n+ */\n+#define DLB2_ENQ_FAIL_CREDIT_RETURN_THRES 100\n \n /*\n * Resources exposed to eventdev. Some values overridden at runtime using\n@@ -2488,6 +2528,61 @@ dlb2_event_queue_detach_ldb(struct dlb2_eventdev *dlb2,\n \treturn ret;\n }\n \n+static inline void\n+dlb2_port_credits_return(struct dlb2_port *qm_port)\n+{\n+\t/* Return all port credits */\n+\tif (qm_port->dlb2->version == DLB2_HW_V2_5) {\n+\t\tif (qm_port->cached_credits) {\n+\t\t\t__atomic_fetch_add(qm_port->credit_pool[DLB2_COMBINED_POOL],\n+\t\t\t\t\t qm_port->cached_credits, __ATOMIC_SEQ_CST);\n+\t\t\tqm_port->cached_credits = 0;\n+\t\t}\n+\t} else {\n+\t\tif (qm_port->cached_ldb_credits) {\n+\t\t\t__atomic_fetch_add(qm_port->credit_pool[DLB2_LDB_QUEUE],\n+\t\t\t\t\t qm_port->cached_ldb_credits, __ATOMIC_SEQ_CST);\n+\t\t\tqm_port->cached_ldb_credits = 0;\n+\t\t}\n+\t\tif (qm_port->cached_dir_credits) {\n+\t\t\t__atomic_fetch_add(qm_port->credit_pool[DLB2_DIR_QUEUE],\n+\t\t\t\t\t qm_port->cached_dir_credits, __ATOMIC_SEQ_CST);\n+\t\t\tqm_port->cached_dir_credits = 0;\n+\t\t}\n+\t}\n+}\n+\n+static inline void\n+dlb2_release_sw_credits(struct dlb2_eventdev *dlb2,\n+\t\t\tstruct dlb2_eventdev_port *ev_port, uint16_t val)\n+{\n+\tif (ev_port->inflight_credits) {\n+\t\t__atomic_fetch_sub(&dlb2->inflights, val, __ATOMIC_SEQ_CST);\n+\t\tev_port->inflight_credits -= val;\n+\t}\n+}\n+\n+static void dlb2_check_and_return_credits(struct dlb2_eventdev_port *ev_port,\n+\t\t\t\t\t bool cond, uint32_t threshold)\n+{\n+#if DLB_SW_CREDITS_CHECKS || DLB_HW_CREDITS_CHECKS\n+\tif (cond) {\n+\t\tif (++ev_port->credit_return_count > threshold) {\n+#if DLB_SW_CREDITS_CHECKS\n+\t\t\tdlb2_release_sw_credits(ev_port->dlb2, ev_port,\n+\t\t\t\t\t\tev_port->inflight_credits);\n+#endif\n+#if DLB_HW_CREDITS_CHECKS\n+\t\t\tdlb2_port_credits_return(&ev_port->qm_port);\n+#endif\n+\t\t\tev_port->credit_return_count = 0;\n+\t\t}\n+\t} else {\n+\t\tev_port->credit_return_count = 0;\n+\t}\n+#endif\n+}\n+\n static int\n dlb2_eventdev_port_unlink(struct rte_eventdev *dev, void *event_port,\n \t\t\t uint8_t queues[], uint16_t nb_unlinks)\n@@ -2507,14 +2602,15 @@ dlb2_eventdev_port_unlink(struct rte_eventdev *dev, void *event_port,\n \n \tif (queues == NULL || nb_unlinks == 0) {\n \t\tDLB2_LOG_DBG(\"dlb2: queues is NULL or nb_unlinks is 0\\n\");\n-\t\treturn 0; /* Ignore and return success */\n+\t\tnb_unlinks = 0; /* Ignore and return success */\n+\t\tgoto ret_credits;\n \t}\n \n \tif (ev_port->qm_port.is_directed) {\n \t\tDLB2_LOG_DBG(\"dlb2: ignore unlink from dir port %d\\n\",\n \t\t\t ev_port->id);\n \t\trte_errno = 0;\n-\t\treturn nb_unlinks; /* as if success */\n+\t\tgoto ret_credits;\n \t}\n \n \tdlb2 = ev_port->dlb2;\n@@ -2553,6 +2649,10 @@ dlb2_eventdev_port_unlink(struct rte_eventdev *dev, void *event_port,\n \t\tev_queue->num_links--;\n \t}\n \n+ret_credits:\n+\tif (ev_port->inflight_credits)\n+\t\tdlb2_check_and_return_credits(ev_port, true, 0);\n+\n \treturn nb_unlinks;\n }\n \n@@ -2752,8 +2852,7 @@ dlb2_replenish_sw_credits(struct dlb2_eventdev *dlb2,\n \t\t/* Replenish credits, saving one quanta for enqueues */\n \t\tuint16_t val = ev_port->inflight_credits - quanta;\n \n-\t\t__atomic_fetch_sub(&dlb2->inflights, val, __ATOMIC_SEQ_CST);\n-\t\tev_port->inflight_credits -= val;\n+\t\tdlb2_release_sw_credits(dlb2, ev_port, val);\n \t}\n }\n \n@@ -2924,7 +3023,9 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n {\n \tstruct dlb2_eventdev *dlb2 = ev_port->dlb2;\n \tstruct dlb2_eventdev_queue *ev_queue;\n+#if DLB_HW_CREDITS_CHECKS\n \tuint16_t *cached_credits = NULL;\n+#endif\n \tstruct dlb2_queue *qm_queue;\n \n \tev_queue = &dlb2->ev_queues[ev->queue_id];\n@@ -2936,6 +3037,7 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t\tgoto op_check;\n \n \tif (!qm_queue->is_directed) {\n+#if DLB_HW_CREDITS_CHECKS\n \t\t/* Load balanced destination queue */\n \n \t\tif (dlb2->version == DLB2_HW_V2) {\n@@ -2951,6 +3053,7 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t\t\t}\n \t\t\tcached_credits = &qm_port->cached_credits;\n \t\t}\n+#endif\n \t\tswitch (ev->sched_type) {\n \t\tcase RTE_SCHED_TYPE_ORDERED:\n \t\t\tDLB2_LOG_DBG(\"dlb2: put_qe: RTE_SCHED_TYPE_ORDERED\\n\");\n@@ -2981,7 +3084,7 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t\t}\n \t} else {\n \t\t/* Directed destination queue */\n-\n+#if DLB_HW_CREDITS_CHECKS\n \t\tif (dlb2->version == DLB2_HW_V2) {\n \t\t\tif (dlb2_check_enqueue_hw_dir_credits(qm_port)) {\n \t\t\t\trte_errno = -ENOSPC;\n@@ -2995,6 +3098,7 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t\t\t}\n \t\t\tcached_credits = &qm_port->cached_credits;\n \t\t}\n+#endif\n \t\tDLB2_LOG_DBG(\"dlb2: put_qe: RTE_SCHED_TYPE_DIRECTED\\n\");\n \n \t\t*sched_type = DLB2_SCHED_DIRECTED;\n@@ -3002,6 +3106,7 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \n op_check:\n \tswitch (ev->op) {\n+#if DLB_SW_CREDITS_CHECKS\n \tcase RTE_EVENT_OP_NEW:\n \t\t/* Check that a sw credit is available */\n \t\tif (dlb2_check_enqueue_sw_credits(dlb2, ev_port)) {\n@@ -3009,7 +3114,10 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t\t\treturn 1;\n \t\t}\n \t\tev_port->inflight_credits--;\n+#endif\n+#if DLB_HW_CREDITS_CHECKS\n \t\t(*cached_credits)--;\n+#endif\n \t\tbreak;\n \tcase RTE_EVENT_OP_FORWARD:\n \t\t/* Check for outstanding_releases underflow. If this occurs,\n@@ -3020,10 +3128,14 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t\tRTE_ASSERT(ev_port->outstanding_releases > 0);\n \t\tev_port->outstanding_releases--;\n \t\tqm_port->issued_releases++;\n+#if DLB_HW_CREDITS_CHECKS\n \t\t(*cached_credits)--;\n+#endif\n \t\tbreak;\n \tcase RTE_EVENT_OP_RELEASE:\n+#if DLB_SW_CREDITS_CHECKS\n \t\tev_port->inflight_credits++;\n+#endif\n \t\t/* Check for outstanding_releases underflow. If this occurs,\n \t\t * the application is not using the EVENT_OPs correctly; for\n \t\t * example, forwarding or releasing events that were not\n@@ -3032,9 +3144,10 @@ dlb2_event_enqueue_prep(struct dlb2_eventdev_port *ev_port,\n \t\tRTE_ASSERT(ev_port->outstanding_releases > 0);\n \t\tev_port->outstanding_releases--;\n \t\tqm_port->issued_releases++;\n-\n+#if DLB_SW_CREDITS_CHECKS\n \t\t/* Replenish s/w credits if enough are cached */\n \t\tdlb2_replenish_sw_credits(dlb2, ev_port);\n+#endif\n \t\tbreak;\n \t}\n \n@@ -3145,6 +3258,8 @@ __dlb2_event_enqueue_burst(void *event_port,\n \t\t\tbreak;\n \t}\n \n+\tdlb2_check_and_return_credits(ev_port, !i, DLB2_ENQ_FAIL_CREDIT_RETURN_THRES);\n+\n \treturn i;\n }\n \n@@ -3283,53 +3398,45 @@ dlb2_event_release(struct dlb2_eventdev *dlb2,\n \t\treturn;\n \t}\n \tev_port->outstanding_releases -= i;\n+#if DLB_SW_CREDITS_CHECKS\n \tev_port->inflight_credits += i;\n \n \t/* Replenish s/w credits if enough releases are performed */\n \tdlb2_replenish_sw_credits(dlb2, ev_port);\n+#endif\n }\n \n static inline void\n dlb2_port_credits_inc(struct dlb2_port *qm_port, int num)\n {\n \tuint32_t batch_size = qm_port->hw_credit_quanta;\n+\tint val;\n \n \t/* increment port credits, and return to pool if exceeds threshold */\n-\tif (!qm_port->is_directed) {\n-\t\tif (qm_port->dlb2->version == DLB2_HW_V2) {\n-\t\t\tqm_port->cached_ldb_credits += num;\n-\t\t\tif (qm_port->cached_ldb_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n-\t\t\t\t\tqm_port->credit_pool[DLB2_LDB_QUEUE],\n-\t\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n-\t\t\t\tqm_port->cached_ldb_credits -= batch_size;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tqm_port->cached_credits += num;\n-\t\t\tif (qm_port->cached_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n-\t\t\t\t qm_port->credit_pool[DLB2_COMBINED_POOL],\n-\t\t\t\t batch_size, __ATOMIC_SEQ_CST);\n-\t\t\t\tqm_port->cached_credits -= batch_size;\n-\t\t\t}\n+\tif (qm_port->dlb2->version == DLB2_HW_V2_5) {\n+\t\tqm_port->cached_credits += num;\n+\t\tif (qm_port->cached_credits >= 2 * batch_size) {\n+\t\t\tval = qm_port->cached_credits - batch_size;\n+\t\t\t__atomic_fetch_add(\n+\t\t\t qm_port->credit_pool[DLB2_COMBINED_POOL], val,\n+\t\t\t __ATOMIC_SEQ_CST);\n+\t\t\tqm_port->cached_credits -= val;\n+\t\t}\n+\t} else if (!qm_port->is_directed) {\n+\t\tqm_port->cached_ldb_credits += num;\n+\t\tif (qm_port->cached_ldb_credits >= 2 * batch_size) {\n+\t\t\tval = qm_port->cached_ldb_credits - batch_size;\n+\t\t\t__atomic_fetch_add(qm_port->credit_pool[DLB2_LDB_QUEUE],\n+\t\t\t\t\t val, __ATOMIC_SEQ_CST);\n+\t\t\tqm_port->cached_ldb_credits -= val;\n \t\t}\n \t} else {\n-\t\tif (qm_port->dlb2->version == DLB2_HW_V2) {\n-\t\t\tqm_port->cached_dir_credits += num;\n-\t\t\tif (qm_port->cached_dir_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n-\t\t\t\t\tqm_port->credit_pool[DLB2_DIR_QUEUE],\n-\t\t\t\t\tbatch_size, __ATOMIC_SEQ_CST);\n-\t\t\t\tqm_port->cached_dir_credits -= batch_size;\n-\t\t\t}\n-\t\t} else {\n-\t\t\tqm_port->cached_credits += num;\n-\t\t\tif (qm_port->cached_credits >= 2 * batch_size) {\n-\t\t\t\t__atomic_fetch_add(\n-\t\t\t\t qm_port->credit_pool[DLB2_COMBINED_POOL],\n-\t\t\t\t batch_size, __ATOMIC_SEQ_CST);\n-\t\t\t\tqm_port->cached_credits -= batch_size;\n-\t\t\t}\n+\t\tqm_port->cached_dir_credits += num;\n+\t\tif (qm_port->cached_dir_credits >= 2 * batch_size) {\n+\t\t\tval = qm_port->cached_dir_credits - batch_size;\n+\t\t\t__atomic_fetch_add(qm_port->credit_pool[DLB2_DIR_QUEUE],\n+\t\t\t\t\t val, __ATOMIC_SEQ_CST);\n+\t\t\tqm_port->cached_dir_credits -= val;\n \t\t}\n \t}\n }\n@@ -3360,6 +3467,15 @@ dlb2_dequeue_wait(struct dlb2_eventdev *dlb2,\n \n \t/* Wait/poll time expired */\n \tif (elapsed_ticks >= timeout) {\n+\n+\t\t/* Return all credits before blocking if remaining credits in\n+\t\t * system is less than quanta.\n+\t\t */\n+\t\tuint32_t sw_inflights = __atomic_load_n(&dlb2->inflights, __ATOMIC_SEQ_CST);\n+\t\tuint32_t quanta = ev_port->credit_update_quanta;\n+\n+\t\tif (dlb2->new_event_limit - sw_inflights < quanta)\n+\t\t\tdlb2_check_and_return_credits(ev_port, true, 0);\n \t\treturn 1;\n \t} else if (dlb2->umwait_allowed) {\n \t\tstruct rte_power_monitor_cond pmc;\n@@ -4222,8 +4338,9 @@ dlb2_hw_dequeue(struct dlb2_eventdev *dlb2,\n \t\t\tdlb2_consume_qe_immediate(qm_port, num);\n \n \t\tev_port->outstanding_releases += num;\n-\n+#if DLB_HW_CREDITS_CHECKS\n \t\tdlb2_port_credits_inc(qm_port, num);\n+#endif\n \t}\n \n \treturn num;\n@@ -4257,6 +4374,9 @@ dlb2_event_dequeue_burst(void *event_port, struct rte_event *ev, uint16_t num,\n \tDLB2_INC_STAT(ev_port->stats.traffic.total_polls, 1);\n \tDLB2_INC_STAT(ev_port->stats.traffic.zero_polls, ((cnt == 0) ? 1 : 0));\n \n+\tdlb2_check_and_return_credits(ev_port, !cnt,\n+\t\t\t\t DLB2_ZERO_DEQ_CREDIT_RETURN_THRES);\n+\n \treturn cnt;\n }\n \n@@ -4293,6 +4413,9 @@ dlb2_event_dequeue_burst_sparse(void *event_port, struct rte_event *ev,\n \n \tDLB2_INC_STAT(ev_port->stats.traffic.total_polls, 1);\n \tDLB2_INC_STAT(ev_port->stats.traffic.zero_polls, ((cnt == 0) ? 1 : 0));\n+\n+\tdlb2_check_and_return_credits(ev_port, !cnt,\n+\t\t\t\t DLB2_ZERO_DEQ_CREDIT_RETURN_THRES);\n \treturn cnt;\n }\n \ndiff --git a/drivers/event/dlb2/dlb2_priv.h b/drivers/event/dlb2/dlb2_priv.h\nindex dc9f98e142..fd76b5b9fb 100644\n--- a/drivers/event/dlb2/dlb2_priv.h\n+++ b/drivers/event/dlb2/dlb2_priv.h\n@@ -527,6 +527,7 @@ struct __rte_cache_aligned dlb2_eventdev_port {\n \tstruct rte_event_port_conf conf; /* user-supplied configuration */\n \tuint16_t inflight_credits; /* num credits this port has right now */\n \tuint16_t credit_update_quanta;\n+\tuint32_t credit_return_count; /* count till the credit return condition is true */\n \tstruct dlb2_eventdev *dlb2; /* backlink optimization */\n \talignas(RTE_CACHE_LINE_SIZE) struct dlb2_port_stats stats;\n \tstruct dlb2_event_queue_link link[DLB2_MAX_NUM_QIDS_PER_LDB_CQ];\ndiff --git a/drivers/event/dlb2/meson.build b/drivers/event/dlb2/meson.build\nindex 515d1795fe..77a197e32c 100644\n--- a/drivers/event/dlb2/meson.build\n+++ b/drivers/event/dlb2/meson.build\n@@ -68,3 +68,15 @@ endif\n headers = files('rte_pmd_dlb2.h')\n \n deps += ['mbuf', 'mempool', 'ring', 'pci', 'bus_pci']\n+\n+if meson.version().version_compare('> 0.58.0')\n+fs = import('fs')\n+dlb_options = fs.read('meson_options.txt').strip().split('\\n')\n+\n+foreach opt: dlb_options\n+\tif (opt.strip().startswith('#') or opt.strip() == '')\n+\t\tcontinue\n+\tendif\n+\tcflags += '-D' + opt.strip().to_upper().replace(' ','')\n+endforeach\n+endif\ndiff --git a/drivers/event/dlb2/meson_options.txt b/drivers/event/dlb2/meson_options.txt\nnew file mode 100644\nindex 0000000000..69be6f41c1\n--- /dev/null\n+++ b/drivers/event/dlb2/meson_options.txt\n@@ -0,0 +1,6 @@\n+# SPDX-License-Identifier: BSD-3-Clause\n+# Copyright(c) 2023-2024 Intel Corporation\n+\n+DLB2_BYPASS_FENCE_ON_PP = 0\n+DLB_HW_CREDITS_CHECKS = 0\n+DLB_SW_CREDITS_CHECKS = 1\n", "prefixes": [ "v1", "3/3" ] }