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GET /api/patches/139851/?format=api
{ "id": 139851, "url": "http://patchwork.dpdk.org/api/patches/139851/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/9b5bd2935c671f829d2dd650cbeb7c50034695e0.1714744629.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<9b5bd2935c671f829d2dd650cbeb7c50034695e0.1714744629.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/9b5bd2935c671f829d2dd650cbeb7c50034695e0.1714744629.git.anatoly.burakov@intel.com", "date": "2024-05-03T13:57:54", "name": "[v2,23/27] net/ixgbe/base: add support for E610 device capabilities detection", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "88a57a157c80aac4d836ea73259300189a89d9a7", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/9b5bd2935c671f829d2dd650cbeb7c50034695e0.1714744629.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 31875, "url": "http://patchwork.dpdk.org/api/series/31875/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31875", "date": "2024-05-03T13:57:31", "name": "Update IXGBE base driver", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31875/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139851/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/139851/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id D1C7643F76;\n\tFri, 3 May 2024 16:01:02 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 02A4B402E4;\n\tFri, 3 May 2024 15:59:10 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.15])\n by mails.dpdk.org (Postfix) with ESMTP id A1FD44067D\n for <dev@dpdk.org>; Fri, 3 May 2024 15:59:07 +0200 (CEST)", "from fmviesa002.fm.intel.com ([10.60.135.142])\n by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 May 2024 06:59:07 -0700", "from silpixa00401119.ir.intel.com ([10.55.129.167])\n by fmviesa002.fm.intel.com with ESMTP; 03 May 2024 06:59:05 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714744747; x=1746280747;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=wNn3/X1uEL2WsN1j1Z3hNqckMZ8PtrNNkQ3lUAaL/1I=;\n b=HOEoK8HeFDuGlPOU2jI8fXYKf/oh3Wg+OHTcXnp9uQ8tnaTRkinQxEz7\n eMDbYdxbyQqg5YkQf8Ovcjy/ps1j55ABV6JgxtYAvM6ijmDfzS5oFNI/A\n e6qUskLs/cfeb0s1gxkkmlZHJvk9zxg7x+jwr2SRN3tMRnX+rymlWEbr9\n RbO3cNWyq1J8DWM84W307q7ujftvoc7M+E4T10vkTWjQafbGvXQwO4S/z\n 3dV+ep3cbjGMRPHhtebPY1MkPailHD/dFLNvADOOgQCLEMcLS7wPzMlUJ\n /M1ZRE7DuyDB84fnkFNkGdtKsKE74BlmqzLP7h/P/DksTm5Oy8mfSwwX3 w==;", "X-CSE-ConnectionGUID": [ "ySBoarreS7Gs3sd3t0ahSQ==", "UBVMyA65RMO+i9xSnt1kag==" ], "X-CSE-MsgGUID": [ "YRKQIR2CR/yEZgOBoYTMhw==", "SN1+7hLXTHubpSQK/Z7Qsw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11063\"; a=\"10714980\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"10714980\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"50642054\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Piotr Kwapulinski <piotr.kwapulinski@intel.com>,\n bruce.richardson@intel.com, vladimir.medvedkin@intel.com,\n Stefan Wegrzyn <stefan.wegrzyn@intel.com>,\n Jedrzej Jagielski <jedrzej.jagielski@intel.com>", "Subject": "[PATCH v2 23/27] net/ixgbe/base: add support for E610 device\n capabilities detection", "Date": "Fri, 3 May 2024 14:57:54 +0100", "Message-ID": "\n <9b5bd2935c671f829d2dd650cbeb7c50034695e0.1714744629.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1714744628.git.anatoly.burakov@intel.com>", "References": "<cover.1713964707.git.anatoly.burakov@intel.com>\n <cover.1714744628.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "From: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\n\nAdd low level support for E610 device capabilities detection. The\ncapabilities are discovered via the Admin Command Interface.\n\nSigned-off-by: Stefan Wegrzyn <stefan.wegrzyn@intel.com>\nSigned-off-by: Jedrzej Jagielski <jedrzej.jagielski@intel.com>\nSigned-off-by: Piotr Kwapulinski <piotr.kwapulinski@intel.com>\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_e610.c | 660 +++++++++++++++++++++++++++\n drivers/net/ixgbe/base/ixgbe_e610.h | 12 +\n drivers/net/ixgbe/base/ixgbe_osdep.h | 1 +\n drivers/net/ixgbe/base/ixgbe_type.h | 2 +\n 4 files changed, 675 insertions(+)", "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_e610.c b/drivers/net/ixgbe/base/ixgbe_e610.c\nindex a989fd741a..7f3eb0cf10 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.c\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.c\n@@ -567,3 +567,663 @@ void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res)\n \t\ttotal_delay++;\n \t}\n }\n+\n+/**\n+ * ixgbe_parse_common_caps - Parse common device/function capabilities\n+ * @hw: pointer to the HW struct\n+ * @caps: pointer to common capabilities structure\n+ * @elem: the capability element to parse\n+ * @prefix: message prefix for tracing capabilities\n+ *\n+ * Given a capability element, extract relevant details into the common\n+ * capability structure.\n+ *\n+ * Return: true if the capability matches one of the common capability ids,\n+ * false otherwise.\n+ */\n+static bool\n+ixgbe_parse_common_caps(struct ixgbe_hw *hw, struct ixgbe_hw_common_caps *caps,\n+\t\t\tstruct ixgbe_aci_cmd_list_caps_elem *elem,\n+\t\t\tconst char *prefix)\n+{\n+\tu32 logical_id = IXGBE_LE32_TO_CPU(elem->logical_id);\n+\tu32 phys_id = IXGBE_LE32_TO_CPU(elem->phys_id);\n+\tu32 number = IXGBE_LE32_TO_CPU(elem->number);\n+\tu16 cap = IXGBE_LE16_TO_CPU(elem->cap);\n+\tbool found = true;\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tswitch (cap) {\n+\tcase IXGBE_ACI_CAPS_VALID_FUNCTIONS:\n+\t\tcaps->valid_functions = number;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_VMDQ:\n+\t\tcaps->vmdq = (number == 1);\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_DCB:\n+\t\tcaps->dcb = (number == 1);\n+\t\tcaps->active_tc_bitmap = logical_id;\n+\t\tcaps->maxtc = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_RSS:\n+\t\tcaps->rss_table_size = number;\n+\t\tcaps->rss_table_entry_width = logical_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_RXQS:\n+\t\tcaps->num_rxq = number;\n+\t\tcaps->rxq_first_id = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_TXQS:\n+\t\tcaps->num_txq = number;\n+\t\tcaps->txq_first_id = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_MSIX:\n+\t\tcaps->num_msix_vectors = number;\n+\t\tcaps->msix_vector_first_id = phys_id;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_NVM_VER:\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_NVM_MGMT:\n+\t\tcaps->sec_rev_disabled =\n+\t\t\t(number & IXGBE_NVM_MGMT_SEC_REV_DISABLED) ?\n+\t\t\ttrue : false;\n+\t\tcaps->update_disabled =\n+\t\t\t(number & IXGBE_NVM_MGMT_UPDATE_DISABLED) ?\n+\t\t\ttrue : false;\n+\t\tcaps->nvm_unified_update =\n+\t\t\t(number & IXGBE_NVM_MGMT_UNIFIED_UPD_SUPPORT) ?\n+\t\t\ttrue : false;\n+\t\tcaps->netlist_auth =\n+\t\t\t(number & IXGBE_NVM_MGMT_NETLIST_AUTH_SUPPORT) ?\n+\t\t\ttrue : false;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_MAX_MTU:\n+\t\tcaps->max_mtu = number;\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_PCIE_RESET_AVOIDANCE:\n+\t\tcaps->pcie_reset_avoidance = (number > 0);\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_POST_UPDATE_RESET_RESTRICT:\n+\t\tcaps->reset_restrict_support = (number == 1);\n+\t\tbreak;\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0:\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG1:\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG2:\n+\tcase IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG3:\n+\t{\n+\t\tu8 index = cap - IXGBE_ACI_CAPS_EXT_TOPO_DEV_IMG0;\n+\n+\t\tcaps->ext_topo_dev_img_ver_high[index] = number;\n+\t\tcaps->ext_topo_dev_img_ver_low[index] = logical_id;\n+\t\tcaps->ext_topo_dev_img_part_num[index] =\n+\t\t\t(phys_id & IXGBE_EXT_TOPO_DEV_IMG_PART_NUM_M) >>\n+\t\t\tIXGBE_EXT_TOPO_DEV_IMG_PART_NUM_S;\n+\t\tcaps->ext_topo_dev_img_load_en[index] =\n+\t\t\t(phys_id & IXGBE_EXT_TOPO_DEV_IMG_LOAD_EN) != 0;\n+\t\tcaps->ext_topo_dev_img_prog_en[index] =\n+\t\t\t(phys_id & IXGBE_EXT_TOPO_DEV_IMG_PROG_EN) != 0;\n+\t\tbreak;\n+\t}\n+\n+\tcase IXGBE_ACI_CAPS_NEXT_CLUSTER_ID:\n+\t\tcaps->next_cluster_id_support = (number == 1);\n+\t\tDEBUGOUT2(\"%s: next_cluster_id_support = %d\\n\",\n+\t\t\t prefix, caps->next_cluster_id_support);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Not one of the recognized common capabilities */\n+\t\tfound = false;\n+\t}\n+\n+\treturn found;\n+}\n+\n+/**\n+ * ixgbe_hweight8 - count set bits among the 8 lowest bits\n+ * @w: variable storing set bits to count\n+ *\n+ * Return: the number of set bits among the 8 lowest bits in the provided value.\n+ */\n+static u8 ixgbe_hweight8(u32 w)\n+{\n+\tu8 hweight = 0, i;\n+\n+\tfor (i = 0; i < 8; i++)\n+\t\tif (w & (1 << i))\n+\t\t\thweight++;\n+\n+\treturn hweight;\n+}\n+\n+/**\n+ * ixgbe_hweight32 - count set bits among the 32 lowest bits\n+ * @w: variable storing set bits to count\n+ *\n+ * Return: the number of set bits among the 32 lowest bits in the\n+ * provided value.\n+ */\n+static u8 ixgbe_hweight32(u32 w)\n+{\n+\tu32 bitMask = 0x1, i;\n+\tu8 bitCnt = 0;\n+\n+\tfor (i = 0; i < 32; i++)\n+\t{\n+\t\tif (w & bitMask)\n+\t\t\tbitCnt++;\n+\n+\t\tbitMask = bitMask << 0x1;\n+\t}\n+\n+\treturn bitCnt;\n+}\n+\n+/**\n+ * ixgbe_func_id_to_logical_id - map from function id to logical pf id\n+ * @active_function_bitmap: active function bitmap\n+ * @pf_id: function number of device\n+ *\n+ * Return: the logical id of a function mapped by the provided pf_id.\n+ */\n+static int ixgbe_func_id_to_logical_id(u32 active_function_bitmap, u8 pf_id)\n+{\n+\tu8 logical_id = 0;\n+\tu8 i;\n+\n+\tfor (i = 0; i < pf_id; i++)\n+\t\tif (active_function_bitmap & BIT(i))\n+\t\t\tlogical_id++;\n+\n+\treturn logical_id;\n+}\n+\n+/**\n+ * ixgbe_parse_valid_functions_cap - Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_VALID_FUNCTIONS for device capabilities.\n+ */\n+static void\n+ixgbe_parse_valid_functions_cap(struct ixgbe_hw *hw,\n+\t\t\t\tstruct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\tstruct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tdev_p->num_funcs = ixgbe_hweight32(number);\n+\n+\thw->logical_pf_id = ixgbe_func_id_to_logical_id(number, hw->pf_id);\n+}\n+\n+/**\n+ * ixgbe_parse_vsi_dev_caps - Parse IXGBE_ACI_CAPS_VSI device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_VSI for device capabilities.\n+ */\n+static void ixgbe_parse_vsi_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tdev_p->num_vsi_allocd_to_host = number;\n+}\n+\n+/**\n+ * ixgbe_parse_1588_dev_caps - Parse IXGBE_ACI_CAPS_1588 device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_1588 for device capabilities.\n+ */\n+static void ixgbe_parse_1588_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tstruct ixgbe_ts_dev_info *info = &dev_p->ts_dev_info;\n+\tu32 logical_id = IXGBE_LE32_TO_CPU(cap->logical_id);\n+\tu32 phys_id = IXGBE_LE32_TO_CPU(cap->phys_id);\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tinfo->ena = ((number & IXGBE_TS_DEV_ENA_M) != 0);\n+\tdev_p->common_cap.ieee_1588 = info->ena;\n+\n+\tinfo->tmr0_owner = number & IXGBE_TS_TMR0_OWNR_M;\n+\tinfo->tmr0_owned = ((number & IXGBE_TS_TMR0_OWND_M) != 0);\n+\tinfo->tmr0_ena = ((number & IXGBE_TS_TMR0_ENA_M) != 0);\n+\n+\tinfo->tmr1_owner = (number & IXGBE_TS_TMR1_OWNR_M) >>\n+\t\t\t IXGBE_TS_TMR1_OWNR_S;\n+\tinfo->tmr1_owned = ((number & IXGBE_TS_TMR1_OWND_M) != 0);\n+\tinfo->tmr1_ena = ((number & IXGBE_TS_TMR1_ENA_M) != 0);\n+\n+\tinfo->ena_ports = logical_id;\n+\tinfo->tmr_own_map = phys_id;\n+\n+}\n+\n+/**\n+ * ixgbe_parse_fdir_dev_caps - Parse IXGBE_ACI_CAPS_FD device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse IXGBE_ACI_CAPS_FD for device capabilities.\n+ */\n+static void ixgbe_parse_fdir_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tdev_p->num_flow_director_fltr = number;\n+}\n+\n+/**\n+ * ixgbe_parse_dev_caps - Parse device capabilities\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @buf: buffer containing the device capability records\n+ * @cap_count: the number of capabilities\n+ *\n+ * Helper device to parse device (0x000B) capabilities list. For\n+ * capabilities shared between device and function, this relies on\n+ * ixgbe_parse_common_caps.\n+ *\n+ * Loop through the list of provided capabilities and extract the relevant\n+ * data into the device capabilities structured.\n+ */\n+static void ixgbe_parse_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_dev_caps *dev_p,\n+\t\t\t\t void *buf, u32 cap_count)\n+{\n+\tstruct ixgbe_aci_cmd_list_caps_elem *cap_resp;\n+\tu32 i;\n+\n+\tcap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf;\n+\n+\tmemset(dev_p, 0, sizeof(*dev_p));\n+\n+\tfor (i = 0; i < cap_count; i++) {\n+\t\tu16 cap = IXGBE_LE16_TO_CPU(cap_resp[i].cap);\n+\t\tbool found;\n+\n+\t\tfound = ixgbe_parse_common_caps(hw, &dev_p->common_cap,\n+\t\t\t\t\t &cap_resp[i], \"dev caps\");\n+\n+\t\tswitch (cap) {\n+\t\tcase IXGBE_ACI_CAPS_VALID_FUNCTIONS:\n+\t\t\tixgbe_parse_valid_functions_cap(hw, dev_p,\n+\t\t\t\t\t\t\t&cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_CAPS_VSI:\n+\t\t\tixgbe_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_CAPS_1588:\n+\t\t\tixgbe_parse_1588_dev_caps(hw, dev_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_CAPS_FD:\n+\t\t\tixgbe_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Don't list common capabilities as unknown */\n+\t\t\tif (!found)\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+}\n+\n+/**\n+ * ixgbe_get_num_per_func - determine number of resources per PF\n+ * @hw: pointer to the HW structure\n+ * @max: value to be evenly split between each PF\n+ *\n+ * Determine the number of valid functions by going through the bitmap returned\n+ * from parsing capabilities and use this to calculate the number of resources\n+ * per PF based on the max value passed in.\n+ *\n+ * Return: the number of resources per PF or 0, if no PH are available.\n+ */\n+static u32 ixgbe_get_num_per_func(struct ixgbe_hw *hw, u32 max)\n+{\n+\tu8 funcs;\n+\n+#define IXGBE_CAPS_VALID_FUNCS_M\t0xFF\n+\tfuncs = ixgbe_hweight8(hw->dev_caps.common_cap.valid_functions &\n+\t\t\t IXGBE_CAPS_VALID_FUNCS_M);\n+\n+\tif (!funcs)\n+\t\treturn 0;\n+\n+\treturn max / funcs;\n+}\n+\n+/**\n+ * ixgbe_parse_vsi_func_caps - Parse IXGBE_ACI_CAPS_VSI function caps\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @cap: pointer to the capability element to parse\n+ *\n+ * Extract function capabilities for IXGBE_ACI_CAPS_VSI.\n+ */\n+static void ixgbe_parse_vsi_func_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_func_caps *func_p,\n+\t\t\t\t struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tfunc_p->guar_num_vsi = ixgbe_get_num_per_func(hw, IXGBE_MAX_VSI);\n+}\n+\n+/**\n+ * ixgbe_parse_1588_func_caps - Parse IXGBE_ACI_CAPS_1588 function caps\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @cap: pointer to the capability element to parse\n+ *\n+ * Extract function capabilities for IXGBE_ACI_CAPS_1588.\n+ */\n+static void ixgbe_parse_1588_func_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_func_caps *func_p,\n+\t\t\t\t struct ixgbe_aci_cmd_list_caps_elem *cap)\n+{\n+\tstruct ixgbe_ts_func_info *info = &func_p->ts_func_info;\n+\tu32 number = IXGBE_LE32_TO_CPU(cap->number);\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tinfo->ena = ((number & IXGBE_TS_FUNC_ENA_M) != 0);\n+\tfunc_p->common_cap.ieee_1588 = info->ena;\n+\n+\tinfo->src_tmr_owned = ((number & IXGBE_TS_SRC_TMR_OWND_M) != 0);\n+\tinfo->tmr_ena = ((number & IXGBE_TS_TMR_ENA_M) != 0);\n+\tinfo->tmr_index_owned = ((number & IXGBE_TS_TMR_IDX_OWND_M) != 0);\n+\tinfo->tmr_index_assoc = ((number & IXGBE_TS_TMR_IDX_ASSOC_M) != 0);\n+\n+\tinfo->clk_freq = (number & IXGBE_TS_CLK_FREQ_M) >> IXGBE_TS_CLK_FREQ_S;\n+\tinfo->clk_src = ((number & IXGBE_TS_CLK_SRC_M) != 0);\n+\n+\tif (info->clk_freq < NUM_IXGBE_TIME_REF_FREQ) {\n+\t\tinfo->time_ref = (enum ixgbe_time_ref_freq)info->clk_freq;\n+\t} else {\n+\t\t/* Unknown clock frequency, so assume a (probably incorrect)\n+\t\t * default to avoid out-of-bounds look ups of frequency\n+\t\t * related information.\n+\t\t */\n+\t\tinfo->time_ref = IXGBE_TIME_REF_FREQ_25_000;\n+\t}\n+\n+}\n+/**\n+ * ixgbe_parse_func_caps - Parse function capabilities\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @buf: buffer containing the function capability records\n+ * @cap_count: the number of capabilities\n+ *\n+ * Helper function to parse function (0x000A) capabilities list. For\n+ * capabilities shared between device and function, this relies on\n+ * ixgbe_parse_common_caps.\n+ *\n+ * Loop through the list of provided capabilities and extract the relevant\n+ * data into the function capabilities structured.\n+ */\n+static void ixgbe_parse_func_caps(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_hw_func_caps *func_p,\n+\t\t\t\t void *buf, u32 cap_count)\n+{\n+\tstruct ixgbe_aci_cmd_list_caps_elem *cap_resp;\n+\tu32 i;\n+\n+\tcap_resp = (struct ixgbe_aci_cmd_list_caps_elem *)buf;\n+\n+\tmemset(func_p, 0, sizeof(*func_p));\n+\n+\tfor (i = 0; i < cap_count; i++) {\n+\t\tu16 cap = IXGBE_LE16_TO_CPU(cap_resp[i].cap);\n+\n+\t\tixgbe_parse_common_caps(hw, &func_p->common_cap,\n+\t\t\t\t\t&cap_resp[i], \"func caps\");\n+\n+\t\tswitch (cap) {\n+\t\tcase IXGBE_ACI_CAPS_VSI:\n+\t\t\tixgbe_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tcase IXGBE_ACI_CAPS_1588:\n+\t\t\tixgbe_parse_1588_func_caps(hw, func_p, &cap_resp[i]);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\t/* Don't list common capabilities as unknown */\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+}\n+\n+/**\n+ * ixgbe_aci_list_caps - query function/device capabilities\n+ * @hw: pointer to the HW struct\n+ * @buf: a buffer to hold the capabilities\n+ * @buf_size: size of the buffer\n+ * @cap_count: if not NULL, set to the number of capabilities reported\n+ * @opc: capabilities type to discover, device or function\n+ *\n+ * Get the function (0x000A) or device (0x000B) capabilities description from\n+ * firmware and store it in the buffer.\n+ *\n+ * If the cap_count pointer is not NULL, then it is set to the number of\n+ * capabilities firmware will report. Note that if the buffer size is too\n+ * small, it is possible the command will return IXGBE_ERR_OUT_OF_MEM. The\n+ * cap_count will still be updated in this case. It is recommended that the\n+ * buffer size be set to IXGBE_ACI_MAX_BUFFER_SIZE (the largest possible\n+ * buffer that firmware could return) to avoid this.\n+ *\n+ * Return: the exit code of the operation.\n+ * Exit code of IXGBE_ERR_OUT_OF_MEM means the buffer size is too small.\n+ */\n+s32 ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size,\n+\t\t\tu32 *cap_count, enum ixgbe_aci_opc opc)\n+{\n+\tstruct ixgbe_aci_cmd_list_caps *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.get_cap;\n+\n+\tif (opc != ixgbe_aci_opc_list_func_caps &&\n+\t opc != ixgbe_aci_opc_list_dev_caps)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, opc);\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, buf, buf_size);\n+\n+\tif (cap_count)\n+\t\t*cap_count = IXGBE_LE32_TO_CPU(cmd->count);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_discover_dev_caps - Read and extract device capabilities\n+ * @hw: pointer to the hardware structure\n+ * @dev_caps: pointer to device capabilities structure\n+ *\n+ * Read the device capabilities and extract them into the dev_caps structure\n+ * for later use.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_discover_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t struct ixgbe_hw_dev_caps *dev_caps)\n+{\n+\tu32 status, cap_count = 0;\n+\tu8 *cbuf = NULL;\n+\n+\tcbuf = (u8*)ixgbe_malloc(hw, IXGBE_ACI_MAX_BUFFER_SIZE);\n+\tif (!cbuf)\n+\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\t/* Although the driver doesn't know the number of capabilities the\n+\t * device will return, we can simply send a 4KB buffer, the maximum\n+\t * possible size that firmware can return.\n+\t */\n+\tcap_count = IXGBE_ACI_MAX_BUFFER_SIZE /\n+\t\t sizeof(struct ixgbe_aci_cmd_list_caps_elem);\n+\n+\tstatus = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE,\n+\t\t\t\t &cap_count,\n+\t\t\t\t ixgbe_aci_opc_list_dev_caps);\n+\tif (!status)\n+\t\tixgbe_parse_dev_caps(hw, dev_caps, cbuf, cap_count);\n+\n+\tif (cbuf)\n+\t\tixgbe_free(hw, cbuf);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_discover_func_caps - Read and extract function capabilities\n+ * @hw: pointer to the hardware structure\n+ * @func_caps: pointer to function capabilities structure\n+ *\n+ * Read the function capabilities and extract them into the func_caps structure\n+ * for later use.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_discover_func_caps(struct ixgbe_hw *hw,\n+\t\t\t struct ixgbe_hw_func_caps *func_caps)\n+{\n+\tu32 cap_count = 0;\n+\tu8 *cbuf = NULL;\n+\ts32 status;\n+\n+\tcbuf = (u8*)ixgbe_malloc(hw, IXGBE_ACI_MAX_BUFFER_SIZE);\n+\tif(!cbuf)\n+\t\treturn IXGBE_ERR_OUT_OF_MEM;\n+\t/* Although the driver doesn't know the number of capabilities the\n+\t * device will return, we can simply send a 4KB buffer, the maximum\n+\t * possible size that firmware can return.\n+\t */\n+\tcap_count = IXGBE_ACI_MAX_BUFFER_SIZE /\n+\t\t sizeof(struct ixgbe_aci_cmd_list_caps_elem);\n+\n+\tstatus = ixgbe_aci_list_caps(hw, cbuf, IXGBE_ACI_MAX_BUFFER_SIZE,\n+\t\t\t\t &cap_count,\n+\t\t\t\t ixgbe_aci_opc_list_func_caps);\n+\tif (!status)\n+\t\tixgbe_parse_func_caps(hw, func_caps, cbuf, cap_count);\n+\n+\tif (cbuf)\n+\t\tixgbe_free(hw, cbuf);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_disable_rxen - disable RX\n+ * @hw: pointer to the HW struct\n+ *\n+ * Request a safe disable of Receive Enable using ACI command (0x000C).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_disable_rxen(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_disable_rxen *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tUNREFERENCED_1PARAMETER(hw);\n+\n+\tcmd = &desc.params.disable_rxen;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_disable_rxen);\n+\n+\tcmd->lport_num = (u8)hw->bus.func;\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_get_phy_caps - returns PHY capabilities\n+ * @hw: pointer to the HW struct\n+ * @qual_mods: report qualified modules\n+ * @report_mode: report mode capabilities\n+ * @pcaps: structure for PHY capabilities to be filled\n+ *\n+ * Returns the various PHY capabilities supported on the Port\n+ * using ACI command (0x0600).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,\n+\t\t\t struct ixgbe_aci_cmd_get_phy_caps_data *pcaps)\n+{\n+\tstruct ixgbe_aci_cmd_get_phy_caps *cmd;\n+\tu16 pcaps_size = sizeof(*pcaps);\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.get_phy;\n+\n+\tif (!pcaps || (report_mode & ~IXGBE_ACI_REPORT_MODE_M))\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_phy_caps);\n+\n+\tif (qual_mods)\n+\t\tcmd->param0 |= IXGBE_CPU_TO_LE16(IXGBE_ACI_GET_PHY_RQM);\n+\n+\tcmd->param0 |= IXGBE_CPU_TO_LE16(report_mode);\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, pcaps, pcaps_size);\n+\n+\tif (status == IXGBE_SUCCESS &&\n+\t report_mode == IXGBE_ACI_REPORT_TOPO_CAP_MEDIA) {\n+\t\thw->phy.phy_type_low = IXGBE_LE64_TO_CPU(pcaps->phy_type_low);\n+\t\thw->phy.phy_type_high = IXGBE_LE64_TO_CPU(pcaps->phy_type_high);\n+\t\tmemcpy(hw->link.link_info.module_type, &pcaps->module_type,\n+\t\t\t sizeof(hw->link.link_info.module_type));\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data\n+ * @caps: PHY ability structure to copy data from\n+ * @cfg: PHY configuration structure to copy data to\n+ *\n+ * Helper function to copy data from PHY capabilities data structure\n+ * to PHY configuration data structure\n+ */\n+void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,\n+\t\t\t\tstruct ixgbe_aci_cmd_set_phy_cfg_data *cfg)\n+{\n+\tif (!caps || !cfg)\n+\t\treturn;\n+\n+\tmemset(cfg, 0, sizeof(*cfg));\n+\tcfg->phy_type_low = caps->phy_type_low;\n+\tcfg->phy_type_high = caps->phy_type_high;\n+\tcfg->caps = caps->caps;\n+\tcfg->low_power_ctrl_an = caps->low_power_ctrl_an;\n+\tcfg->eee_cap = caps->eee_cap;\n+\tcfg->eeer_value = caps->eeer_value;\n+\tcfg->link_fec_opt = caps->link_fec_options;\n+\tcfg->module_compliance_enforcement =\n+\t\tcaps->module_compliance_enforcement;\n+}\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.h b/drivers/net/ixgbe/base/ixgbe_e610.h\nindex aeaa75af37..5f78f970c4 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.h\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.h\n@@ -18,8 +18,20 @@ s32 ixgbe_aci_get_event(struct ixgbe_hw *hw, struct ixgbe_aci_event *e,\n \n void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode);\n \n+s32 ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw);\n s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n \t\t enum ixgbe_aci_res_access_type access, u32 timeout);\n void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res);\n+s32 ixgbe_aci_list_caps(struct ixgbe_hw *hw, void *buf, u16 buf_size,\n+\t\t\tu32 *cap_count, enum ixgbe_aci_opc opc);\n+s32 ixgbe_discover_dev_caps(struct ixgbe_hw *hw,\n+\t\t\t struct ixgbe_hw_dev_caps *dev_caps);\n+s32 ixgbe_discover_func_caps(struct ixgbe_hw* hw,\n+\t\t\t struct ixgbe_hw_func_caps* func_caps);\n+s32 ixgbe_aci_disable_rxen(struct ixgbe_hw *hw);\n+s32 ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,\n+\t\t\t struct ixgbe_aci_cmd_get_phy_caps_data *pcaps);\n+void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,\n+\t\t\t\tstruct ixgbe_aci_cmd_set_phy_cfg_data *cfg);\n \n #endif /* _IXGBE_E610_H_ */\ndiff --git a/drivers/net/ixgbe/base/ixgbe_osdep.h b/drivers/net/ixgbe/base/ixgbe_osdep.h\nindex b3266a3c77..e832a7bec8 100644\n--- a/drivers/net/ixgbe/base/ixgbe_osdep.h\n+++ b/drivers/net/ixgbe/base/ixgbe_osdep.h\n@@ -82,6 +82,7 @@ enum {\n #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)\n #define IXGBE_LE16_TO_CPU(_i) rte_le_to_cpu_16(_i)\n #define IXGBE_LE32_TO_CPU(_i) rte_le_to_cpu_32(_i)\n+#define IXGBE_LE64_TO_CPU(_i) rte_le_to_cpu_64(_i)\n #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)\n #define IXGBE_CPU_TO_BE16(_i) rte_cpu_to_be_16(_i)\n #define IXGBE_CPU_TO_BE32(_i) rte_cpu_to_be_32(_i)\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex fe7411541e..5ba15fc721 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -4190,6 +4190,8 @@ struct ixgbe_hw {\n \tu16 subsystem_device_id;\n \tu16 subsystem_vendor_id;\n \tu8 revision_id;\n+\tu8 pf_id;\n+\tu8 logical_pf_id;\n \tbool adapter_stopped;\n \tint api_version;\n \tbool force_full_reset;\n", "prefixes": [ "v2", "23/27" ] }