Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/139855/?format=api
{ "id": 139855, "url": "http://patchwork.dpdk.org/api/patches/139855/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/93795571c98db29f975ee12675246b5169c7082e.1714744629.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<93795571c98db29f975ee12675246b5169c7082e.1714744629.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/93795571c98db29f975ee12675246b5169c7082e.1714744629.git.anatoly.burakov@intel.com", "date": "2024-05-03T13:57:58", "name": "[v2,27/27] net/ixgbe/base: add various miscellaneous features", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4e18be99b08ae5282c64e7c14dd3ce3a2bc5b64e", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Burakov, Anatoly", "email": "anatoly.burakov@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/93795571c98db29f975ee12675246b5169c7082e.1714744629.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 31875, "url": "http://patchwork.dpdk.org/api/series/31875/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31875", "date": "2024-05-03T13:57:31", "name": "Update IXGBE base driver", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31875/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139855/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/139855/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 0FB4E43F76;\n\tFri, 3 May 2024 16:01:45 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 86A1C41104;\n\tFri, 3 May 2024 15:59:20 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.15])\n by mails.dpdk.org (Postfix) with ESMTP id 2896D4064A\n for <dev@dpdk.org>; Fri, 3 May 2024 15:59:18 +0200 (CEST)", "from fmviesa002.fm.intel.com ([10.60.135.142])\n by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 May 2024 06:59:17 -0700", "from silpixa00401119.ir.intel.com ([10.55.129.167])\n by fmviesa002.fm.intel.com with ESMTP; 03 May 2024 06:59:16 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714744758; x=1746280758;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=tdRFVxmHRaMb/Zr4Y7K4k+qKm/dpQbPQI99wkaffQfQ=;\n b=frhh6GNCo1iTwZHlDGQtzjbEg5DEgm4FsShwHzl0FHi+6Blly9Na0R13\n +b9+FtZKzYl83OSUzxFbHicMROHjxNFNIQDBl9O6x78Ezw1PmGH+Y27b3\n AUWYbN2iv+ID4KpafxYV3NRY2xkcSvFg5ssFfgqov2XeW+1X8gNepFmCz\n 3h49cfuJTT64ag0TVm7bfDdjTm9a4XSSaGHovFP3q+qMtKaiQ7DlqJRuo\n S15PcbS2aPGrRdnU3Kn8jsLkTEF0/7K/rd0RxIhD9fdgZp4gPyraH8Wq6\n qH2nZmFvkneM40VpoU4J+jPSVE52qDfHazNW1d4EcbSypCGQl/tfAKwzO g==;", "X-CSE-ConnectionGUID": [ "rz4IIWapQoawGH2e9ShAGw==", "GcwmhRi5QQCxvM81FKY0Cg==" ], "X-CSE-MsgGUID": [ "HDRp7CmmTe68QcoI42ziCg==", "RTtru96FQ9m4Sl/lP5Ve7Q==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11063\"; a=\"10714989\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"10714989\"", "E=Sophos;i=\"6.07,251,1708416000\"; d=\"scan'208\";a=\"50642075\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "bruce.richardson@intel.com,\n\tvladimir.medvedkin@intel.com", "Subject": "[PATCH v2 27/27] net/ixgbe/base: add various miscellaneous features", "Date": "Fri, 3 May 2024 14:57:58 +0100", "Message-ID": "\n <93795571c98db29f975ee12675246b5169c7082e.1714744629.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<cover.1714744628.git.anatoly.burakov@intel.com>", "References": "<cover.1713964707.git.anatoly.burakov@intel.com>\n <cover.1714744628.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add various features to the base driver that are not specifically\nabout packet I/O but are present in the shared code snapshot.\n\nAlso, update documentation to reflect new base code snapshot version,\nas well as document new hardware support.\n\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n doc/guides/rel_notes/release_24_07.rst | 4 +\n drivers/net/ixgbe/base/README | 6 +-\n drivers/net/ixgbe/base/ixgbe_e610.c | 1089 ++++++++++++++++++++++\n drivers/net/ixgbe/base/ixgbe_e610.h | 58 ++\n drivers/net/ixgbe/base/ixgbe_type_e610.h | 402 ++++++++\n 5 files changed, 1557 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/rel_notes/release_24_07.rst b/doc/guides/rel_notes/release_24_07.rst\nindex a69f24cf99..9499352c46 100644\n--- a/doc/guides/rel_notes/release_24_07.rst\n+++ b/doc/guides/rel_notes/release_24_07.rst\n@@ -55,6 +55,10 @@ New Features\n Also, make sure to start the actual text at the margin.\n =======================================================\n \n+* **Updated IXGBE base code.**\n+\n+ * Updated shared code to more recent version.\n+ * Added support for E610 device family.\n \n Removed Items\n -------------\ndiff --git a/drivers/net/ixgbe/base/README b/drivers/net/ixgbe/base/README\nindex 2c74693924..98353ba26f 100644\n--- a/drivers/net/ixgbe/base/README\n+++ b/drivers/net/ixgbe/base/README\n@@ -1,12 +1,12 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n- * Copyright(c) 2010-2020 Intel Corporation\n+ * Copyright(c) 2010-2024 Intel Corporation\n */\n \n Intel® IXGBE driver\n ===================\n \n This directory contains source code of FreeBSD ixgbe driver of version\n-not-released-cid-ixgbe.2020.06.09.tar.gz released by the team which develop\n+not-released-cid-ixgbe.2024.04.24.tar.gz released by the team which develop\n basic drivers for any ixgbe NIC. The sub-directory of base/\n contains the original source package.\n This driver is valid for the product(s) listed below\n@@ -24,6 +24,7 @@ This driver is valid for the product(s) listed below\n * Intel® Ethernet Server Adapter X520 Series\n * Intel® Ethernet Server Adapter X520-T2\n * Intel® Ethernet Controller X550 Series\n+* Intel® Ethernet Controller E610 Series\n \n Updating the driver\n ===================\n@@ -32,3 +33,4 @@ NOTE: The source code in this directory should not be modified apart from\n the following file(s):\n \n ixgbe_osdep.h\n+ ixgbe_osdep.c\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.c b/drivers/net/ixgbe/base/ixgbe_e610.c\nindex 6618c21cef..ae9bc70de8 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.c\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.c\n@@ -1207,6 +1207,25 @@ s32 ixgbe_discover_func_caps(struct ixgbe_hw *hw,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_get_caps - get info about the HW\n+ * @hw: pointer to the hardware structure\n+ *\n+ * Retrieve both device and function capabilities.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_caps(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\n+\tstatus = ixgbe_discover_dev_caps(hw, &hw->dev_caps);\n+\tif (status)\n+\t\treturn status;\n+\n+\treturn ixgbe_discover_func_caps(hw, &hw->func_caps);\n+}\n+\n /**\n * ixgbe_aci_disable_rxen - disable RX\n * @hw: pointer to the HW struct\n@@ -1275,6 +1294,45 @@ s32 ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_phy_caps_equals_cfg - check if capabilities match the PHY config\n+ * @phy_caps: PHY capabilities\n+ * @phy_cfg: PHY configuration\n+ *\n+ * Helper function to determine if PHY capabilities match PHY\n+ * configuration\n+ *\n+ * Return: true if PHY capabilities match PHY configuration.\n+ */\n+bool\n+ixgbe_phy_caps_equals_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *phy_caps,\n+\t\t\t struct ixgbe_aci_cmd_set_phy_cfg_data *phy_cfg)\n+{\n+\tu8 caps_mask, cfg_mask;\n+\n+\tif (!phy_caps || !phy_cfg)\n+\t\treturn false;\n+\n+\t/* These bits are not common between capabilities and configuration.\n+\t * Do not use them to determine equality.\n+\t */\n+\tcaps_mask = IXGBE_ACI_PHY_CAPS_MASK & ~(IXGBE_ACI_PHY_AN_MODE |\n+\t\t\t\t\t IXGBE_ACI_PHY_EN_MOD_QUAL);\n+\tcfg_mask = IXGBE_ACI_PHY_ENA_VALID_MASK &\n+\t\t ~IXGBE_ACI_PHY_ENA_AUTO_LINK_UPDT;\n+\n+\tif (phy_caps->phy_type_low != phy_cfg->phy_type_low ||\n+\t phy_caps->phy_type_high != phy_cfg->phy_type_high ||\n+\t ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) ||\n+\t phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an ||\n+\t phy_caps->eee_cap != phy_cfg->eee_cap ||\n+\t phy_caps->eeer_value != phy_cfg->eeer_value ||\n+\t phy_caps->link_fec_options != phy_cfg->link_fec_opt)\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n /**\n * ixgbe_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data\n * @caps: PHY ability structure to copy data from\n@@ -1726,6 +1784,239 @@ s32 ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,\n \treturn IXGBE_SUCCESS;\n }\n \n+/**\n+ * ixgbe_aci_get_netlist_node_pin - get a node pin handle\n+ * @hw: pointer to the hw struct\n+ * @cmd: get_link_topo_pin AQ structure\n+ * @node_handle: output node handle parameter if node found\n+ *\n+ * Get the netlist node pin and assign it to\n+ * the provided handle using ACI command (0x06E1).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_netlist_node_pin(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_aci_cmd_get_link_topo_pin *cmd,\n+\t\t\t\t u16 *node_handle)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_link_topo_pin);\n+\tdesc.params.get_link_topo_pin = *cmd;\n+\n+\tif (ixgbe_aci_send_cmd(hw, &desc, NULL, 0))\n+\t\treturn IXGBE_ERR_NOT_SUPPORTED;\n+\n+\tif (node_handle)\n+\t\t*node_handle =\n+\t\t\tIXGBE_LE16_TO_CPU(desc.params.get_link_topo_pin.addr.handle);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_find_netlist_node - find a node handle\n+ * @hw: pointer to the hw struct\n+ * @node_type_ctx: type of netlist node to look for\n+ * @node_part_number: node part number to look for\n+ * @node_handle: output parameter if node found - optional\n+ *\n+ * Find and return the node handle for a given node type and part number in the\n+ * netlist. When found IXGBE_SUCCESS is returned, IXGBE_ERR_NOT_SUPPORTED\n+ * otherwise. If @node_handle provided, it would be set to found node handle.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_find_netlist_node(struct ixgbe_hw *hw, u8 node_type_ctx,\n+\t\t\t u8 node_part_number, u16 *node_handle)\n+{\n+\tstruct ixgbe_aci_cmd_get_link_topo cmd;\n+\tu8 rec_node_part_number;\n+\tu16 rec_node_handle;\n+\ts32 status;\n+\tu8 idx;\n+\n+\tfor (idx = 0; idx < IXGBE_MAX_NETLIST_SIZE; idx++) {\n+\t\tmemset(&cmd, 0, sizeof(cmd));\n+\n+\t\tcmd.addr.topo_params.node_type_ctx =\n+\t\t\t(node_type_ctx << IXGBE_ACI_LINK_TOPO_NODE_TYPE_S);\n+\t\tcmd.addr.topo_params.index = idx;\n+\n+\t\tstatus = ixgbe_aci_get_netlist_node(hw, &cmd,\n+\t\t\t\t\t\t &rec_node_part_number,\n+\t\t\t\t\t\t &rec_node_handle);\n+\t\tif (status)\n+\t\t\treturn status;\n+\n+\t\tif (rec_node_part_number == node_part_number) {\n+\t\t\tif (node_handle)\n+\t\t\t\t*node_handle = rec_node_handle;\n+\t\t\treturn IXGBE_SUCCESS;\n+\t\t}\n+\t}\n+\n+\treturn IXGBE_ERR_NOT_SUPPORTED;\n+}\n+\n+/**\n+ * ixgbe_aci_read_i2c - read I2C register value\n+ * @hw: pointer to the hw struct\n+ * @topo_addr: topology address for a device to communicate with\n+ * @bus_addr: 7-bit I2C bus address\n+ * @addr: I2C memory address (I2C offset) with up to 16 bits\n+ * @params: I2C parameters: bit [7] - Repeated start,\n+ *\t\t\t\t bits [6:5] data offset size,\n+ *\t\t\t bit [4] - I2C address type, bits [3:0] - data size\n+ *\t\t\t\t to read (0-16 bytes)\n+ * @data: pointer to data (0 to 16 bytes) to be read from the I2C device\n+ *\n+ * Read the value of the I2C pin register using ACI command (0x06E2).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_read_i2c(struct ixgbe_hw *hw,\n+\t\t struct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t u16 bus_addr, __le16 addr, u8 params, u8 *data)\n+{\n+\tstruct ixgbe_aci_desc desc = { 0 };\n+\tstruct ixgbe_aci_cmd_i2c *cmd;\n+\tu8 data_size;\n+\ts32 status;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_read_i2c);\n+\tcmd = &desc.params.read_write_i2c;\n+\n+\tif (!data)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tdata_size = (params & IXGBE_ACI_I2C_DATA_SIZE_M) >>\n+\t\t IXGBE_ACI_I2C_DATA_SIZE_S;\n+\n+\tcmd->i2c_bus_addr = IXGBE_CPU_TO_LE16(bus_addr);\n+\tcmd->topo_addr = topo_addr;\n+\tcmd->i2c_params = params;\n+\tcmd->i2c_addr = addr;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (!status) {\n+\t\tstruct ixgbe_aci_cmd_read_i2c_resp *resp;\n+\t\tu8 i;\n+\n+\t\tresp = &desc.params.read_i2c_resp;\n+\t\tfor (i = 0; i < data_size; i++) {\n+\t\t\t*data = resp->i2c_data[i];\n+\t\t\tdata++;\n+\t\t}\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_write_i2c - write a value to I2C register\n+ * @hw: pointer to the hw struct\n+ * @topo_addr: topology address for a device to communicate with\n+ * @bus_addr: 7-bit I2C bus address\n+ * @addr: I2C memory address (I2C offset) with up to 16 bits\n+ * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size\n+ *\t\t\t\t to write (0-7 bytes)\n+ * @data: pointer to data (0 to 4 bytes) to be written to the I2C device\n+ *\n+ * Write a value to the I2C pin register using ACI command (0x06E3).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_write_i2c(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t\tu16 bus_addr, __le16 addr, u8 params, u8 *data)\n+{\n+\tstruct ixgbe_aci_desc desc = { 0 };\n+\tstruct ixgbe_aci_cmd_i2c *cmd;\n+\tu8 i, data_size;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_write_i2c);\n+\tcmd = &desc.params.read_write_i2c;\n+\n+\tdata_size = (params & IXGBE_ACI_I2C_DATA_SIZE_M) >>\n+\t\t IXGBE_ACI_I2C_DATA_SIZE_S;\n+\n+\t/* data_size limited to 4 */\n+\tif (data_size > 4)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tcmd->i2c_bus_addr = IXGBE_CPU_TO_LE16(bus_addr);\n+\tcmd->topo_addr = topo_addr;\n+\tcmd->i2c_params = params;\n+\tcmd->i2c_addr = addr;\n+\n+\tfor (i = 0; i < data_size; i++) {\n+\t\tcmd->i2c_data[i] = *data;\n+\t\tdata++;\n+\t}\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_set_gpio - set GPIO pin state\n+ * @hw: pointer to the hw struct\n+ * @gpio_ctrl_handle: GPIO controller node handle\n+ * @pin_idx: IO Number of the GPIO that needs to be set\n+ * @value: SW provide IO value to set in the LSB\n+ *\n+ * Set the GPIO pin state that is a part of the topology\n+ * using ACI command (0x06EC).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_set_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t bool value)\n+{\n+\tstruct ixgbe_aci_cmd_gpio *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_set_gpio);\n+\tcmd = &desc.params.read_write_gpio;\n+\tcmd->gpio_ctrl_handle = IXGBE_CPU_TO_LE16(gpio_ctrl_handle);\n+\tcmd->gpio_num = pin_idx;\n+\tcmd->gpio_val = value ? 1 : 0;\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_get_gpio - get GPIO pin state\n+ * @hw: pointer to the hw struct\n+ * @gpio_ctrl_handle: GPIO controller node handle\n+ * @pin_idx: IO Number of the GPIO that needs to be set\n+ * @value: IO value read\n+ *\n+ * Get the value of a GPIO signal which is part of the topology\n+ * using ACI command (0x06ED).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t bool *value)\n+{\n+\tstruct ixgbe_aci_cmd_gpio *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_get_gpio);\n+\tcmd = &desc.params.read_write_gpio;\n+\tcmd->gpio_ctrl_handle = IXGBE_CPU_TO_LE16(gpio_ctrl_handle);\n+\tcmd->gpio_num = pin_idx;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (status)\n+\t\treturn status;\n+\n+\t*value = !!cmd->gpio_val;\n+\treturn IXGBE_SUCCESS;\n+}\n+\n /**\n * ixgbe_aci_sff_eeprom - read/write SFF EEPROM\n * @hw: pointer to the HW struct\n@@ -1772,6 +2063,72 @@ s32 ixgbe_aci_sff_eeprom(struct ixgbe_hw *hw, u16 lport, u8 bus_addr,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_aci_prog_topo_dev_nvm - program Topology Device NVM\n+ * @hw: pointer to the hardware structure\n+ * @topo_params: pointer to structure storing topology parameters for a device\n+ *\n+ * Program Topology Device NVM using ACI command (0x06F2).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_prog_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params)\n+{\n+\tstruct ixgbe_aci_cmd_prog_topo_dev_nvm *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\n+\tcmd = &desc.params.prog_topo_dev_nvm;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_prog_topo_dev_nvm);\n+\n+\tmemcpy(&cmd->topo_params, topo_params, sizeof(*topo_params));\n+\n+\treturn ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+}\n+\n+/**\n+ * ixgbe_aci_read_topo_dev_nvm - read Topology Device NVM\n+ * @hw: pointer to the hardware structure\n+ * @topo_params: pointer to structure storing topology parameters for a device\n+ * @start_address: byte offset in the topology device NVM\n+ * @data: pointer to data buffer\n+ * @data_size: number of bytes to be read from the topology device NVM\n+ * Read Topology Device NVM (0x06F3)\n+ *\n+ * Read Topology of Device NVM using ACI command (0x06F3).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_read_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params,\n+\t\t\tu32 start_address, u8 *data, u8 data_size)\n+{\n+\tstruct ixgbe_aci_cmd_read_topo_dev_nvm *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tif (!data || data_size == 0 ||\n+\t data_size > IXGBE_ACI_READ_TOPO_DEV_NVM_DATA_READ_SIZE)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tcmd = &desc.params.read_topo_dev_nvm;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_read_topo_dev_nvm);\n+\n+\tdesc.datalen = IXGBE_CPU_TO_LE16(data_size);\n+\tmemcpy(&cmd->topo_params, topo_params, sizeof(*topo_params));\n+\tcmd->start_address = IXGBE_CPU_TO_LE32(start_address);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (status)\n+\t\treturn status;\n+\n+\tmemcpy(data, cmd->data_read, data_size);\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n /**\n * ixgbe_acquire_nvm - Generic request for acquiring the NVM ownership\n * @hw: pointer to the HW structure\n@@ -1896,6 +2253,37 @@ s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw)\n \treturn status;\n }\n \n+/**\n+ * ixgbe_nvm_recalculate_checksum - recalculate checksum\n+ * @hw: pointer to the HW struct\n+ *\n+ * Recalculate NVM PFA checksum using ACI command (0x0706).\n+ * The function acquires and then releases the NVM ownership.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_nvm_recalculate_checksum(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_cmd_nvm_checksum *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tcmd = &desc.params.nvm_checksum;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_checksum);\n+\tcmd->flags = IXGBE_ACI_NVM_CHECKSUM_RECALC;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n /**\n * ixgbe_get_flash_bank_offset - Get offset into requested flash bank\n * @hw: pointer to the HW structure\n@@ -2100,6 +2488,60 @@ static s32 ixgbe_read_nvm_sr_copy(struct ixgbe_hw *hw,\n \treturn ixgbe_read_nvm_module(hw, bank, hdr_len + offset, data);\n }\n \n+/**\n+ * ixgbe_get_nvm_minsrevs - Get the minsrevs values from flash\n+ * @hw: pointer to the HW struct\n+ * @minsrevs: structure to store NVM and OROM minsrev values\n+ *\n+ * Read the Minimum Security Revision TLV and extract\n+ * the revision values from the flash image\n+ * into a readable structure for processing.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_nvm_minsrevs(struct ixgbe_hw *hw,\n+\t\t\t struct ixgbe_minsrev_info *minsrevs)\n+{\n+\tstruct ixgbe_aci_cmd_nvm_minsrev data;\n+\ts32 status;\n+\tu16 valid;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\tstatus = ixgbe_aci_read_nvm(hw, IXGBE_ACI_NVM_MINSREV_MOD_ID,\n+\t\t\t\t 0, sizeof(data), &data,\n+\t\t\t\t true, false);\n+\n+\tixgbe_release_nvm(hw);\n+\n+\tif (status)\n+\t\treturn status;\n+\n+\tvalid = IXGBE_LE16_TO_CPU(data.validity);\n+\n+\t/* Extract NVM minimum security revision */\n+\tif (valid & IXGBE_ACI_NVM_MINSREV_NVM_VALID) {\n+\t\tu16 minsrev_l = IXGBE_LE16_TO_CPU(data.nvm_minsrev_l);\n+\t\tu16 minsrev_h = IXGBE_LE16_TO_CPU(data.nvm_minsrev_h);\n+\n+\t\tminsrevs->nvm = minsrev_h << 16 | minsrev_l;\n+\t\tminsrevs->nvm_valid = true;\n+\t}\n+\n+\t/* Extract the OROM minimum security revision */\n+\tif (valid & IXGBE_ACI_NVM_MINSREV_OROM_VALID) {\n+\t\tu16 minsrev_l = IXGBE_LE16_TO_CPU(data.orom_minsrev_l);\n+\t\tu16 minsrev_h = IXGBE_LE16_TO_CPU(data.orom_minsrev_h);\n+\n+\t\tminsrevs->orom = minsrev_h << 16 | minsrev_l;\n+\t\tminsrevs->orom_valid = true;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n /**\n * ixgbe_get_nvm_srev - Read the security revision from the NVM CSS header\n * @hw: pointer to the HW struct\n@@ -2175,6 +2617,22 @@ static s32 ixgbe_get_nvm_ver_info(struct ixgbe_hw *hw,\n \treturn IXGBE_SUCCESS;\n }\n \n+/**\n+ * ixgbe_get_inactive_nvm_ver - Read Option ROM version from the inactive bank\n+ * @hw: pointer to the HW structure\n+ * @nvm: storage for Option ROM version information\n+ *\n+ * Reads the NVM EETRACK ID, Map version, and security revision of the\n+ * inactive NVM bank. Used to access version data for a pending update that\n+ * has not yet been activated.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm)\n+{\n+\treturn ixgbe_get_nvm_ver_info(hw, IXGBE_INACTIVE_FLASH_BANK, nvm);\n+}\n+\n /**\n * ixgbe_get_active_nvm_ver - Read Option ROM version from the active bank\n * @hw: pointer to the HW structure\n@@ -2190,6 +2648,308 @@ s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm)\n \treturn ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK, nvm);\n }\n \n+/**\n+ * ixgbe_read_sr_pointer - Read the value of a Shadow RAM pointer word\n+ * @hw: pointer to the HW structure\n+ * @offset: the word offset of the Shadow RAM word to read\n+ * @pointer: pointer value read from Shadow RAM\n+ *\n+ * Read the given Shadow RAM word, and convert it to a pointer value specified\n+ * in bytes. This function assumes the specified offset is a valid pointer\n+ * word.\n+ *\n+ * Each pointer word specifies whether it is stored in word size or 4KB\n+ * sector size by using the highest bit. The reported pointer value will be in\n+ * bytes, intended for flat NVM reads.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_sr_pointer(struct ixgbe_hw *hw, u16 offset, u32 *pointer)\n+{\n+\ts32 status;\n+\tu16 value;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, offset, &value);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Determine if the pointer is in 4KB or word units */\n+\tif (value & IXGBE_SR_NVM_PTR_4KB_UNITS)\n+\t\t*pointer = (value & ~IXGBE_SR_NVM_PTR_4KB_UNITS) * 4 * 1024;\n+\telse\n+\t\t*pointer = value * 2;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_read_sr_area_size - Read an area size from a Shadow RAM word\n+ * @hw: pointer to the HW structure\n+ * @offset: the word offset of the Shadow RAM to read\n+ * @size: size value read from the Shadow RAM\n+ *\n+ * Read the given Shadow RAM word, and convert it to an area size value\n+ * specified in bytes. This function assumes the specified offset is a valid\n+ * area size word.\n+ *\n+ * Each area size word is specified in 4KB sector units. This function reports\n+ * the size in bytes, intended for flat NVM reads.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_read_sr_area_size(struct ixgbe_hw *hw, u16 offset, u32 *size)\n+{\n+\ts32 status;\n+\tu16 value;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, offset, &value);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Area sizes are always specified in 4KB units */\n+\t*size = value * 4 * 1024;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_discover_flash_size - Discover the available flash size.\n+ * @hw: pointer to the HW struct\n+ *\n+ * The device flash could be up to 16MB in size. However, it is possible that\n+ * the actual size is smaller. Use bisection to determine the accessible size\n+ * of flash memory.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_discover_flash_size(struct ixgbe_hw *hw)\n+{\n+\tu32 min_size = 0, max_size = IXGBE_ACI_NVM_MAX_OFFSET + 1;\n+\ts32 status;\n+\n+\tstatus = ixgbe_acquire_nvm(hw, IXGBE_RES_READ);\n+\tif (status)\n+\t\treturn status;\n+\n+\twhile ((max_size - min_size) > 1) {\n+\t\tu32 offset = (max_size + min_size) / 2;\n+\t\tu32 len = 1;\n+\t\tu8 data;\n+\n+\t\tstatus = ixgbe_read_flat_nvm(hw, offset, &len, &data, false);\n+\t\tif (status == IXGBE_ERR_ACI_ERROR &&\n+\t\t hw->aci.last_status == IXGBE_ACI_RC_EINVAL) {\n+\t\t\tstatus = IXGBE_SUCCESS;\n+\t\t\tmax_size = offset;\n+\t\t} else if (!status) {\n+\t\t\tmin_size = offset;\n+\t\t} else {\n+\t\t\t/* an unexpected error occurred */\n+\t\t\tgoto err_read_flat_nvm;\n+\t\t}\n+\t}\n+\n+\thw->flash.flash_size = max_size;\n+\n+err_read_flat_nvm:\n+\tixgbe_release_nvm(hw);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_determine_active_flash_banks - Discover active bank for each module\n+ * @hw: pointer to the HW struct\n+ *\n+ * Read the Shadow RAM control word and determine which banks are active for\n+ * the NVM, OROM, and Netlist modules. Also read and calculate the associated\n+ * pointer and size. These values are then cached into the ixgbe_flash_info\n+ * structure for later use in order to calculate the correct offset to read\n+ * from the active module.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+static s32 ixgbe_determine_active_flash_banks(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_bank_info *banks = &hw->flash.banks;\n+\tu16 ctrl_word;\n+\ts32 status;\n+\n+\tstatus = ixgbe_read_ee_aci_E610(hw, E610_SR_NVM_CTRL_WORD, &ctrl_word);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\t/* Check that the control word indicates validity */\n+\tif ((ctrl_word & IXGBE_SR_CTRL_WORD_1_M) >> IXGBE_SR_CTRL_WORD_1_S !=\n+\t IXGBE_SR_CTRL_WORD_VALID) {\n+\t\treturn IXGBE_ERR_CONFIG;\n+\t}\n+\n+\tif (!(ctrl_word & IXGBE_SR_CTRL_WORD_NVM_BANK))\n+\t\tbanks->nvm_bank = IXGBE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->nvm_bank = IXGBE_2ND_FLASH_BANK;\n+\n+\tif (!(ctrl_word & IXGBE_SR_CTRL_WORD_OROM_BANK))\n+\t\tbanks->orom_bank = IXGBE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->orom_bank = IXGBE_2ND_FLASH_BANK;\n+\n+\tif (!(ctrl_word & IXGBE_SR_CTRL_WORD_NETLIST_BANK))\n+\t\tbanks->netlist_bank = IXGBE_1ST_FLASH_BANK;\n+\telse\n+\t\tbanks->netlist_bank = IXGBE_2ND_FLASH_BANK;\n+\n+\tstatus = ixgbe_read_sr_pointer(hw, E610_SR_1ST_NVM_BANK_PTR,\n+\t\t\t\t &banks->nvm_ptr);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_area_size(hw, E610_SR_NVM_BANK_SIZE,\n+\t\t\t\t\t &banks->nvm_size);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_pointer(hw, E610_SR_1ST_OROM_BANK_PTR,\n+\t\t\t\t &banks->orom_ptr);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_area_size(hw, E610_SR_OROM_BANK_SIZE,\n+\t\t\t\t\t &banks->orom_size);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_pointer(hw, E610_SR_NETLIST_BANK_PTR,\n+\t\t\t\t &banks->netlist_ptr);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_read_sr_area_size(hw, E610_SR_NETLIST_BANK_SIZE,\n+\t\t\t\t\t &banks->netlist_size);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_init_nvm - initializes NVM setting\n+ * @hw: pointer to the HW struct\n+ *\n+ * Read and populate NVM settings such as Shadow RAM size,\n+ * max_timeout, and blank_nvm_mode\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_init_nvm(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_flash_info *flash = &hw->flash;\n+\tu32 fla, gens_stat, status;\n+\tu8 sr_size;\n+\n+\t/* The SR size is stored regardless of the NVM programming mode\n+\t * as the blank mode may be used in the factory line.\n+\t */\n+\tgens_stat = IXGBE_READ_REG(hw, GLNVM_GENS);\n+\tsr_size = (gens_stat & GLNVM_GENS_SR_SIZE_M) >> GLNVM_GENS_SR_SIZE_S;\n+\n+\t/* Switching to words (sr_size contains power of 2) */\n+\tflash->sr_words = BIT(sr_size) * IXGBE_SR_WORDS_IN_1KB;\n+\n+\t/* Check if we are in the normal or blank NVM programming mode */\n+\tfla = IXGBE_READ_REG(hw, GLNVM_FLA);\n+\tif (fla & GLNVM_FLA_LOCKED_M) { /* Normal programming mode */\n+\t\tflash->blank_nvm_mode = false;\n+\t} else {\n+\t\t/* Blank programming mode */\n+\t\tflash->blank_nvm_mode = true;\n+\t\treturn IXGBE_ERR_NVM_BLANK_MODE;\n+\t}\n+\n+\tstatus = ixgbe_discover_flash_size(hw);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_determine_active_flash_banks(hw);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\tstatus = ixgbe_get_nvm_ver_info(hw, IXGBE_ACTIVE_FLASH_BANK,\n+\t\t\t\t\t&flash->nvm);\n+\tif (status) {\n+\t\treturn status;\n+\t}\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_sanitize_operate - Clear the user data\n+ * @hw: pointer to the HW struct\n+ *\n+ * Clear user data from NVM using ACI command (0x070C).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_sanitize_operate(struct ixgbe_hw *hw)\n+{\n+\ts32 status;\n+\tu8 values;\n+\n+\tu8 cmd_flags = IXGBE_ACI_SANITIZE_REQ_OPERATE |\n+\t\t IXGBE_ACI_SANITIZE_OPERATE_SUBJECT_CLEAR;\n+\n+\tstatus = ixgbe_sanitize_nvm(hw, cmd_flags, &values);\n+\tif (status)\n+\t\treturn status;\n+\tif ((!(values & IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE) &&\n+\t !(values & IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE)) ||\n+\t ((values & IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_DONE) &&\n+\t !(values & IXGBE_ACI_SANITIZE_OPERATE_HOST_CLEAN_SUCCESS)) ||\n+\t ((values & IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_DONE) &&\n+\t !(values & IXGBE_ACI_SANITIZE_OPERATE_BMC_CLEAN_SUCCESS)))\n+\t\treturn IXGBE_ERR_ACI_ERROR;\n+\n+\treturn IXGBE_SUCCESS;\n+}\n+\n+/**\n+ * ixgbe_sanitize_nvm - Sanitize NVM\n+ * @hw: pointer to the HW struct\n+ * @cmd_flags: flag to the ACI command\n+ * @values: values returned from the command\n+ *\n+ * Sanitize NVM using ACI command (0x070C).\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_sanitize_nvm(struct ixgbe_hw *hw, u8 cmd_flags, u8 *values)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\tstruct ixgbe_aci_cmd_nvm_sanitization *cmd;\n+\ts32 status;\n+\n+\tcmd = &desc.params.nvm_sanitization;\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_nvm_sanitization);\n+\tcmd->cmd_flags = cmd_flags;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (values)\n+\t\t*values = cmd->values;\n+\n+\treturn status;\n+}\n+\n /**\n * ixgbe_read_sr_word_aci - Reads Shadow RAM via ACI\n * @hw: pointer to the HW structure\n@@ -2310,6 +3070,335 @@ s32 ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length,\n \treturn status;\n }\n \n+/**\n+ * ixgbe_aci_alternate_write - write to alternate structure\n+ * @hw: pointer to the hardware structure\n+ * @reg_addr0: address of first dword to be written\n+ * @reg_val0: value to be written under 'reg_addr0'\n+ * @reg_addr1: address of second dword to be written\n+ * @reg_val1: value to be written under 'reg_addr1'\n+ *\n+ * Write one or two dwords to alternate structure using ACI command (0x0900).\n+ * Fields are indicated by 'reg_addr0' and 'reg_addr1' register numbers.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_write(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t u32 reg_val0, u32 reg_addr1, u32 reg_val1)\n+{\n+\tstruct ixgbe_aci_cmd_read_write_alt_direct *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.read_write_alt_direct;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_write_alt_direct);\n+\tcmd->dword0_addr = IXGBE_CPU_TO_LE32(reg_addr0);\n+\tcmd->dword1_addr = IXGBE_CPU_TO_LE32(reg_addr1);\n+\tcmd->dword0_value = IXGBE_CPU_TO_LE32(reg_val0);\n+\tcmd->dword1_value = IXGBE_CPU_TO_LE32(reg_val1);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_alternate_read - read from alternate structure\n+ * @hw: pointer to the hardware structure\n+ * @reg_addr0: address of first dword to be read\n+ * @reg_val0: pointer for data read from 'reg_addr0'\n+ * @reg_addr1: address of second dword to be read\n+ * @reg_val1: pointer for data read from 'reg_addr1'\n+ *\n+ * Read one or two dwords from alternate structure using ACI command (0x0902).\n+ * Fields are indicated by 'reg_addr0' and 'reg_addr1' register numbers.\n+ * If 'reg_val1' pointer is not passed then only register at 'reg_addr0'\n+ * is read.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_read(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t u32 *reg_val0, u32 reg_addr1, u32 *reg_val1)\n+{\n+\tstruct ixgbe_aci_cmd_read_write_alt_direct *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.read_write_alt_direct;\n+\n+\tif (!reg_val0)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_read_alt_direct);\n+\tcmd->dword0_addr = IXGBE_CPU_TO_LE32(reg_addr0);\n+\tcmd->dword1_addr = IXGBE_CPU_TO_LE32(reg_addr1);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\tif (status == IXGBE_SUCCESS) {\n+\t\t*reg_val0 = IXGBE_LE32_TO_CPU(cmd->dword0_value);\n+\n+\t\tif (reg_val1)\n+\t\t\t*reg_val1 = IXGBE_LE32_TO_CPU(cmd->dword1_value);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_alternate_write_done - check if writing to alternate structure\n+ * is done\n+ * @hw: pointer to the HW structure.\n+ * @bios_mode: indicates whether the command is executed by UEFI or legacy BIOS\n+ * @reset_needed: indicates the SW should trigger GLOBAL reset\n+ *\n+ * Indicates to the FW that alternate structures have been changed.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_write_done(struct ixgbe_hw *hw, u8 bios_mode,\n+\t\t\t\t bool *reset_needed)\n+{\n+\tstruct ixgbe_aci_cmd_done_alt_write *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.done_alt_write;\n+\n+\tif (!reset_needed)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc, ixgbe_aci_opc_done_alt_write);\n+\tcmd->flags = bios_mode;\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\tif (!status)\n+\t\t*reset_needed = (IXGBE_LE16_TO_CPU(cmd->flags) &\n+\t\t\t\t IXGBE_ACI_RESP_RESET_NEEDED) != 0;\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_alternate_clear - clear alternate structure\n+ * @hw: pointer to the HW structure.\n+ *\n+ * Clear the alternate structures of the port from which the function\n+ * is called.\n+ *\n+ * Return: 0 on success and error code on failure.\n+ */\n+s32 ixgbe_aci_alternate_clear(struct ixgbe_hw *hw)\n+{\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc,\n+\t\t\t\t\tixgbe_aci_opc_clear_port_alt_write);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, NULL, 0);\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_aci_get_internal_data - get internal FW/HW data\n+ * @hw: pointer to the hardware structure\n+ * @cluster_id: specific cluster to dump\n+ * @table_id: table ID within cluster\n+ * @start: index of line in the block to read\n+ * @buf: dump buffer\n+ * @buf_size: dump buffer size\n+ * @ret_buf_size: return buffer size (returned by FW)\n+ * @ret_next_cluster: next cluster to read (returned by FW)\n+ * @ret_next_table: next block to read (returned by FW)\n+ * @ret_next_index: next index to read (returned by FW)\n+ *\n+ * Get internal FW/HW data using ACI command (0xFF08) for debug purposes.\n+ *\n+ * Return: the exit code of the operation.\n+ */\n+s32 ixgbe_aci_get_internal_data(struct ixgbe_hw *hw, u16 cluster_id,\n+\t\t\t\tu16 table_id, u32 start, void *buf,\n+\t\t\t\tu16 buf_size, u16 *ret_buf_size,\n+\t\t\t\tu16 *ret_next_cluster, u16 *ret_next_table,\n+\t\t\t\tu32 *ret_next_index)\n+{\n+\tstruct ixgbe_aci_cmd_debug_dump_internals *cmd;\n+\tstruct ixgbe_aci_desc desc;\n+\ts32 status;\n+\n+\tcmd = &desc.params.debug_dump;\n+\n+\tif (buf_size == 0 || !buf)\n+\t\treturn IXGBE_ERR_PARAM;\n+\n+\tixgbe_fill_dflt_direct_cmd_desc(&desc,\n+\t\t\t\t\tixgbe_aci_opc_debug_dump_internals);\n+\n+\tcmd->cluster_id = IXGBE_CPU_TO_LE16(cluster_id);\n+\tcmd->table_id = IXGBE_CPU_TO_LE16(table_id);\n+\tcmd->idx = IXGBE_CPU_TO_LE32(start);\n+\n+\tstatus = ixgbe_aci_send_cmd(hw, &desc, buf, buf_size);\n+\n+\tif (!status) {\n+\t\tif (ret_buf_size)\n+\t\t\t*ret_buf_size = IXGBE_LE16_TO_CPU(desc.datalen);\n+\t\tif (ret_next_cluster)\n+\t\t\t*ret_next_cluster = IXGBE_LE16_TO_CPU(cmd->cluster_id);\n+\t\tif (ret_next_table)\n+\t\t\t*ret_next_table = IXGBE_LE16_TO_CPU(cmd->table_id);\n+\t\tif (ret_next_index)\n+\t\t\t*ret_next_index = IXGBE_LE32_TO_CPU(cmd->idx);\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ixgbe_validate_nvm_rw_reg - Check that an NVM access request is valid\n+ * @cmd: NVM access command structure\n+ *\n+ * Validates that an NVM access structure is request to read or write a valid\n+ * register offset. First validates that the module and flags are correct, and\n+ * then ensures that the register offset is one of the accepted registers.\n+ *\n+ * Return: 0 if the register access is valid, out of range error code otherwise.\n+ */\n+static s32\n+ixgbe_validate_nvm_rw_reg(struct ixgbe_nvm_access_cmd *cmd)\n+{\n+\tu16 i;\n+\n+\tswitch (cmd->offset) {\n+\tcase GL_HICR:\n+\tcase GL_HICR_EN: /* Note, this register is read only */\n+\tcase GL_FWSTS:\n+\tcase GL_MNG_FWSM:\n+\tcase GLNVM_GENS:\n+\tcase GLNVM_FLA:\n+\tcase GL_FWRESETCNT:\n+\t\treturn 0;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tfor (i = 0; i <= GL_HIDA_MAX_INDEX; i++)\n+\t\tif (cmd->offset == (u32)GL_HIDA(i))\n+\t\t\treturn 0;\n+\n+\tfor (i = 0; i <= GL_HIBA_MAX_INDEX; i++)\n+\t\tif (cmd->offset == (u32)GL_HIBA(i))\n+\t\t\treturn 0;\n+\n+\t/* All other register offsets are not valid */\n+\treturn IXGBE_ERR_OUT_OF_RANGE;\n+}\n+\n+/**\n+ * ixgbe_nvm_access_read - Handle an NVM read request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command to process\n+ * @data: storage for the register value read\n+ *\n+ * Process an NVM access request to read a register.\n+ *\n+ * Return: 0 if the register read is valid and successful,\n+ * out of range error code otherwise.\n+ */\n+static s32 ixgbe_nvm_access_read(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\tstruct ixgbe_nvm_access_data *data)\n+{\n+\ts32 status;\n+\n+\t/* Always initialize the output data, even on failure */\n+\tmemset(&data->regval, 0, cmd->data_size);\n+\n+\t/* Make sure this is a valid read/write access request */\n+\tstatus = ixgbe_validate_nvm_rw_reg(cmd);\n+\tif (status)\n+\t\treturn status;\n+\n+\tDEBUGOUT1(\"NVM access: reading register %08x\\n\", cmd->offset);\n+\n+\t/* Read the register and store the contents in the data field */\n+\tdata->regval = IXGBE_READ_REG(hw, cmd->offset);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ixgbe_nvm_access_write - Handle an NVM write request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command to process\n+ * @data: NVM access data to write\n+ *\n+ * Process an NVM access request to write a register.\n+ *\n+ * Return: 0 if the register write is valid and successful,\n+ * out of range error code otherwise.\n+ */\n+static s32 ixgbe_nvm_access_write(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\tstruct ixgbe_nvm_access_data *data)\n+{\n+\ts32 status;\n+\n+\t/* Make sure this is a valid read/write access request */\n+\tstatus = ixgbe_validate_nvm_rw_reg(cmd);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Reject requests to write to read-only registers */\n+\tswitch (cmd->offset) {\n+\tcase GL_HICR_EN:\n+\t\treturn IXGBE_ERR_OUT_OF_RANGE;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\tDEBUGOUT2(\"NVM access: writing register %08x with value %08x\\n\",\n+\t\tcmd->offset, data->regval);\n+\n+\t/* Write the data field to the specified register */\n+\tIXGBE_WRITE_REG(hw, cmd->offset, data->regval);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ixgbe_handle_nvm_access - Handle an NVM access request\n+ * @hw: pointer to the HW struct\n+ * @cmd: NVM access command info\n+ * @data: pointer to read or return data\n+ *\n+ * Process an NVM access request. Read the command structure information and\n+ * determine if it is valid. If not, report an error indicating the command\n+ * was invalid.\n+ *\n+ * For valid commands, perform the necessary function, copying the data into\n+ * the provided data buffer.\n+ *\n+ * Return: 0 if the nvm access request is valid and successful,\n+ * error code otherwise.\n+ */\n+s32 ixgbe_handle_nvm_access(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\tstruct ixgbe_nvm_access_data *data)\n+{\n+\tswitch (cmd->command) {\n+\tcase IXGBE_NVM_CMD_READ:\n+\t\treturn ixgbe_nvm_access_read(hw, cmd, data);\n+\tcase IXGBE_NVM_CMD_WRITE:\n+\t\treturn ixgbe_nvm_access_write(hw, cmd, data);\n+\tdefault:\n+\t\treturn IXGBE_ERR_PARAM;\n+\t}\n+}\n+\n /**\n * ixgbe_init_ops_E610 - Inits func ptrs and MAC type\n * @hw: pointer to hardware structure\ndiff --git a/drivers/net/ixgbe/base/ixgbe_e610.h b/drivers/net/ixgbe/base/ixgbe_e610.h\nindex 608d60bfee..81e75a6e17 100644\n--- a/drivers/net/ixgbe/base/ixgbe_e610.h\n+++ b/drivers/net/ixgbe/base/ixgbe_e610.h\n@@ -20,6 +20,8 @@ void ixgbe_fill_dflt_direct_cmd_desc(struct ixgbe_aci_desc *desc, u16 opcode);\n \n s32 ixgbe_aci_get_fw_ver(struct ixgbe_hw *hw);\n s32 ixgbe_aci_send_driver_ver(struct ixgbe_hw *hw, struct ixgbe_driver_ver *dv);\n+s32 ixgbe_aci_set_pf_context(struct ixgbe_hw *hw, u8 pf_id);\n+\n s32 ixgbe_acquire_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res,\n \t\t enum ixgbe_aci_res_access_type access, u32 timeout);\n void ixgbe_release_res(struct ixgbe_hw *hw, enum ixgbe_aci_res_ids res);\n@@ -29,9 +31,12 @@ s32 ixgbe_discover_dev_caps(struct ixgbe_hw *hw,\n \t\t\t struct ixgbe_hw_dev_caps *dev_caps);\n s32 ixgbe_discover_func_caps(struct ixgbe_hw* hw,\n \t\t\t struct ixgbe_hw_func_caps* func_caps);\n+s32 ixgbe_get_caps(struct ixgbe_hw *hw);\n s32 ixgbe_aci_disable_rxen(struct ixgbe_hw *hw);\n s32 ixgbe_aci_get_phy_caps(struct ixgbe_hw *hw, bool qual_mods, u8 report_mode,\n \t\t\t struct ixgbe_aci_cmd_get_phy_caps_data *pcaps);\n+bool ixgbe_phy_caps_equals_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,\n+\t\t\t struct ixgbe_aci_cmd_set_phy_cfg_data *cfg);\n void ixgbe_copy_phy_caps_to_cfg(struct ixgbe_aci_cmd_get_phy_caps_data *caps,\n \t\t\t\tstruct ixgbe_aci_cmd_set_phy_cfg_data *cfg);\n s32 ixgbe_aci_set_phy_cfg(struct ixgbe_hw *hw,\n@@ -43,9 +48,34 @@ s32 ixgbe_aci_get_link_info(struct ixgbe_hw *hw, bool ena_lse,\n \t\t\t struct ixgbe_link_status *link);\n s32 ixgbe_aci_set_event_mask(struct ixgbe_hw *hw, u8 port_num, u16 mask);\n s32 ixgbe_configure_lse(struct ixgbe_hw *hw, bool activate, u16 mask);\n+\n+s32 ixgbe_aci_get_netlist_node(struct ixgbe_hw *hw,\n+\t\t\t struct ixgbe_aci_cmd_get_link_topo *cmd,\n+\t\t\t u8 *node_part_number, u16 *node_handle);\n+s32 ixgbe_aci_get_netlist_node_pin(struct ixgbe_hw *hw,\n+\t\t\t\t struct ixgbe_aci_cmd_get_link_topo_pin *cmd,\n+\t\t\t\t u16 *node_handle);\n+s32 ixgbe_find_netlist_node(struct ixgbe_hw *hw, u8 node_type_ctx,\n+\t\t\t u8 node_part_number, u16 *node_handle);\n+s32 ixgbe_aci_read_i2c(struct ixgbe_hw *hw,\n+\t\t struct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t u16 bus_addr, __le16 addr, u8 params, u8 *data);\n+s32 ixgbe_aci_write_i2c(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_addr topo_addr,\n+\t\t\tu16 bus_addr, __le16 addr, u8 params, u8 *data);\n+s32 ixgbe_aci_set_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t bool value);\n+s32 ixgbe_aci_get_gpio(struct ixgbe_hw *hw, u16 gpio_ctrl_handle, u8 pin_idx,\n+\t\t bool *value);\n s32 ixgbe_aci_sff_eeprom(struct ixgbe_hw *hw, u16 lport, u8 bus_addr,\n \t\t\t u16 mem_addr, u8 page, u8 page_bank_ctrl, u8 *data,\n \t\t\t u8 length, bool write);\n+s32 ixgbe_aci_prog_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params);\n+s32 ixgbe_aci_read_topo_dev_nvm(struct ixgbe_hw *hw,\n+\t\t\tstruct ixgbe_aci_cmd_link_topo_params *topo_params,\n+\t\t\tu32 start_address, u8 *data, u8 data_size);\n+\n s32 ixgbe_acquire_nvm(struct ixgbe_hw *hw,\n \t\t enum ixgbe_aci_res_access_type access);\n void ixgbe_release_nvm(struct ixgbe_hw *hw);\n@@ -55,11 +85,39 @@ s32 ixgbe_aci_read_nvm(struct ixgbe_hw *hw, u16 module_typeid, u32 offset,\n \t\t bool read_shadow_ram);\n \n s32 ixgbe_nvm_validate_checksum(struct ixgbe_hw *hw);\n+s32 ixgbe_nvm_recalculate_checksum(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_get_nvm_minsrevs(struct ixgbe_hw *hw, struct ixgbe_minsrev_info *minsrevs);\n+s32 ixgbe_get_inactive_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n s32 ixgbe_get_active_nvm_ver(struct ixgbe_hw *hw, struct ixgbe_nvm_info *nvm);\n+s32 ixgbe_init_nvm(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_sanitize_operate(struct ixgbe_hw *hw);\n+s32 ixgbe_sanitize_nvm(struct ixgbe_hw *hw, u8 cmd_flags, u8 *values);\n+\n s32 ixgbe_read_sr_word_aci(struct ixgbe_hw *hw, u16 offset, u16 *data);\n s32 ixgbe_read_sr_buf_aci(struct ixgbe_hw *hw, u16 offset, u16 *words, u16 *data);\n s32 ixgbe_read_flat_nvm(struct ixgbe_hw *hw, u32 offset, u32 *length,\n \t\t\tu8 *data, bool read_shadow_ram);\n+\n+s32 ixgbe_aci_alternate_write(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t u32 reg_val0, u32 reg_addr1, u32 reg_val1);\n+s32 ixgbe_aci_alternate_read(struct ixgbe_hw *hw, u32 reg_addr0,\n+\t\t\t u32 *reg_val0, u32 reg_addr1, u32 *reg_val1);\n+s32 ixgbe_aci_alternate_write_done(struct ixgbe_hw *hw, u8 bios_mode,\n+\t\t\t\t bool *reset_needed);\n+s32 ixgbe_aci_alternate_clear(struct ixgbe_hw *hw);\n+\n+s32 ixgbe_aci_get_internal_data(struct ixgbe_hw *hw, u16 cluster_id,\n+\t\t\t\tu16 table_id, u32 start, void *buf,\n+\t\t\t\tu16 buf_size, u16 *ret_buf_size,\n+\t\t\t\tu16 *ret_next_cluster, u16 *ret_next_table,\n+\t\t\t\tu32 *ret_next_index);\n+\n+s32 ixgbe_handle_nvm_access(struct ixgbe_hw *hw,\n+\t\t\t\tstruct ixgbe_nvm_access_cmd *cmd,\n+\t\t\t\tstruct ixgbe_nvm_access_data *data);\n+\n /* E610 operations */\n s32 ixgbe_reset_hw_E610(struct ixgbe_hw *hw);\n s32 ixgbe_start_hw_E610(struct ixgbe_hw *hw);\ndiff --git a/drivers/net/ixgbe/base/ixgbe_type_e610.h b/drivers/net/ixgbe/base/ixgbe_type_e610.h\nindex b366ea571a..35134cdae9 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type_e610.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type_e610.h\n@@ -119,6 +119,14 @@\n #define E610_SR_NVM_CTRL_WORD\t\t0x00\n #define E610_SR_PBA_BLOCK_PTR\t\t0x16\n \n+/* The Orom version topology */\n+#define IXGBE_OROM_VER_PATCH_SHIFT\t0\n+#define IXGBE_OROM_VER_PATCH_MASK\t(0xff << IXGBE_OROM_VER_PATCH_SHIFT)\n+#define IXGBE_OROM_VER_BUILD_SHIFT\t8\n+#define IXGBE_OROM_VER_BUILD_MASK\t(0xffff << IXGBE_OROM_VER_BUILD_SHIFT)\n+#define IXGBE_OROM_VER_SHIFT\t\t24\n+#define IXGBE_OROM_VER_MASK\t\t(0xff << IXGBE_OROM_VER_SHIFT)\n+\n /* CSS Header words */\n #define IXGBE_NVM_CSS_HDR_LEN_L\t\t\t0x02\n #define IXGBE_NVM_CSS_HDR_LEN_H\t\t\t0x03\n@@ -128,6 +136,39 @@\n /* Length of Authentication header section in words */\n #define IXGBE_NVM_AUTH_HEADER_LEN\t\t0x08\n \n+/* The Netlist ID Block is located after all of the Link Topology nodes. */\n+#define IXGBE_NETLIST_ID_BLK_SIZE\t\t0x30\n+#define IXGBE_NETLIST_ID_BLK_OFFSET(n)\t\tIXGBE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))\n+\n+/* netlist ID block field offsets (word offsets) */\n+#define IXGBE_NETLIST_ID_BLK_MAJOR_VER_LOW\t0x02\n+#define IXGBE_NETLIST_ID_BLK_MAJOR_VER_HIGH\t0x03\n+#define IXGBE_NETLIST_ID_BLK_MINOR_VER_LOW\t0x04\n+#define IXGBE_NETLIST_ID_BLK_MINOR_VER_HIGH\t0x05\n+#define IXGBE_NETLIST_ID_BLK_TYPE_LOW\t\t0x06\n+#define IXGBE_NETLIST_ID_BLK_TYPE_HIGH\t\t0x07\n+#define IXGBE_NETLIST_ID_BLK_REV_LOW\t\t0x08\n+#define IXGBE_NETLIST_ID_BLK_REV_HIGH\t\t0x09\n+#define IXGBE_NETLIST_ID_BLK_SHA_HASH_WORD(n)\t(0x0A + (n))\n+#define IXGBE_NETLIST_ID_BLK_CUST_VER\t\t0x2F\n+\n+/* The Link Topology Netlist section is stored as a series of words. It is\n+ * stored in the NVM as a TLV, with the first two words containing the type\n+ * and length.\n+ */\n+#define IXGBE_NETLIST_LINK_TOPO_MOD_ID\t\t0x011B\n+#define IXGBE_NETLIST_TYPE_OFFSET\t\t0x0000\n+#define IXGBE_NETLIST_LEN_OFFSET\t\t0x0001\n+\n+/* The Link Topology section follows the TLV header. When reading the netlist\n+ * using ixgbe_read_netlist_module, we need to account for the 2-word TLV\n+ * header.\n+ */\n+#define IXGBE_NETLIST_LINK_TOPO_OFFSET(n)\t((n) + 2)\n+#define IXGBE_LINK_TOPO_MODULE_LEN\tIXGBE_NETLIST_LINK_TOPO_OFFSET(0x0000)\n+#define IXGBE_LINK_TOPO_NODE_COUNT\tIXGBE_NETLIST_LINK_TOPO_OFFSET(0x0001)\n+#define IXGBE_LINK_TOPO_NODE_COUNT_M\tMAKEMASK(0x3FF, 0)\n+\n /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */\n #define IXGBE_SR_CTRL_WORD_1_S\t\t0x06\n #define IXGBE_SR_CTRL_WORD_1_M\t\t(0x03 << IXGBE_SR_CTRL_WORD_1_S)\n@@ -152,6 +193,9 @@\n */\n #define IXGBE_SR_SW_CHECKSUM_BASE\t\t0xBABA\n \n+/* Netlist */\n+#define IXGBE_MAX_NETLIST_SIZE\t\t\t10\n+\n /* General registers */\n \n /* Firmware Status Register (GL_FWSTS) */\n@@ -227,17 +271,81 @@\n #define GLNVM_FLA_LOCKED_S\t\t\t6\n #define GLNVM_FLA_LOCKED_M\t\t\tBIT(6)\n \n+/* Bit Bang registers */\n+#define RDASB_MSGCTL\t\t\t\t0x000B6820\n+#define RDASB_MSGCTL_HDR_DWS_S\t\t\t0\n+#define RDASB_MSGCTL_EXP_RDW_S\t\t\t8\n+#define RDASB_MSGCTL_CMDV_M\t\t\tBIT(31)\n+#define RDASB_RSPCTL\t\t\t\t0x000B6824\n+#define RDASB_RSPCTL_BAD_LENGTH_M\t\tBIT(30)\n+#define RDASB_RSPCTL_NOT_SUCCESS_M\t\tBIT(31)\n+#define RDASB_WHDR0\t\t\t\t0x000B68F4\n+#define RDASB_WHDR1\t\t\t\t0x000B68F8\n+#define RDASB_WHDR2\t\t\t\t0x000B68FC\n+#define RDASB_WHDR3\t\t\t\t0x000B6900\n+#define RDASB_WHDR4\t\t\t\t0x000B6904\n+#define RDASB_RHDR0\t\t\t\t0x000B6AFC\n+#define RDASB_RHDR0_RESPONSE_S\t\t\t27\n+#define RDASB_RHDR0_RESPONSE_M\t\t\tMAKEMASK(0x7, 27)\n+#define RDASB_RDATA0\t\t\t\t0x000B6B00\n+#define RDASB_RDATA1\t\t\t\t0x000B6B04\n+\n+/* SPI Registers */\n+#define SPISB_MSGCTL\t\t\t\t0x000B7020\n+#define SPISB_MSGCTL_HDR_DWS_S\t\t\t0\n+#define SPISB_MSGCTL_EXP_RDW_S\t\t\t8\n+#define SPISB_MSGCTL_MSG_MODE_S\t\t\t26\n+#define SPISB_MSGCTL_TOKEN_MODE_S\t\t28\n+#define SPISB_MSGCTL_BARCLR_S\t\t\t30\n+#define SPISB_MSGCTL_CMDV_S\t\t\t31\n+#define SPISB_MSGCTL_CMDV_M\t\t\tBIT(31)\n+#define SPISB_RSPCTL\t\t\t\t0x000B7024\n+#define SPISB_RSPCTL_BAD_LENGTH_M\t\tBIT(30)\n+#define SPISB_RSPCTL_NOT_SUCCESS_M\t\tBIT(31)\n+#define SPISB_WHDR0\t\t\t\t0x000B70F4\n+#define SPISB_WHDR0_DEST_SEL_S\t\t\t12\n+#define SPISB_WHDR0_OPCODE_SEL_S\t\t16\n+#define SPISB_WHDR0_TAG_S\t\t\t24\n+#define SPISB_WHDR1\t\t\t\t0x000B70F8\n+#define SPISB_WHDR2\t\t\t\t0x000B70FC\n+#define SPISB_RDATA\t\t\t\t0x000B7300\n+#define SPISB_WDATA\t\t\t\t0x000B7100\n+\n+/* Firmware Reset Count register */\n+#define GL_FWRESETCNT\t\t\t\t0x00083100 /* Reset Source: POR */\n+#define GL_FWRESETCNT_FWRESETCNT_S\t\t0\n+#define GL_FWRESETCNT_FWRESETCNT_M\t\tMAKEMASK(0xFFFFFFFF, 0)\n+\n /* Admin Command Interface (ACI) registers */\n #define PF_HIDA(_i)\t\t\t(0x00085000 + ((_i) * 4))\n #define PF_HIDA_2(_i)\t\t\t(0x00085020 + ((_i) * 4))\n #define PF_HIBA(_i)\t\t\t(0x00084000 + ((_i) * 4))\n #define PF_HICR\t\t\t\t0x00082048\n \n+#define PF_HIDA_MAX_INDEX\t\t15\n+#define PF_HIBA_MAX_INDEX\t\t1023\n+\n #define PF_HICR_EN\t\t\tBIT(0)\n #define PF_HICR_C\t\t\tBIT(1)\n #define PF_HICR_SV\t\t\tBIT(2)\n #define PF_HICR_EV\t\t\tBIT(3)\n \n+#define GL_HIDA(_i)\t\t\t(0x00082000 + ((_i) * 4))\n+#define GL_HIDA_2(_i)\t\t\t(0x00082020 + ((_i) * 4))\n+#define GL_HIBA(_i)\t\t\t(0x00081000 + ((_i) * 4))\n+#define GL_HICR\t\t\t\t0x00082040\n+\n+#define GL_HIDA_MAX_INDEX\t\t15\n+#define GL_HIBA_MAX_INDEX\t\t1023\n+\n+#define GL_HICR_C\t\t\tBIT(1)\n+#define GL_HICR_SV\t\t\tBIT(2)\n+#define GL_HICR_EV\t\t\tBIT(3)\n+\n+#define GL_HICR_EN\t\t\t0x00082044\n+\n+#define GL_HICR_EN_CHECK\t\tBIT(0)\n+\n /* Admin Command Interface (ACI) defines */\n /* Defines that help manage the driver vs FW API checks.\n */\n@@ -260,6 +368,14 @@\n /* [ms] timeout of waiting for resource release */\n #define IXGBE_ACI_RELEASE_RES_TIMEOUT\t\t10000\n \n+/* Timestamp spacing for Tools ACI: queue is active if spacing is within the range [LO..HI] */\n+#define IXGBE_TOOLS_ACI_ACTIVE_STAMP_SPACING_LO 0\n+#define IXGBE_TOOLS_ACI_ACTIVE_STAMP_SPACING_HI 200\n+\n+/* Timestamp spacing for Tools ACI: queue is expired if spacing is outside the range [LO..HI] */\n+#define IXGBE_TOOLS_ACI_EXPIRED_STAMP_SPACING_LO -5\n+#define IXGBE_TOOLS_ACI_EXPIRED_STAMP_SPACING_HI 205\n+\n /* FW defined boundary for a large buffer, 4k >= Large buffer > 512 bytes */\n #define IXGBE_ACI_LG_BUF\t\t512\n \n@@ -488,6 +604,8 @@ IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_exp_err);\n \n /* FW update timeout definitions are in milliseconds */\n #define IXGBE_NVM_TIMEOUT\t\t180000\n+#define IXGBE_CHANGE_LOCK_TIMEOUT\t1000\n+#define IXGBE_GLOBAL_CFG_LOCK_TIMEOUT\t3000\n \n enum ixgbe_aci_res_access_type {\n \tIXGBE_RES_READ = 1,\n@@ -1234,10 +1352,48 @@ struct ixgbe_aci_cmd_nvm {\n };\n \n /* NVM Module_Type ID, needed offset and read_len for struct ixgbe_aci_cmd_nvm. */\n+#define IXGBE_ACI_NVM_SECTOR_UNIT\t\t4096 /* In Bytes */\n+#define IXGBE_ACI_NVM_WORD_UNIT\t\t\t2 /* In Bytes */\n+\n #define IXGBE_ACI_NVM_START_POINT\t\t0\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_OFFSET\t\t0x90\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_RD_LEN\t\t2 /* In Bytes */\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_M\t\tMAKEMASK(0x7FFF, 0)\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_S\t\t15\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_M\t\tBIT(15)\n+#define IXGBE_ACI_NVM_EMP_SR_PTR_TYPE_SECTOR\t1\n+\n+#define IXGBE_ACI_NVM_LLDP_CFG_PTR_OFFSET\t0x46\n+#define IXGBE_ACI_NVM_LLDP_CFG_HEADER_LEN\t2 /* In Bytes */\n+#define IXGBE_ACI_NVM_LLDP_CFG_PTR_RD_LEN\t2 /* In Bytes */\n+\n+#define IXGBE_ACI_NVM_LLDP_PRESERVED_MOD_ID\t\t0x129\n+#define IXGBE_ACI_NVM_CUR_LLDP_PERSIST_RD_OFFSET\t2 /* In Bytes */\n+#define IXGBE_ACI_NVM_LLDP_STATUS_M\t\t\tMAKEMASK(0xF, 0)\n+#define IXGBE_ACI_NVM_LLDP_STATUS_M_LEN\t\t\t4 /* In Bits */\n+#define IXGBE_ACI_NVM_LLDP_STATUS_RD_LEN\t\t4 /* In Bytes */\n+\n+#define IXGBE_ACI_NVM_MINSREV_MOD_ID\t\t0x130\n \n IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm);\n \n+/* Used for reading and writing MinSRev using 0x0701 and 0x0703. Note that the\n+ * type field is excluded from the section when reading and writing from\n+ * a module using the module_typeid field with these AQ commands.\n+ */\n+struct ixgbe_aci_cmd_nvm_minsrev {\n+\t__le16 length;\n+\t__le16 validity;\n+#define IXGBE_ACI_NVM_MINSREV_NVM_VALID\t\tBIT(0)\n+#define IXGBE_ACI_NVM_MINSREV_OROM_VALID\tBIT(1)\n+\t__le16 nvm_minsrev_l;\n+\t__le16 nvm_minsrev_h;\n+\t__le16 orom_minsrev_l;\n+\t__le16 orom_minsrev_h;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(12, ixgbe_aci_cmd_nvm_minsrev);\n+\n /* Used for 0x0704 as well as for 0x0705 commands */\n struct ixgbe_aci_cmd_nvm_cfg {\n \tu8\tcmd_flags;\n@@ -1254,6 +1410,14 @@ struct ixgbe_aci_cmd_nvm_cfg {\n \n IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_nvm_cfg);\n \n+struct ixgbe_aci_cmd_nvm_cfg_data {\n+\t__le16 field_id;\n+\t__le16 field_options;\n+\t__le16 field_value;\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(6, ixgbe_aci_cmd_nvm_cfg_data);\n+\n /* NVM Checksum Command (direct, 0x0706) */\n struct ixgbe_aci_cmd_nvm_checksum {\n \tu8 flags;\n@@ -1329,6 +1493,211 @@ struct ixgbe_aci_cmd_clear_port_alt_write {\n \n IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_clear_port_alt_write);\n \n+/* Get CGU abilities command response data structure (indirect 0x0C61) */\n+struct ixgbe_aci_cmd_get_cgu_abilities {\n+\tu8 num_inputs;\n+\tu8 num_outputs;\n+\tu8 pps_dpll_idx;\n+\tu8 synce_dpll_idx;\n+\t__le32 max_in_freq;\n+\t__le32 max_in_phase_adj;\n+\t__le32 max_out_freq;\n+\t__le32 max_out_phase_adj;\n+\tu8 cgu_part_num;\n+\tu8 rsvd[3];\n+};\n+\n+IXGBE_CHECK_STRUCT_LEN(24, ixgbe_aci_cmd_get_cgu_abilities);\n+\n+#define IXGBE_ACI_NODE_HANDLE_VALID\tBIT(10)\n+#define IXGBE_ACI_NODE_HANDLE\t\tMAKEMASK(0x3FF, 0)\n+#define IXGBE_ACI_DRIVING_CLK_NUM_SHIFT\t10\n+#define IXGBE_ACI_DRIVING_CLK_NUM\tMAKEMASK(0x3F, IXGBE_ACI_DRIVING_CLK_NUM_SHIFT)\n+\n+/* Set CGU input config (direct 0x0C62) */\n+struct ixgbe_aci_cmd_set_cgu_input_config {\n+\tu8 input_idx;\n+\tu8 flags1;\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_FREQ\tBIT(6)\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG1_UPDATE_DELAY\tBIT(7)\n+\tu8 flags2;\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_INPUT_EN\t\tBIT(5)\n+#define IXGBE_ACI_SET_CGU_IN_CFG_FLG2_ESYNC_EN\t\tBIT(6)\n+\tu8 rsvd;\n+\t__le32 freq;\n+\t__le32 phase_delay;\n+\tu8 rsvd2[2];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_input_config);\n+\n+/* Get CGU input config response descriptor structure (direct 0x0C63) */\n+struct ixgbe_aci_cmd_get_cgu_input_config {\n+\tu8 input_idx;\n+\tu8 status;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_LOS\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_SCM_FAIL\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_CFM_FAIL\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_GST_FAIL\tBIT(3)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_PFM_FAIL\tBIT(4)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_FAIL\tBIT(6)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_STATUS_ESYNC_CAP\tBIT(7)\n+\tu8 type;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_READ_ONLY\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_GPS\t\tBIT(4)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_EXTERNAL\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_TYPE_PHY\t\tBIT(6)\n+\tu8 flags1;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_PHASE_DELAY_SUPP\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_1PPS_SUPP\t\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_10MHZ_SUPP\tBIT(3)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG1_ANYFREQ\t\tBIT(7)\n+\t__le32 freq;\n+\t__le32 phase_delay;\n+\tu8 flags2;\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_INPUT_EN\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_IN_CFG_FLG2_ESYNC_EN\t\tBIT(6)\n+\tu8 rsvd[1];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_input_config);\n+\n+/* Set CGU output config (direct 0x0C64) */\n+struct ixgbe_aci_cmd_set_cgu_output_config {\n+\tu8 output_idx;\n+\tu8 flags;\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_OUT_EN\t\tBIT(0)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_ESYNC_EN\t\tBIT(1)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_FREQ\t\tBIT(2)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_PHASE\t\tBIT(3)\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_UPDATE_SRC_SEL\tBIT(4)\n+\tu8 src_sel;\n+#define IXGBE_ACI_SET_CGU_OUT_CFG_DPLL_SRC_SEL\t\tMAKEMASK(0x1F, 0)\n+\tu8 rsvd;\n+\t__le32 freq;\n+\t__le32 phase_delay;\n+\tu8 rsvd2[2];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_output_config);\n+\n+/* Get CGU output config (direct 0x0C65) */\n+struct ixgbe_aci_cmd_get_cgu_output_config {\n+\tu8 output_idx;\n+\tu8 flags;\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_OUT_EN\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_EN\t\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_ESYNC_ABILITY\t\tBIT(2)\n+\tu8 src_sel;\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT\t0\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL \\\n+\tMAKEMASK(0x1F, IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_SRC_SEL_SHIFT)\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT\t5\n+#define IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE \\\n+\tMAKEMASK(0x7, IXGBE_ACI_GET_CGU_OUT_CFG_DPLL_MODE_SHIFT)\n+\tu8 rsvd;\n+\t__le32 freq;\n+\t__le32 src_freq;\n+\tu8 rsvd2[2];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_output_config);\n+\n+/* Get CGU DPLL status (direct 0x0C66) */\n+struct ixgbe_aci_cmd_get_cgu_dpll_status {\n+\tu8 dpll_num;\n+\tu8 ref_state;\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_LOS\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_SCM\t\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_CFM\t\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_GST\t\tBIT(3)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_PFM\t\tBIT(4)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_FAST_LOCK_EN\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_REF_SW_ESYNC\t\tBIT(6)\n+\t__le16 dpll_state;\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_LOCK\t\tBIT(0)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO\t\t\tBIT(1)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_HO_READY\t\tBIT(2)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_FLHIT\t\tBIT(5)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_PSLHIT\t\tBIT(7)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT\t8\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SEL\t\t\\\n+\tMAKEMASK(0x1F, IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_CLK_REF_SHIFT)\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT\t\t13\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE \t\t\\\n+\tMAKEMASK(0x7, IXGBE_ACI_GET_CGU_DPLL_STATUS_STATE_MODE_SHIFT)\n+\t__le32 phase_offset_h;\n+\t__le32 phase_offset_l;\n+\tu8 eec_mode;\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_1\t\t0xA\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_2\t\t0xB\n+#define IXGBE_ACI_GET_CGU_DPLL_STATUS_EEC_MODE_UNKNOWN\t\t0xF\n+\tu8 rsvd[1];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_dpll_status);\n+\n+/* Set CGU DPLL config (direct 0x0C67) */\n+struct ixgbe_aci_cmd_set_cgu_dpll_config {\n+\tu8 dpll_num;\n+\tu8 ref_state;\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_LOS\tBIT(0)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_SCM\tBIT(1)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_CFM\tBIT(2)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_GST\tBIT(3)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_PFM\tBIT(4)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_FLOCK_EN\tBIT(5)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_REF_SW_ESYNC\tBIT(6)\n+\tu8 rsvd;\n+\tu8 config;\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_CLK_REF_SEL\tMAKEMASK(0x1F, 0)\n+#define IXGBE_ACI_SET_CGU_DPLL_CONFIG_MODE\t\tMAKEMASK(0x7, 5)\n+\tu8 rsvd2[8];\n+\tu8 eec_mode;\n+\tu8 rsvd3[1];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_dpll_config);\n+\n+/* Set CGU reference priority (direct 0x0C68) */\n+struct ixgbe_aci_cmd_set_cgu_ref_prio {\n+\tu8 dpll_num;\n+\tu8 ref_idx;\n+\tu8 ref_priority;\n+\tu8 rsvd[11];\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_set_cgu_ref_prio);\n+\n+/* Get CGU reference priority (direct 0x0C69) */\n+struct ixgbe_aci_cmd_get_cgu_ref_prio {\n+\tu8 dpll_num;\n+\tu8 ref_idx;\n+\tu8 ref_priority; /* Valid only in response */\n+\tu8 rsvd[13];\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_ref_prio);\n+\n+/* Get CGU info (direct 0x0C6A) */\n+struct ixgbe_aci_cmd_get_cgu_info {\n+\t__le32 cgu_id;\n+\t__le32 cgu_cfg_ver;\n+\t__le32 cgu_fw_ver;\n+\tu8 node_part_num;\n+\tu8 dev_rev;\n+\t__le16 node_handle;\n+};\n+\n+IXGBE_CHECK_PARAM_LEN(ixgbe_aci_cmd_get_cgu_info);\n+\n /* Debug Dump Internal Data (indirect 0xFF08) */\n struct ixgbe_aci_cmd_debug_dump_internals {\n \t__le16 cluster_id; /* Expresses next cluster ID in response */\n@@ -1694,6 +2063,16 @@ struct ixgbe_ts_dev_info {\n \tu8 tmr1_ena;\n };\n \n+#pragma pack(1)\n+struct ixgbe_orom_civd_info {\n+\tu8 signature[4];\t/* Must match ASCII '$CIV' characters */\n+\tu8 checksum;\t\t/* Simple modulo 256 sum of all structure bytes must equal 0 */\n+\t__le32 combo_ver;\t/* Combo Image Version number */\n+\tu8 combo_name_len;\t/* Length of the unicode combo image version string, max of 32 */\n+\t__le16 combo_name[32];\t/* Unicode string representing the Combo Image version */\n+};\n+#pragma pack()\n+\n /* Function specific capabilities */\n struct ixgbe_hw_func_caps {\n \tstruct ixgbe_hw_common_caps common_cap;\n@@ -1724,6 +2103,14 @@ struct ixgbe_aci_info {\n \tstruct ixgbe_lock lock;\t\t/* admin command interface lock */\n };\n \n+/* Minimum Security Revision information */\n+struct ixgbe_minsrev_info {\n+\tu32 nvm;\n+\tu32 orom;\n+\tu8 nvm_valid : 1;\n+\tu8 orom_valid : 1;\n+};\n+\n /* Enumeration of which flash bank is desired to read from, either the active\n * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from\n * code which just wants to read the active or inactive flash bank.\n@@ -1781,4 +2168,19 @@ struct ixgbe_flash_info {\n \tu8 blank_nvm_mode;\t\t\t/* is NVM empty (no FW present) */\n };\n \n+#define IXGBE_NVM_CMD_READ\t\t0x0000000B\n+#define IXGBE_NVM_CMD_WRITE\t\t0x0000000C\n+\n+/* NVM Access command */\n+struct ixgbe_nvm_access_cmd {\n+\tu32 command;\t\t/* NVM command: READ or WRITE */\n+\tu32 offset;\t\t\t/* Offset to read/write, in bytes */\n+\tu32 data_size;\t\t/* Size of data field, in bytes */\n+};\n+\n+/* NVM Access data */\n+struct ixgbe_nvm_access_data {\n+\tu32 regval;\t\t\t/* Storage for register value */\n+};\n+\n #endif /* _IXGBE_TYPE_E610_H_ */\n", "prefixes": [ "v2", "27/27" ] }