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GET /api/patches/139873/?format=api
{ "id": 139873, "url": "http://patchwork.dpdk.org/api/patches/139873/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240505183142.20148-1-arkadiuszx.kusztal@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240505183142.20148-1-arkadiuszx.kusztal@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240505183142.20148-1-arkadiuszx.kusztal@intel.com", "date": "2024-05-05T18:31:42", "name": "[v2] common/qat: add legacy algorithm option", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "372bfd920de9a7e3025129078bb35e3ff537f763", "submitter": { "id": 452, "url": "http://patchwork.dpdk.org/api/people/452/?format=api", "name": "Arkadiusz Kusztal", "email": "arkadiuszx.kusztal@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240505183142.20148-1-arkadiuszx.kusztal@intel.com/mbox/", "series": [ { "id": 31883, "url": "http://patchwork.dpdk.org/api/series/31883/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31883", "date": "2024-05-05T18:31:42", "name": "[v2] common/qat: add legacy algorithm option", "version": 2, "mbox": "http://patchwork.dpdk.org/series/31883/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/139873/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/139873/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 90CA843FB9;\n\tSun, 5 May 2024 20:32:07 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 66501400EF;\n\tSun, 5 May 2024 20:32:05 +0200 (CEST)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.10])\n by mails.dpdk.org (Postfix) with ESMTP id 7148B40041\n for <dev@dpdk.org>; Sun, 5 May 2024 20:32:03 +0200 (CEST)", "from fmviesa005.fm.intel.com ([10.60.135.145])\n by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 May 2024 11:32:03 -0700", "from silpixa00400308.ir.intel.com ([10.237.214.154])\n by fmviesa005.fm.intel.com with ESMTP; 05 May 2024 11:32:00 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1714933924; x=1746469924;\n h=from:to:cc:subject:date:message-id:in-reply-to: references;\n bh=GB6GG23MTwbe2w9QmkWgaLODHtzST2ZWMopboNzznpI=;\n b=iyPBZCTbscfSelc4r94jpMW8URb/D/xOG44STJuZsLuUFiV6mmgsHp/1\n bq2vqC1TlleWZIlJ+xntXhUt5JD1diHbvwr8XGzYJGZJP+wbaIox7l1MK\n PA225TZbHEgbHcU15b6gf1+UziD1LvEzXybcL9Yt6HNiWlOfgcrpLBnWz\n G8EChRnxrvwyXWhjQFcImLMDAwsVHF6zYnKDydZ+iD+fJOxc+G5uVj1sH\n DCrgA5Y1KnD4s/jQcYC7CpSmZLwZN4aO3YuKKYyy16rXH87bTlhT1CeUf\n 1PnZgTFpFLHKPh39173hOZ12nNk42QdkxZoMzL2Q3zEvFrUv0p1B7K9eF w==;", "X-CSE-ConnectionGUID": [ "p8rF0/H6TmGz+93SH445mA==", "zjwD3ImhSK65dGHq+lJbyQ==" ], "X-CSE-MsgGUID": [ "mGYBQ9IvRMeBLn7L0ErSVw==", "rkebN1UuT6ChUbpLyjpvAQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6600,9927,11064\"; a=\"28150514\"", "E=Sophos;i=\"6.07,256,1708416000\"; d=\"scan'208\";a=\"28150514\"", "E=Sophos;i=\"6.07,256,1708416000\"; d=\"scan'208\";a=\"32428957\"" ], "X-ExtLoop1": "1", "From": "Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>", "To": "dev@dpdk.org", "Cc": "gakhil@marvell.com, ciara.power@intel.com,\n Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>", "Subject": "[PATCH v2] common/qat: add legacy algorithm option", "Date": "Sun, 5 May 2024 19:31:42 +0100", "Message-Id": "<20240505183142.20148-1-arkadiuszx.kusztal@intel.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20240418165128.17261-1-arkadiuszx.kusztal@intel.com>", "References": "<20240418165128.17261-1-arkadiuszx.kusztal@intel.com>", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "This commit adds legacy algorithms flag to the qat_device\nstruct. This will allow handling this flag within the device\nitself, and not using the global variable.\n\nSigned-off-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>\n---\nv2:\n- added session parameters handling\n\n drivers/common/qat/qat_common.h | 9 +++++++++\n drivers/common/qat/qat_device.c | 7 +++----\n drivers/common/qat/qat_device.h | 7 ++-----\n drivers/common/qat/qat_qp.c | 2 +-\n drivers/common/qat/qat_qp.h | 3 ++-\n drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c | 4 ++--\n drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c | 17 +++++++++--------\n drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c | 4 ++--\n drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c | 4 ++--\n drivers/crypto/qat/dev/qat_sym_pmd_gen1.c | 6 +++---\n drivers/crypto/qat/qat_asym.c | 23 ++++++++++++++---------\n drivers/crypto/qat/qat_crypto.h | 1 -\n drivers/crypto/qat/qat_sym.c | 24 ++++++++++++------------\n drivers/crypto/qat/qat_sym_session.c | 10 +++++-----\n 14 files changed, 66 insertions(+), 55 deletions(-)", "diff": "diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h\nindex 6d0f4aefd5..97828e2c67 100644\n--- a/drivers/common/qat/qat_common.h\n+++ b/drivers/common/qat/qat_common.h\n@@ -19,6 +19,15 @@\n \n extern const char *const *qat_cmdline_defines[];\n \n+struct qat_options {\n+\tuint32_t slice_map;\n+\t/**< Map of the crypto and compression slices */\n+\tuint16_t has_wireless_slice;\n+\t/**< Wireless Slices supported */\n+\tuint8_t legacy_alg;\n+\t/**< are legacy algorithm supported */\n+};\n+\n enum qat_device_gen {\n \tQAT_GEN1,\n \tQAT_GEN2,\ndiff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c\nindex 666e2bb995..c6ac7a0015 100644\n--- a/drivers/common/qat/qat_device.c\n+++ b/drivers/common/qat/qat_device.c\n@@ -31,7 +31,6 @@ struct qat_service qat_service[QAT_MAX_SERVICES];\n /* per-process array of device data */\n struct qat_device_info qat_pci_devs[RTE_PMD_QAT_MAX_PCI_DEVICES];\n static int qat_nb_pci_devices;\n-int qat_legacy_capa;\n \n /*\n * The set of PCI devices this driver supports\n@@ -331,7 +330,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev)\n \tqat_pci_devs[qat_dev_id].pci_dev = pci_dev;\n \n \tif (wireless_slice_support(pci_dev->id.device_id))\n-\t\tqat_dev->has_wireless_slice = 1;\n+\t\tqat_dev->options.has_wireless_slice = 1;\n \n \tops_hw = qat_dev_hw_spec[qat_dev->qat_dev_gen];\n \tNOT_NULL(ops_hw->qat_dev_get_misc_bar, goto error,\n@@ -352,7 +351,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev)\n \t/* Parse the arguments */\n \tcmdline = qat_dev_cmdline_get_val(qat_dev, QAT_LEGACY_CAPA);\n \tif (cmdline)\n-\t\tqat_legacy_capa = atoi(cmdline);\n+\t\tqat_dev->options.legacy_alg = atoi(cmdline);\n \n \tif (qat_read_qp_config(qat_dev)) {\n \t\tQAT_LOG(ERR,\n@@ -372,7 +371,7 @@ qat_pci_device_allocate(struct rte_pci_device *pci_dev)\n \tNOT_NULL(ops_hw->qat_dev_get_slice_map, goto error,\n \t\t\"QAT internal error! Read slice function not set, gen : %d\",\n \t\tqat_dev_gen);\n-\tif (ops_hw->qat_dev_get_slice_map(&qat_dev->slice_map, pci_dev) < 0) {\n+\tif (ops_hw->qat_dev_get_slice_map(&qat_dev->options.slice_map, pci_dev) < 0) {\n \t\tRTE_LOG(ERR, EAL,\n \t\t\t\"Cannot read slice configuration\\n\");\n \t\tgoto error;\ndiff --git a/drivers/common/qat/qat_device.h b/drivers/common/qat/qat_device.h\nindex 9275156ef8..f5ba1592c3 100644\n--- a/drivers/common/qat/qat_device.h\n+++ b/drivers/common/qat/qat_device.h\n@@ -42,7 +42,6 @@ typedef int (*qat_dev_get_extra_size_t)(void);\n typedef int (*qat_dev_get_slice_map_t)(uint32_t *map,\n \t\tconst struct rte_pci_device *pci_dev);\n \n-extern int qat_legacy_capa;\n char *qat_dev_cmdline_get_val(struct qat_pci_device *qat_dev, const char *key);\n \n struct qat_dev_hw_spec_funcs {\n@@ -122,14 +121,12 @@ struct qat_pci_device {\n \t/**< Address of misc bar */\n \tvoid *dev_private;\n \t/**< Per generation specific information */\n-\tuint32_t slice_map;\n-\t/**< Map of the crypto and compression slices */\n-\tuint16_t has_wireless_slice;\n-\t/**< Wireless Slices supported */\n \tchar *command_line;\n \t/**< Map of the crypto and compression slices */\n \tvoid *pmd[QAT_MAX_SERVICES];\n \t/**< link back to pmd private data */\n+\tstruct qat_options options;\n+\t/**< qat device options */\n };\n \n struct qat_gen_hw_data {\ndiff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c\nindex f95dd33375..ad44b0e01f 100644\n--- a/drivers/common/qat/qat_qp.c\n+++ b/drivers/common/qat/qat_qp.c\n@@ -634,7 +634,7 @@ qat_enqueue_op_burst(void *qp, qat_op_build_request_t op_build_request,\n \twhile (nb_ops_sent != nb_ops_possible) {\n \t\tret = op_build_request(*ops, base_addr + tail,\n \t\t\t\ttmp_qp->op_cookies[tail >> queue->trailz],\n-\t\t\t\ttmp_qp->opaque, tmp_qp->qat_dev_gen);\n+\t\t\t\ttmp_qp);\n \n \t\tif (ret != 0) {\n \t\t\ttmp_qp->stats.enqueue_err_count++;\ndiff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h\nindex ae18fb942e..9fb1bf62ae 100644\n--- a/drivers/common/qat/qat_qp.h\n+++ b/drivers/common/qat/qat_qp.h\n@@ -12,6 +12,7 @@\n \n #define QAT_QP_MIN_INFL_THRESHOLD\t256\n \n+struct qat_qp;\n struct qat_pci_device;\n \n /**\n@@ -57,7 +58,7 @@ struct qat_queue {\n * - EINVAL if error\n **/\n typedef int (*qat_op_build_request_t)(void *in_op, uint8_t *out_msg,\n-\t\tvoid *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen);\n+\t\tvoid *op_cookie, struct qat_qp *qp);\n \n /**\n * Type define qat_op_dequeue_t function pointer, passed in as argument\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\nindex 62874039a9..f20d367404 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen2.c\n@@ -290,7 +290,7 @@ qat_sym_crypto_cap_get_gen2(struct qat_cryptodev_private *internals,\n \tuint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen2);\n \tlegacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities);\n \n-\tif (unlikely(qat_legacy_capa))\n+\tif (unlikely(internals->qat_dev->options.legacy_alg))\n \t\tsize = size + legacy_size;\n \n \tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n@@ -309,7 +309,7 @@ qat_sym_crypto_cap_get_gen2(struct qat_cryptodev_private *internals,\n \t\t\t\tinternals->capa_mz->addr;\n \tstruct rte_cryptodev_capabilities *capabilities;\n \n-\tif (unlikely(qat_legacy_capa)) {\n+\tif (unlikely(internals->qat_dev->options.legacy_alg)) {\n \t\tcapabilities = qat_sym_crypto_legacy_caps_gen2;\n \t\tmemcpy(addr, capabilities, legacy_size);\n \t\taddr += legacy_capa_num;\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\nindex 907c3ce3e2..af664fb9b9 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen3.c\n@@ -206,7 +206,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \tlegacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities);\n \tstruct rte_cryptodev_capabilities *cap;\n \n-\tif (unlikely(qat_legacy_capa))\n+\tif (unlikely(internals->qat_dev->options.legacy_alg))\n \t\tsize = size + legacy_size;\n \n \tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n@@ -225,7 +225,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \t\t\t\tinternals->capa_mz->addr;\n \tstruct rte_cryptodev_capabilities *capabilities;\n \n-\tif (unlikely(qat_legacy_capa)) {\n+\tif (unlikely(internals->qat_dev->options.legacy_alg)) {\n \t\tcapabilities = qat_sym_crypto_legacy_caps_gen3;\n \t\tcapa_num += legacy_capa_num;\n \t} else {\n@@ -233,7 +233,8 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \t}\n \n \tfor (i = 0; i < capa_num; i++, iter++) {\n-\t\tif (unlikely(qat_legacy_capa) && (i == legacy_capa_num)) {\n+\t\tif (unlikely(internals->qat_dev->options.legacy_alg) &&\n+\t\t\t\t(i == legacy_capa_num)) {\n \t\t\tcapabilities = qat_sym_crypto_caps_gen3;\n \t\t\taddr += curr_capa;\n \t\t\tcurr_capa = 0;\n@@ -265,7 +266,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \t\t\tcontinue;\n \t\t}\n \n-\t\tif (internals->qat_dev->has_wireless_slice && (\n+\t\tif (internals->qat_dev->options.has_wireless_slice && (\n \t\t\tcheck_auth_capa(&capabilities[iter],\n \t\t\t\tRTE_CRYPTO_AUTH_KASUMI_F9) ||\n \t\t\tcheck_cipher_capa(&capabilities[iter],\n@@ -279,7 +280,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \t\tmemcpy(addr + curr_capa, capabilities + iter,\n \t\t\tsizeof(struct rte_cryptodev_capabilities));\n \n-\t\tif (internals->qat_dev->has_wireless_slice && (\n+\t\tif (internals->qat_dev->options.has_wireless_slice && (\n \t\t\tcheck_auth_capa(&capabilities[iter],\n \t\t\t\tRTE_CRYPTO_AUTH_ZUC_EIA3))) {\n \t\t\tcap = addr + curr_capa;\n@@ -290,7 +291,7 @@ qat_sym_crypto_cap_get_gen3(struct qat_cryptodev_private *internals,\n \t\t\tcap->sym.auth.digest_size.max = 16;\n \t\t\tcap->sym.auth.digest_size.increment = 4;\n \t\t}\n-\t\tif (internals->qat_dev->has_wireless_slice && (\n+\t\tif (internals->qat_dev->options.has_wireless_slice && (\n \t\t\tcheck_cipher_capa(&capabilities[iter],\n \t\t\t\tRTE_CRYPTO_CIPHER_ZUC_EEA3))) {\n \t\t\tcap = addr + curr_capa;\n@@ -551,7 +552,7 @@ qat_sym_crypto_set_session_gen3(void *cdev, void *session)\n \t\t\t\tctx->qat_cipher_alg ==\n \t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3)) {\n \t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n-\t\t} else if ((internals->qat_dev->has_wireless_slice) &&\n+\t\t} else if ((internals->qat_dev->options.has_wireless_slice) &&\n \t\t\t\t((ctx->aes_cmac ||\n \t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_NULL) &&\n \t\t\t\t(ctx->qat_cipher_alg ==\n@@ -560,7 +561,7 @@ qat_sym_crypto_set_session_gen3(void *cdev, void *session)\n \t\t\t\tICP_QAT_HW_CIPHER_ALGO_ZUC_3G_128_EEA3 ||\n \t\t\t\tctx->qat_cipher_alg == ICP_QAT_HW_CIPHER_ALGO_ZUC_256))) {\n \t\t\tqat_sym_session_set_ext_hash_flags_gen2(ctx, 0);\n-\t\t} else if ((internals->qat_dev->has_wireless_slice) &&\n+\t\t} else if ((internals->qat_dev->options.has_wireless_slice) &&\n \t\t\t(ctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_32 ||\n \t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_64 ||\n \t\t\t\tctx->qat_hash_alg == ICP_QAT_HW_AUTH_ALGO_ZUC_256_MAC_128) &&\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\nindex 11f6078759..5e808a60bf 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen4.c\n@@ -124,7 +124,7 @@ qat_sym_crypto_cap_get_gen4(struct qat_cryptodev_private *internals,\n \tuint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen4);\n \tlegacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities);\n \n-\tif (unlikely(qat_legacy_capa))\n+\tif (unlikely(internals->qat_dev->options.legacy_alg))\n \t\tsize = size + legacy_size;\n \n \tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n@@ -144,7 +144,7 @@ qat_sym_crypto_cap_get_gen4(struct qat_cryptodev_private *internals,\n \n \tstruct rte_cryptodev_capabilities *capabilities;\n \n-\tif (unlikely(qat_legacy_capa)) {\n+\tif (unlikely(internals->qat_dev->options.legacy_alg)) {\n \t\tcapabilities = qat_sym_crypto_legacy_caps_gen4;\n \t\tmemcpy(addr, capabilities, legacy_size);\n \t\taddr += legacy_capa_num;\ndiff --git a/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c b/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c\nindex 1902430480..e1302e9b36 100644\n--- a/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c\n+++ b/drivers/crypto/qat/dev/qat_crypto_pmd_gen5.c\n@@ -167,7 +167,7 @@ qat_sym_crypto_cap_get_gen5(struct qat_cryptodev_private *internals,\n \tlegacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities);\n \tcapa_num = RTE_DIM(qat_sym_crypto_caps_gen5);\n \n-\tif (unlikely(qat_legacy_capa))\n+\tif (unlikely(internals->qat_dev->options.legacy_alg))\n \t\tsize = size + legacy_size;\n \n \tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n@@ -187,7 +187,7 @@ qat_sym_crypto_cap_get_gen5(struct qat_cryptodev_private *internals,\n \n \tstruct rte_cryptodev_capabilities *capabilities;\n \n-\tif (unlikely(qat_legacy_capa)) {\n+\tif (unlikely(internals->qat_dev->options.legacy_alg)) {\n \t\tcapabilities = qat_sym_crypto_legacy_caps_gen5;\n \t\tmemcpy(addr, capabilities, legacy_size);\n \t\taddr += legacy_capa_num;\ndiff --git a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\nindex bdd1647ea2..24e51a9318 100644\n--- a/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n+++ b/drivers/crypto/qat/dev/qat_sym_pmd_gen1.c\n@@ -164,7 +164,7 @@ qat_sym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,\n \tuint32_t legacy_size = sizeof(qat_sym_crypto_legacy_caps_gen1);\n \tlegacy_capa_num = legacy_size/sizeof(struct rte_cryptodev_capabilities);\n \n-\tif (unlikely(qat_legacy_capa))\n+\tif (unlikely(internals->qat_dev->options.legacy_alg))\n \t\tsize = size + legacy_size;\n \n \tinternals->capa_mz = rte_memzone_lookup(capa_memz_name);\n@@ -184,7 +184,7 @@ qat_sym_crypto_cap_get_gen1(struct qat_cryptodev_private *internals,\n \n \tstruct rte_cryptodev_capabilities *capabilities;\n \n-\tif (unlikely(qat_legacy_capa)) {\n+\tif (unlikely(internals->qat_dev->options.legacy_alg)) {\n \t\tcapabilities = qat_sym_crypto_legacy_caps_gen1;\n \t\tmemcpy(addr, capabilities, legacy_size);\n \t\taddr += legacy_capa_num;\n@@ -292,7 +292,7 @@ qat_sym_build_op_auth_gen1(void *in_op, struct qat_sym_session *ctx,\n \tcdev = rte_cryptodev_pmd_get_dev(ctx->dev_id);\n \tinternals = cdev->data->dev_private;\n \n-\tif (internals->qat_dev->has_wireless_slice && !ctx->is_gmac)\n+\tif (internals->qat_dev->options.has_wireless_slice && !ctx->is_gmac)\n \t\tICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(\n \t\t\t\treq->comn_hdr.serv_specif_flags, 0);\n \ndiff --git a/drivers/crypto/qat/qat_asym.c b/drivers/crypto/qat/qat_asym.c\nindex 14d6ec358c..491f5ecd5b 100644\n--- a/drivers/crypto/qat/qat_asym.c\n+++ b/drivers/crypto/qat/qat_asym.c\n@@ -986,7 +986,8 @@ static int\n asym_set_input(struct icp_qat_fw_pke_request *qat_req,\n \t\tstruct qat_asym_op_cookie *cookie,\n \t\tconst struct rte_crypto_asym_op *asym_op,\n-\t\tconst struct rte_crypto_asym_xform *xform)\n+\t\tconst struct rte_crypto_asym_xform *xform,\n+\t\tuint8_t legacy_alg)\n {\n \tswitch (xform->xform_type) {\n \tcase RTE_CRYPTO_ASYM_XFORM_MODEX:\n@@ -995,7 +996,7 @@ asym_set_input(struct icp_qat_fw_pke_request *qat_req,\n \t\treturn modinv_set_input(qat_req, cookie, asym_op, xform);\n \tcase RTE_CRYPTO_ASYM_XFORM_RSA:{\n \t\tif (unlikely((xform->rsa.n.length < RSA_MODULUS_2048_BITS)\n-\t\t\t\t\t&& (qat_legacy_capa == 0)))\n+\t\t\t\t\t&& (legacy_alg == 0)))\n \t\t\treturn RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n \t\treturn rsa_set_input(qat_req, cookie, asym_op, xform);\n \t}\n@@ -1029,9 +1030,10 @@ asym_set_input(struct icp_qat_fw_pke_request *qat_req,\n }\n \n static int\n-qat_asym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,\n-\t\t\t__rte_unused uint64_t *opaque,\n-\t\t\t__rte_unused enum qat_device_gen qat_dev_gen)\n+qat_asym_build_request(void *in_op,\n+\tuint8_t *out_msg,\n+\tvoid *op_cookie,\n+\tstruct qat_qp *qp)\n {\n \tstruct rte_crypto_op *op = (struct rte_crypto_op *)in_op;\n \tstruct rte_crypto_asym_op *asym_op = op->asym;\n@@ -1065,7 +1067,8 @@ qat_asym_build_request(void *in_op, uint8_t *out_msg, void *op_cookie,\n \t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n \t\tgoto error;\n \t}\n-\terr = asym_set_input(qat_req, cookie, asym_op, xform);\n+\terr = asym_set_input(qat_req, cookie, asym_op, xform,\n+\t\tqp->qat_dev->options.legacy_alg);\n \tif (err) {\n \t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n \t\tgoto error;\n@@ -1354,9 +1357,11 @@ qat_asym_session_configure(struct rte_cryptodev *dev __rte_unused,\n \t\tstruct rte_crypto_asym_xform *xform,\n \t\tstruct rte_cryptodev_asym_session *session)\n {\n+\tstruct qat_cryptodev_private *crypto_qat;\n \tstruct qat_asym_session *qat_session;\n \tint ret = 0;\n \n+\tcrypto_qat = dev->data->dev_private;\n \tqat_session = (struct qat_asym_session *) session->sess_private_data;\n \tmemset(qat_session, 0, sizeof(*qat_session));\n \n@@ -1370,7 +1375,7 @@ qat_asym_session_configure(struct rte_cryptodev *dev __rte_unused,\n \t\tbreak;\n \tcase RTE_CRYPTO_ASYM_XFORM_RSA: {\n \t\tif (unlikely((xform->rsa.n.length < RSA_MODULUS_2048_BITS)\n-\t\t\t\t\t&& (qat_legacy_capa == 0))) {\n+\t\t\t\t&& (crypto_qat->qat_dev->options.legacy_alg == 0))) {\n \t\t\tret = -ENOTSUP;\n \t\t\treturn ret;\n \t\t}\n@@ -1594,7 +1599,7 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev)\n \t\t\tatoi(cmdline);\n \t}\n \n-\tif (qat_pci_dev->slice_map & ICP_ACCEL_MASK_PKE_SLICE) {\n+\tif (qat_pci_dev->options.slice_map & ICP_ACCEL_MASK_PKE_SLICE) {\n \t\tQAT_LOG(ERR, \"Device %s does not support PKE slice\",\n \t\t\t\tname);\n \t\trte_cryptodev_pmd_destroy(cryptodev);\n@@ -1604,7 +1609,7 @@ qat_asym_dev_create(struct qat_pci_device *qat_pci_dev)\n \t}\n \n \tif (gen_dev_ops->get_capabilities(internals,\n-\t\t\tcapa_memz_name, qat_pci_dev->slice_map) < 0) {\n+\t\t\tcapa_memz_name, qat_pci_dev->options.slice_map) < 0) {\n \t\tQAT_LOG(ERR,\n \t\t\t\"Device cannot obtain capabilities, destroying PMD for %s\",\n \t\t\tname);\ndiff --git a/drivers/crypto/qat/qat_crypto.h b/drivers/crypto/qat/qat_crypto.h\nindex 2e702927b0..fcd62eda27 100644\n--- a/drivers/crypto/qat/qat_crypto.h\n+++ b/drivers/crypto/qat/qat_crypto.h\n@@ -11,7 +11,6 @@\n \n extern uint8_t qat_sym_driver_id;\n extern uint8_t qat_asym_driver_id;\n-extern int qat_legacy_capa;\n \n /**\n * helper macro to set cryptodev capability range\ndiff --git a/drivers/crypto/qat/qat_sym.c b/drivers/crypto/qat/qat_sym.c\nindex c530496786..b41d1b1def 100644\n--- a/drivers/crypto/qat/qat_sym.c\n+++ b/drivers/crypto/qat/qat_sym.c\n@@ -71,11 +71,11 @@ qat_sym_init_op_cookie(void *op_cookie)\n \n static __rte_always_inline int\n qat_sym_build_request(void *in_op, uint8_t *out_msg,\n-\t\tvoid *op_cookie, uint64_t *opaque, enum qat_device_gen dev_gen)\n+\t\tvoid *op_cookie, struct qat_qp *qp)\n {\n \tstruct rte_crypto_op *op = (struct rte_crypto_op *)in_op;\n-\tuintptr_t sess = (uintptr_t)opaque[0];\n-\tuintptr_t build_request_p = (uintptr_t)opaque[1];\n+\tuintptr_t sess = (uintptr_t)qp->opaque[0];\n+\tuintptr_t build_request_p = (uintptr_t)qp->opaque[1];\n \tqat_sym_build_request_t build_request = (void *)build_request_p;\n \tstruct qat_sym_session *ctx = NULL;\n \tenum rte_proc_type_t proc_type = rte_eal_process_type();\n@@ -92,7 +92,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\tcdev = rte_cryptodev_pmd_get_dev(ctx->dev_id);\n \t\t\tinternals = cdev->data->dev_private;\n \n-\t\t\tif (internals->qat_dev->qat_dev_gen != dev_gen) {\n+\t\t\tif (internals->qat_dev->qat_dev_gen != qp->qat_dev_gen) {\n \t\t\t\top->status =\n \t\t\t\t\tRTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n \t\t\t\treturn -EINVAL;\n@@ -100,7 +100,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \n \t\t\tif (unlikely(ctx->build_request[proc_type] == NULL)) {\n \t\t\t\tint ret =\n-\t\t\t\tqat_sym_gen_dev_ops[dev_gen].set_session(\n+\t\t\t\tqat_sym_gen_dev_ops[qp->qat_dev_gen].set_session(\n \t\t\t\t\t(void *)cdev, (void *)ctx);\n \t\t\t\tif (ret < 0) {\n \t\t\t\t\top->status =\n@@ -110,8 +110,8 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\t}\n \n \t\t\tbuild_request = ctx->build_request[proc_type];\n-\t\t\topaque[0] = (uintptr_t)ctx;\n-\t\t\topaque[1] = (uintptr_t)build_request;\n+\t\t\tqp->opaque[0] = (uintptr_t)ctx;\n+\t\t\tqp->opaque[1] = (uintptr_t)build_request;\n \t\t}\n \t} else if (op->sess_type == RTE_CRYPTO_OP_SECURITY_SESSION) {\n \t\tctx = SECURITY_GET_SESS_PRIV(op->sym->session);\n@@ -145,7 +145,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \t\t\tcdev = rte_cryptodev_pmd_get_dev(ctx->dev_id);\n \t\t\tinternals = cdev->data->dev_private;\n \n-\t\t\tif (internals->qat_dev->qat_dev_gen != dev_gen) {\n+\t\t\tif (internals->qat_dev->qat_dev_gen != qp->qat_dev_gen) {\n \t\t\t\top->status =\n \t\t\t\t\tRTE_CRYPTO_OP_STATUS_INVALID_SESSION;\n \t\t\t\treturn -EINVAL;\n@@ -153,7 +153,7 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \n \t\t\tif (unlikely(ctx->build_request[proc_type] == NULL)) {\n \t\t\t\tint ret =\n-\t\t\t\tqat_sym_gen_dev_ops[dev_gen].set_session(\n+\t\t\t\tqat_sym_gen_dev_ops[qp->qat_dev_gen].set_session(\n \t\t\t\t\t(void *)cdev, (void *)sess);\n \t\t\t\tif (ret < 0) {\n \t\t\t\t\top->status =\n@@ -164,8 +164,8 @@ qat_sym_build_request(void *in_op, uint8_t *out_msg,\n \n \t\t\tsess = (uintptr_t)op->sym->session;\n \t\t\tbuild_request = ctx->build_request[proc_type];\n-\t\t\topaque[0] = sess;\n-\t\t\topaque[1] = (uintptr_t)build_request;\n+\t\t\tqp->opaque[0] = sess;\n+\t\t\tqp->opaque[1] = (uintptr_t)build_request;\n \t\t}\n \t} else { /* RTE_CRYPTO_OP_SESSIONLESS */\n \t\top->status = RTE_CRYPTO_OP_STATUS_INVALID_ARGS;\n@@ -317,7 +317,7 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev)\n \t\tinternals->cipher_crc_offload_enable = atoi(cmdline);\n \n \tif (gen_dev_ops->get_capabilities(internals,\n-\t\t\tcapa_memz_name, qat_pci_dev->slice_map) < 0) {\n+\t\t\tcapa_memz_name, qat_pci_dev->options.slice_map) < 0) {\n \t\tQAT_LOG(ERR,\n \t\t\t\"Device cannot obtain capabilities, destroying PMD for %s\",\n \t\t\tname);\ndiff --git a/drivers/crypto/qat/qat_sym_session.c b/drivers/crypto/qat/qat_sym_session.c\nindex 9e2dba5423..eb267db424 100644\n--- a/drivers/crypto/qat/qat_sym_session.c\n+++ b/drivers/crypto/qat/qat_sym_session.c\n@@ -422,7 +422,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\t\tgoto error_out;\n \t\t}\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n-\t\tif (internals->qat_dev->has_wireless_slice)\n+\t\tif (internals->qat_dev->options.has_wireless_slice)\n \t\t\tis_wireless = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_CIPHER_NULL:\n@@ -543,7 +543,7 @@ qat_sym_session_configure_cipher(struct rte_cryptodev *dev,\n \t\tsession->qat_mode = ICP_QAT_HW_CIPHER_ECB_MODE;\n \t\tif (cipher_xform->key.length == ICP_QAT_HW_ZUC_256_KEY_SZ)\n \t\t\tsession->is_zuc256 = 1;\n-\t\tif (internals->qat_dev->has_wireless_slice)\n+\t\tif (internals->qat_dev->options.has_wireless_slice)\n \t\t\tis_wireless = 1;\n \t\tbreak;\n \tcase RTE_CRYPTO_CIPHER_AES_XTS:\n@@ -933,7 +933,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_AES_CMAC:\n \t\tsession->aes_cmac = 1;\n-\t\tif (!internals->qat_dev->has_wireless_slice) {\n+\t\tif (!internals->qat_dev->options.has_wireless_slice) {\n \t\t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_AES_XCBC_MAC;\n \t\t\tbreak;\n \t\t}\n@@ -968,7 +968,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\tbreak;\n \tcase RTE_CRYPTO_AUTH_SNOW3G_UIA2:\n \t\tsession->qat_hash_alg = ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2;\n-\t\tif (internals->qat_dev->has_wireless_slice) {\n+\t\tif (internals->qat_dev->options.has_wireless_slice) {\n \t\t\tis_wireless = 1;\n \t\t\tsession->is_wireless = 1;\n \t\t\thash_flag = 1 << ICP_QAT_FW_AUTH_HDR_FLAG_SNOW3G_UIA2_BITPOS;\n@@ -1012,7 +1012,7 @@ qat_sym_session_configure_auth(struct rte_cryptodev *dev,\n \t\t\tQAT_LOG(ERR, \"Invalid key length: %d\", key_length);\n \t\t\treturn -ENOTSUP;\n \t\t}\n-\t\tif (internals->qat_dev->has_wireless_slice) {\n+\t\tif (internals->qat_dev->options.has_wireless_slice) {\n \t\t\tis_wireless = 1;\n \t\t\tsession->is_wireless = 1;\n \t\t\thash_flag = 1 << ICP_QAT_FW_AUTH_HDR_FLAG_ZUC_EIA3_BITPOS;\n", "prefixes": [ "v2" ] }