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GET /api/patches/140166/?format=api
{ "id": 140166, "url": "http://patchwork.dpdk.org/api/patches/140166/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240517074448.3146611-6-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240517074448.3146611-6-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240517074448.3146611-6-ndabilpuram@marvell.com", "date": "2024-05-17T07:44:44", "name": "[06/10] net/cnxk: add option to disable custom meta aura", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "97f5eecc1647671b3af11636adad02584429e731", "submitter": { "id": 1202, "url": "http://patchwork.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240517074448.3146611-6-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 31944, "url": "http://patchwork.dpdk.org/api/series/31944/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31944", "date": "2024-05-17T07:44:39", "name": "[01/10] common/cnxk: sync VF root weight with kernel", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31944/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/140166/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/140166/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E5D3844048;\n\tFri, 17 May 2024 09:45:37 +0200 (CEST)", "from mails.dpdk.org (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C2795406FF;\n\tFri, 17 May 2024 09:45:13 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 250E84069D\n for <dev@dpdk.org>; Fri, 17 May 2024 09:45:12 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id\n 44GLNBjI025156\n for <dev@dpdk.org>; Fri, 17 May 2024 00:45:11 -0700", "from dc5-exch05.marvell.com ([199.233.59.128])\n by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 3y5t0vhc3c-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Fri, 17 May 2024 00:45:11 -0700 (PDT)", "from DC5-EXCH05.marvell.com (10.69.176.209) by\n DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1544.4; Fri, 17 May 2024 00:45:10 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com\n (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend\n Transport; Fri, 17 May 2024 00:45:10 -0700", "from hyd1588t430.caveonetworks.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id EF91B3F7059;\n Fri, 17 May 2024 00:45:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=\n from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding:content-type; s=\n pfpt0220; bh=35t8+JYutPqn5AS4qH401jkFWYG8semthp7Px5QVGhs=; b=eIG\n v+BheGIjGWBs81quqO5i5Rj6PVLlcCz/EUGSLcTzdLTnW03f7Bvb2G1paA4k9eZb\n FPMZvpWpXJ3ipWaklh4zcdBtrUv0X8qZdsTRJilkjAQXwg4AQ/pm2SwC/NdDM/47\n uDqoKLBa7Vb3bxiRI1DB5dQiDLKIP6xBmGrYCrQJlkBJ9JocdRJcruXaS0GWUBIE\n 2FclZH/lanN0nfcXw9q64lJv9OgmE8L/fR+NfBSs1PtrQuMQBUy8qRO3Yi1yt06h\n QkqS8AK0+K3psg1MC9b13mpSyUarGcIH7pfztUzRIJsYDNoLYC9AX0TavPAbbKrQ\n +QKTypCcsEugypA3xdw==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>, Harman Kalra <hkalra@marvell.com>", "CC": "<jerinj@marvell.com>, <dev@dpdk.org>", "Subject": "[PATCH 06/10] net/cnxk: add option to disable custom meta aura", "Date": "Fri, 17 May 2024 13:14:44 +0530", "Message-ID": "<20240517074448.3146611-6-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20240517074448.3146611-1-ndabilpuram@marvell.com>", "References": "<20240517074448.3146611-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "n3PAj3sYVn-pWu97mv2ZF4dlVTdpj-zb", "X-Proofpoint-GUID": "n3PAj3sYVn-pWu97mv2ZF4dlVTdpj-zb", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.650,FMLib:17.11.176.26\n definitions=2024-05-16_07,2024-05-15_01,2023-05-22_02", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add option to explicitly disable custom meta aura. Currently\ncustom meta aura is enabled automatically when inl_cpt_channel\nis set i.e inline dev is masking CHAN field in IPsec rules.\n\nAlso decouple the custom meta aura feature from custom sa action\nso that the custom sa action can independently be used.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 13 +++++++++++++\n drivers/common/cnxk/roc_nix_inl.c | 19 +++++++++++++------\n drivers/common/cnxk/roc_nix_inl.h | 1 +\n drivers/common/cnxk/version.map | 1 +\n drivers/net/cnxk/cnxk_ethdev.c | 5 +++++\n drivers/net/cnxk/cnxk_ethdev.h | 3 +++\n drivers/net/cnxk/cnxk_ethdev_devargs.c | 8 +++++++-\n 7 files changed, 43 insertions(+), 7 deletions(-)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex f5f296ee36..99ad224efd 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -444,6 +444,19 @@ Runtime Config Options\n With the above configuration, driver would enable packet inject from ARM cores\n to crypto to process and send back in Rx path.\n \n+- ``Disable custom meta aura feature`` (default ``0``)\n+\n+ Custom meta aura i.e 1:N meta aura is enabled for second pass traffic by default when\n+ ``inl_cpt_channel`` devarg is provided. Provide an option to disable the custom\n+ meta aura feature by setting devarg ``custom_meta_aura_dis`` to ``1``.\n+\n+ For example::\n+\n+ -a 0002:02:00.0,custom_meta_aura_dis=1\n+\n+ With the above configuration, driver would disable custom meta aura feature for\n+ ``0002:02:00.0`` ethdev.\n+\n .. note::\n \n Above devarg parameters are configurable per device, user needs to pass the\ndiff --git a/drivers/common/cnxk/roc_nix_inl.c b/drivers/common/cnxk/roc_nix_inl.c\nindex 7dbeae5017..74a688abbd 100644\n--- a/drivers/common/cnxk/roc_nix_inl.c\n+++ b/drivers/common/cnxk/roc_nix_inl.c\n@@ -872,7 +872,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \tstruct nix *nix = roc_nix_to_nix_priv(roc_nix);\n \tstruct roc_cpt_inline_ipsec_inb_cfg cfg;\n \tstruct idev_cfg *idev = idev_get_cfg();\n-\tstruct nix_inl_dev *inl_dev;\n \tuint16_t bpids[ROC_NIX_MAX_BPID_CNT];\n \tstruct roc_cpt *roc_cpt;\n \tint rc;\n@@ -929,11 +928,6 @@ roc_nix_inl_inb_init(struct roc_nix *roc_nix)\n \tif (rc)\n \t\treturn rc;\n \n-\tinl_dev = idev->nix_inl_dev;\n-\n-\troc_nix->custom_meta_aura_ena = (roc_nix->local_meta_aura_ena &&\n-\t\t\t\t\t ((inl_dev && inl_dev->is_multi_channel) ||\n-\t\t\t\t\t roc_nix->custom_sa_action));\n \tif (!roc_model_is_cn9k() && !roc_errata_nix_no_meta_aura()) {\n \t\tnix->need_meta_aura = true;\n \t\tif (!roc_nix->local_meta_aura_ena || roc_nix->custom_meta_aura_ena)\n@@ -1245,6 +1239,19 @@ roc_nix_inl_dev_is_probed(void)\n \treturn !!idev->nix_inl_dev;\n }\n \n+bool\n+roc_nix_inl_dev_is_multi_channel(void)\n+{\n+\tstruct idev_cfg *idev = idev_get_cfg();\n+\tstruct nix_inl_dev *inl_dev;\n+\n+\tif (idev == NULL || !idev->nix_inl_dev)\n+\t\treturn false;\n+\n+\tinl_dev = idev->nix_inl_dev;\n+\treturn inl_dev->is_multi_channel;\n+}\n+\n bool\n roc_nix_inl_inb_is_enabled(struct roc_nix *roc_nix)\n {\ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nindex 8acd7e0545..ab0965e512 100644\n--- a/drivers/common/cnxk/roc_nix_inl.h\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -115,6 +115,7 @@ int __roc_api roc_nix_inl_dev_stats_get(struct roc_nix_stats *stats);\n uint16_t __roc_api roc_nix_inl_dev_pffunc_get(void);\n int __roc_api roc_nix_inl_dev_cpt_setup(bool use_inl_dev_sso);\n int __roc_api roc_nix_inl_dev_cpt_release(void);\n+bool __roc_api roc_nix_inl_dev_is_multi_channel(void);\n \n /* NIX Inline Inbound API */\n int __roc_api roc_nix_inl_inb_init(struct roc_nix *roc_nix);\ndiff --git a/drivers/common/cnxk/version.map b/drivers/common/cnxk/version.map\nindex 424ad7f484..e8d32b331e 100644\n--- a/drivers/common/cnxk/version.map\n+++ b/drivers/common/cnxk/version.map\n@@ -238,6 +238,7 @@ INTERNAL {\n \troc_nix_inl_dev_dump;\n \troc_nix_inl_dev_fini;\n \troc_nix_inl_dev_init;\n+\troc_nix_inl_dev_is_multi_channel;\n \troc_nix_inl_dev_is_probed;\n \troc_nix_inl_dev_stats_get;\n \troc_nix_inl_dev_lock;\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.c b/drivers/net/cnxk/cnxk_ethdev.c\nindex 1bccebad9f..db8feca620 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.c\n+++ b/drivers/net/cnxk/cnxk_ethdev.c\n@@ -107,6 +107,11 @@ nix_security_setup(struct cnxk_eth_dev *dev)\n \t\tnix->ipsec_in_min_spi = dev->inb.no_inl_dev ? dev->inb.min_spi : 0;\n \t\tnix->ipsec_in_max_spi = dev->inb.no_inl_dev ? dev->inb.max_spi : 1;\n \n+\t\t/* Enable custom meta aura when multi-chan is used */\n+\t\tif (nix->local_meta_aura_ena && roc_nix_inl_dev_is_multi_channel() &&\n+\t\t !dev->inb.custom_meta_aura_dis)\n+\t\t\tnix->custom_meta_aura_ena = true;\n+\n \t\t/* Setup Inline Inbound */\n \t\trc = roc_nix_inl_inb_init(nix);\n \t\tif (rc) {\ndiff --git a/drivers/net/cnxk/cnxk_ethdev.h b/drivers/net/cnxk/cnxk_ethdev.h\nindex 5e040643ab..687c60c27d 100644\n--- a/drivers/net/cnxk/cnxk_ethdev.h\n+++ b/drivers/net/cnxk/cnxk_ethdev.h\n@@ -257,6 +257,9 @@ struct cnxk_eth_dev_sec_inb {\n \n \t/* Lock to synchronize sa setup/release */\n \trte_spinlock_t lock;\n+\n+\t/* Disable custom meta aura */\n+\tbool custom_meta_aura_dis;\n };\n \n /* Outbound security data */\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c\nindex 1bab19fc23..3454295d7d 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c\n@@ -280,6 +280,7 @@ parse_val_u16(const char *key, const char *value, void *extra_args)\n #define CNXK_NIX_META_BUF_SZ\t\"meta_buf_sz\"\n #define CNXK_FLOW_AGING_POLL_FREQ\t\"aging_poll_freq\"\n #define CNXK_NIX_RX_INJ_ENABLE\t\"rx_inj_ena\"\n+#define CNXK_CUSTOM_META_AURA_DIS \"custom_meta_aura_dis\"\n \n int\n cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n@@ -291,6 +292,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n \tuint32_t ipsec_in_max_spi = BIT(8) - 1;\n \tuint16_t sqb_slack = ROC_NIX_SQB_SLACK;\n \tuint32_t ipsec_out_max_sa = BIT(12);\n+\tuint16_t custom_meta_aura_dis = 0;\n \tuint16_t flow_prealloc_size = 1;\n \tuint16_t switch_header_type = 0;\n \tuint16_t flow_max_priority = 3;\n@@ -358,6 +360,8 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n \trte_kvargs_process(kvlist, CNXK_FLOW_AGING_POLL_FREQ, &parse_val_u16,\n \t\t\t &aging_thread_poll_freq);\n \trte_kvargs_process(kvlist, CNXK_NIX_RX_INJ_ENABLE, &parse_flag, &rx_inj_ena);\n+\trte_kvargs_process(kvlist, CNXK_CUSTOM_META_AURA_DIS, &parse_flag,\n+\t\t\t &custom_meta_aura_dis);\n \trte_kvargs_free(kvlist);\n \n null_devargs:\n@@ -366,6 +370,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)\n \tdev->inb.no_inl_dev = !!no_inl_dev;\n \tdev->inb.min_spi = ipsec_in_min_spi;\n \tdev->inb.max_spi = ipsec_in_max_spi;\n+\tdev->inb.custom_meta_aura_dis = custom_meta_aura_dis;\n \tdev->outb.max_sa = ipsec_out_max_sa;\n \tdev->outb.nb_desc = outb_nb_desc;\n \tdev->outb.nb_crypto_qs = outb_nb_crypto_qs;\n@@ -415,4 +420,5 @@ RTE_PMD_REGISTER_PARAM_STRING(net_cnxk,\n \t\t\t CNXK_CUSTOM_SA_ACT \"=1\"\n \t\t\t CNXK_SQB_SLACK \"=<12-512>\"\n \t\t\t CNXK_FLOW_AGING_POLL_FREQ \"=<10-65535>\"\n-\t\t\t CNXK_NIX_RX_INJ_ENABLE \"=1\");\n+\t\t\t CNXK_NIX_RX_INJ_ENABLE \"=1\"\n+\t\t\t CNXK_CUSTOM_META_AURA_DIS \"=1\");\n", "prefixes": [ "06/10" ] }