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GET /api/patches/140184/?format=api
{ "id": 140184, "url": "http://patchwork.dpdk.org/api/patches/140184/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20240520062524.2401676-1-dongzhou@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20240520062524.2401676-1-dongzhou@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20240520062524.2401676-1-dongzhou@nvidia.com", "date": "2024-05-20T06:25:24", "name": "net/mlx5/hws: add support for NVGRE matching", "commit_ref": null, "pull_url": null, "state": "awaiting-upstream", "archived": false, "hash": "111e8a5cbc2f279ba278703fedd602533a3f8538", "submitter": { "id": 2011, "url": "http://patchwork.dpdk.org/api/people/2011/?format=api", "name": "Dong Zhou", "email": "dongzhou@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20240520062524.2401676-1-dongzhou@nvidia.com/mbox/", "series": [ { "id": 31949, "url": "http://patchwork.dpdk.org/api/series/31949/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=31949", "date": "2024-05-20T06:25:24", "name": "net/mlx5/hws: add support for NVGRE matching", "version": 1, "mbox": "http://patchwork.dpdk.org/series/31949/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/140184/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/140184/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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Matan Azrad <matan@nvidia.com>", "CC": "<dev@dpdk.org>, <thomas@monjalon.net>, <rasland@nvidia.com>", "Subject": "[PATCH] net/mlx5/hws: add support for NVGRE matching", "Date": "Mon, 20 May 2024 09:25:24 +0300", "Message-ID": "<20240520062524.2401676-1-dongzhou@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[10.126.231.35]", "X-ClientProxiedBy": "rnnvmail203.nvidia.com (10.129.68.9) To\n rnnvmail201.nvidia.com (10.129.68.8)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "MWH0EPF000A6730:EE_|CYYPR12MB8749:EE_", "X-MS-Office365-Filtering-Correlation-Id": "73838085-8594-44de-8bd6-08dc7895b462", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230031|82310400017|36860700004|376005|1800799015;", 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"X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org" }, "content": "Add HWS support for RTE_FLOW_ITEM_TYPE_NVGRE item\nall fields.\n\nSigned-off-by: Dong Zhou <dongzhou@nvidia.com>\nAcked-by: Alex Vesker <valex@nvidia.com>\n---\n doc/guides/nics/mlx5.rst | 10 +++\n drivers/net/mlx5/hws/mlx5dr_definer.c | 87 +++++++++++++++++++++++++++\n drivers/net/mlx5/hws/mlx5dr_definer.h | 3 +\n drivers/net/mlx5/mlx5_flow_hw.c | 1 +\n 4 files changed, 101 insertions(+)", "diff": "diff --git a/doc/guides/nics/mlx5.rst b/doc/guides/nics/mlx5.rst\nindex 9b2fe07fd3..06f5cb6454 100644\n--- a/doc/guides/nics/mlx5.rst\n+++ b/doc/guides/nics/mlx5.rst\n@@ -875,6 +875,16 @@ Limitations\n \n Matching on checksum and sequence needs MLNX_OFED 5.6+.\n \n+- Matching on NVGRE header:\n+\n+ - c_rc_k_s_rsvd0_ver\n+ - protocol\n+ - tni\n+ - flow_id\n+\n+ In SW steering (``dv_flow_en`` = 1), only tni is supported.\n+ In HW steering (``dv_flow_en`` = 2), all fields are supported.\n+\n - The NIC egress flow rules on representor port are not supported.\n \n - A driver limitation for ``RTE_FLOW_ACTION_TYPE_PORT_REPRESENTOR`` action\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.c b/drivers/net/mlx5/hws/mlx5dr_definer.c\nindex 35a2ed2048..42fb4c32c6 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.c\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.c\n@@ -15,6 +15,9 @@\n #define UDP_GENEVE_PORT 6081\n #define UDP_ROCEV2_PORT\t4791\n #define DR_FLOW_LAYER_TUNNEL_NO_MPLS (MLX5_FLOW_LAYER_TUNNEL & ~MLX5_FLOW_LAYER_MPLS)\n+#define NVGRE_PORT 0x6558\n+#define NVGRE_C_RSVD0_VER 0x2000\n+#define NVGRE_C_RSVD0_VER_MASK 0xB000\n \n #define STE_NO_VLAN\t0x0\n #define STE_SVLAN\t0x1\n@@ -220,6 +223,12 @@ struct mlx5dr_definer_conv_data {\n \tX(SET_BE32,\tgre_opt_key,\t\tv->key.key,\t\trte_flow_item_gre_opt) \\\n \tX(SET_BE32,\tgre_opt_seq,\t\tv->sequence.sequence,\trte_flow_item_gre_opt) \\\n \tX(SET_BE16,\tgre_opt_checksum,\tv->checksum_rsvd.checksum,\trte_flow_item_gre_opt) \\\n+\tX(SET,\t\tnvgre_def_c_rsvd0_ver,\tNVGRE_C_RSVD0_VER,\trte_flow_item_nvgre) \\\n+\tX(SET,\t\tnvgre_def_c_rsvd0_ver_mask,\tNVGRE_C_RSVD0_VER_MASK,\trte_flow_item_nvgre) \\\n+\tX(SET,\t\tnvgre_def_protocol,\tNVGRE_PORT,\t\trte_flow_item_nvgre) \\\n+\tX(SET_BE16,\tnvgre_c_rsvd0_ver,\tv->c_k_s_rsvd0_ver,\trte_flow_item_nvgre) \\\n+\tX(SET_BE16,\tnvgre_protocol,\t\tv->protocol,\t\trte_flow_item_nvgre) \\\n+\tX(SET_BE32P,\tnvgre_dw1,\t\t&v->tni[0],\t\trte_flow_item_nvgre) \\\n \tX(SET,\t\tmeter_color,\t\trte_col_2_mlx5_col(v->color),\trte_flow_item_meter_color) \\\n \tX(SET_BE32, ipsec_spi, v->hdr.spi, rte_flow_item_esp) \\\n \tX(SET_BE32, ipsec_sequence_number, v->hdr.seq, rte_flow_item_esp) \\\n@@ -2012,6 +2021,80 @@ mlx5dr_definer_conv_item_gre_key(struct mlx5dr_definer_conv_data *cd,\n \treturn 0;\n }\n \n+static int\n+mlx5dr_definer_conv_item_nvgre(struct mlx5dr_definer_conv_data *cd,\n+\t\t\t\tstruct rte_flow_item *item,\n+\t\t\t\tint item_idx)\n+{\n+\tconst struct rte_flow_item_nvgre *m = item->mask;\n+\tstruct mlx5dr_definer_fc *fc;\n+\tbool inner = cd->tunnel;\n+\n+\tif (inner) {\n+\t\tDR_LOG(ERR, \"Inner gre item not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn rte_errno;\n+\t}\n+\n+\tif (!cd->relaxed) {\n+\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\tif (!fc->tag_set) {\n+\t\t\tfc = &cd->fc[DR_CALC_FNAME(IP_PROTOCOL, inner)];\n+\t\t\tfc->item_idx = item_idx;\n+\t\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\t\tfc->tag_set = &mlx5dr_definer_ipv4_protocol_gre_set;\n+\t\t\tDR_CALC_SET(fc, eth_l3, protocol_next_header, inner);\n+\t\t}\n+\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_NVGRE_C_K_S];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_nvgre_def_c_rsvd0_ver_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_nvgre_def_c_rsvd0_ver_mask_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->bit_mask = __mlx5_mask(header_gre, c_rsvd0_ver);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_gre, c_rsvd0_ver);\n+\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_NVGRE_PROTOCOL];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_nvgre_def_protocol_set;\n+\t\tfc->tag_mask_set = &mlx5dr_definer_ones_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->byte_off += MLX5_BYTE_OFF(header_gre, gre_protocol);\n+\t\tfc->bit_mask = __mlx5_mask(header_gre, gre_protocol);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_gre, gre_protocol);\n+\t}\n+\n+\tif (!m)\n+\t\treturn 0;\n+\n+\tif (m->c_k_s_rsvd0_ver) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_NVGRE_C_K_S];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_nvgre_c_rsvd0_ver_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->bit_mask = __mlx5_mask(header_gre, c_rsvd0_ver);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_gre, c_rsvd0_ver);\n+\t}\n+\n+\tif (m->protocol) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_NVGRE_PROTOCOL];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_nvgre_protocol_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_0);\n+\t\tfc->byte_off += MLX5_BYTE_OFF(header_gre, gre_protocol);\n+\t\tfc->bit_mask = __mlx5_mask(header_gre, gre_protocol);\n+\t\tfc->bit_off = __mlx5_dw_bit_off(header_gre, gre_protocol);\n+\t}\n+\n+\tif (!is_mem_zero(m->tni, 4)) {\n+\t\tfc = &cd->fc[MLX5DR_DEFINER_FNAME_NVGRE_DW1];\n+\t\tfc->item_idx = item_idx;\n+\t\tfc->tag_set = &mlx5dr_definer_nvgre_dw1_set;\n+\t\tDR_CALC_SET_HDR(fc, tunnel_header, tunnel_header_2);\n+\t}\n+\treturn 0;\n+}\n+\n static int\n mlx5dr_definer_conv_item_ptype(struct mlx5dr_definer_conv_data *cd,\n \t\t\t struct rte_flow_item *item,\n@@ -3195,6 +3278,10 @@ mlx5dr_definer_conv_items_to_hl(struct mlx5dr_context *ctx,\n \t\t\tbreak;\n \t\tcase RTE_FLOW_ITEM_TYPE_VOID:\n \t\t\tbreak;\n+\t\tcase RTE_FLOW_ITEM_TYPE_NVGRE:\n+\t\t\tret = mlx5dr_definer_conv_item_nvgre(&cd, items, i);\n+\t\t\titem_flags |= MLX5_FLOW_LAYER_NVGRE;\n+\t\t\tbreak;\n \t\tdefault:\n \t\t\tDR_LOG(ERR, \"Unsupported item type %d\", items->type);\n \t\t\tgoto not_supp;\ndiff --git a/drivers/net/mlx5/hws/mlx5dr_definer.h b/drivers/net/mlx5/hws/mlx5dr_definer.h\nindex ca530ebf30..3204bb825f 100644\n--- a/drivers/net/mlx5/hws/mlx5dr_definer.h\n+++ b/drivers/net/mlx5/hws/mlx5dr_definer.h\n@@ -151,6 +151,9 @@ enum mlx5dr_definer_fname {\n \tMLX5DR_DEFINER_FNAME_GRE_OPT_KEY,\n \tMLX5DR_DEFINER_FNAME_GRE_OPT_SEQ,\n \tMLX5DR_DEFINER_FNAME_GRE_OPT_CHECKSUM,\n+\tMLX5DR_DEFINER_FNAME_NVGRE_C_K_S,\n+\tMLX5DR_DEFINER_FNAME_NVGRE_PROTOCOL,\n+\tMLX5DR_DEFINER_FNAME_NVGRE_DW1,\n \tMLX5DR_DEFINER_FNAME_INTEGRITY_O,\n \tMLX5DR_DEFINER_FNAME_INTEGRITY_I,\n \tMLX5DR_DEFINER_FNAME_ICMP_DW1,\ndiff --git a/drivers/net/mlx5/mlx5_flow_hw.c b/drivers/net/mlx5/mlx5_flow_hw.c\nindex 825f258065..b864808820 100644\n--- a/drivers/net/mlx5/mlx5_flow_hw.c\n+++ b/drivers/net/mlx5/mlx5_flow_hw.c\n@@ -7652,6 +7652,7 @@ flow_hw_pattern_validate(struct rte_eth_dev *dev,\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE_KEY:\n \t\tcase RTE_FLOW_ITEM_TYPE_GRE_OPTION:\n+\t\tcase RTE_FLOW_ITEM_TYPE_NVGRE:\n \t\tcase RTE_FLOW_ITEM_TYPE_ICMP:\n \t\tcase RTE_FLOW_ITEM_TYPE_ICMP6:\n \t\tcase RTE_FLOW_ITEM_TYPE_ICMP6_ECHO_REQUEST:\n", "prefixes": [] }