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GET /api/patches/4561/?format=api
{ "id": 4561, "url": "http://patchwork.dpdk.org/api/patches/4561/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1430406219-23901-10-git-send-email-helin.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1430406219-23901-10-git-send-email-helin.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1430406219-23901-10-git-send-email-helin.zhang@intel.com", "date": "2015-04-30T15:03:15", "name": "[dpdk-dev,v2,09/33] i40e/base: update of shadow RAM read/write functions", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f3088b1719615de344b2494cce64acf2e0ccb8ad", "submitter": { "id": 14, "url": "http://patchwork.dpdk.org/api/people/14/?format=api", "name": "Zhang, Helin", "email": "helin.zhang@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1430406219-23901-10-git-send-email-helin.zhang@intel.com/mbox/", "series": [], "comments": "http://patchwork.dpdk.org/api/patches/4561/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/4561/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id DECCFCBFE;\n\tThu, 30 Apr 2015 17:04:11 +0200 (CEST)", "from mga11.intel.com (mga11.intel.com [192.55.52.93])\n\tby dpdk.org (Postfix) with ESMTP id C2858CBCE\n\tfor <dev@dpdk.org>; Thu, 30 Apr 2015 17:04:09 +0200 (CEST)", "from fmsmga003.fm.intel.com ([10.253.24.29])\n\tby fmsmga102.fm.intel.com with ESMTP; 30 Apr 2015 08:04:08 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby FMSMGA003.fm.intel.com with ESMTP; 30 Apr 2015 08:04:07 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id t3UF443n028527;\n\tThu, 30 Apr 2015 23:04:04 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid t3UF403h023999; Thu, 30 Apr 2015 23:04:02 +0800", "(from hzhan75@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id t3UF40rF023995; \n\tThu, 30 Apr 2015 23:04:00 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.11,677,1422950400\"; d=\"scan'208\";a=\"487715764\"", "From": "Helin Zhang <helin.zhang@intel.com>", "To": "dev@dpdk.org", "Date": "Thu, 30 Apr 2015 23:03:15 +0800", "Message-Id": "<1430406219-23901-10-git-send-email-helin.zhang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1430406219-23901-1-git-send-email-helin.zhang@intel.com>", "References": "<1429518150-28098-1-git-send-email-helin.zhang@intel.com>\n\t<1430406219-23901-1-git-send-email-helin.zhang@intel.com>", "Cc": "monica.kenguva@intel.com, steven.j.murray@intel.com,\n\tshannon.nelson@intel.com", "Subject": "[dpdk-dev] [PATCH v2 09/33] i40e/base: update of shadow RAM\n\tread/write functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "To support different hardware, shadow RAM read should be done via\nSRCTL register or AQ command, and shadow RAM write should be done\nvia AQ command only.\n\nSigned-off-by: Helin Zhang <helin.zhang@intel.com>\n---\n lib/librte_pmd_i40e/i40e/i40e_nvm.c | 196 ++++++++++++++++++++++++++++++++++--\n 1 file changed, 190 insertions(+), 6 deletions(-)", "diff": "diff --git a/lib/librte_pmd_i40e/i40e/i40e_nvm.c b/lib/librte_pmd_i40e/i40e/i40e_nvm.c\nindex 2b70508..c63f5ba 100644\n--- a/lib/librte_pmd_i40e/i40e/i40e_nvm.c\n+++ b/lib/librte_pmd_i40e/i40e/i40e_nvm.c\n@@ -33,6 +33,18 @@ POSSIBILITY OF SUCH DAMAGE.\n \n #include \"i40e_prototype.h\"\n \n+enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *data);\n+enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *data);\n+enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t\t u16 *words, u16 *data);\n+enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *words, u16 *data);\n+enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,\n+\t\t\t\t u32 offset, u16 words, void *data,\n+\t\t\t\t bool last_command);\n+\n /**\n * i40e_init_nvm_ops - Initialize NVM function pointers\n * @hw: pointer to the HW structure\n@@ -190,13 +202,29 @@ static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)\n enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,\n \t\t\t\t\t u16 *data)\n {\n+\treturn i40e_read_nvm_word_srctl(hw, offset, data);\n+}\n+\n+/**\n+ * i40e_read_nvm_word_srctl - Reads Shadow RAM via SRCTL register\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.\n+ **/\n+enum i40e_status_code i40e_read_nvm_word_srctl(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *data)\n+{\n \tenum i40e_status_code ret_code = I40E_ERR_TIMEOUT;\n \tu32 sr_reg;\n \n-\tDEBUGFUNC(\"i40e_read_nvm_srctl\");\n+\tDEBUGFUNC(\"i40e_read_nvm_word_srctl\");\n \n \tif (offset >= hw->nvm.sr_size) {\n-\t\tDEBUGOUT(\"NVM read error: Offset beyond Shadow RAM limit.\\n\");\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM read error: Offset %d beyond Shadow RAM limit %d\\n\",\n+\t\t\t offset, hw->nvm.sr_size);\n \t\tret_code = I40E_ERR_PARAM;\n \t\tgoto read_nvm_exit;\n \t}\n@@ -219,14 +247,36 @@ enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,\n \t\t}\n \t}\n \tif (ret_code != I40E_SUCCESS)\n-\t\tDEBUGOUT1(\"NVM read error: Couldn't access Shadow RAM address: 0x%x\\n\",\n-\t\t\t offset);\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM read error: Couldn't access Shadow RAM address: 0x%x\\n\",\n+\t\t\t offset);\n \n read_nvm_exit:\n \treturn ret_code;\n }\n \n /**\n+ * i40e_read_nvm_word_aq - Reads Shadow RAM via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)\n+ * @data: word read from the Shadow RAM\n+ *\n+ * Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.\n+ **/\n+enum i40e_status_code i40e_read_nvm_word_aq(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *data)\n+{\n+\tenum i40e_status_code ret_code = I40E_ERR_TIMEOUT;\n+\n+\tDEBUGFUNC(\"i40e_read_nvm_word_aq\");\n+\n+\tret_code = i40e_read_nvm_aq(hw, 0x0, offset, 1, data, true);\n+\t*data = LE16_TO_CPU(*(__le16 *)data);\n+\n+\treturn ret_code;\n+}\n+\n+/**\n * i40e_read_nvm_buffer - Reads Shadow RAM buffer\n * @hw: pointer to the HW structure\n * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n@@ -240,15 +290,32 @@ read_nvm_exit:\n enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,\n \t\t\t\t\t u16 *words, u16 *data)\n {\n+\treturn i40e_read_nvm_buffer_srctl(hw, offset, words, data);\n+}\n+\n+/**\n+ * i40e_read_nvm_buffer_srctl - Reads Shadow RAM buffer via SRCTL register\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()\n+ * method. The buffer read is preceded by the NVM ownership take\n+ * and followed by the release.\n+ **/\n+enum i40e_status_code i40e_read_nvm_buffer_srctl(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t\t u16 *words, u16 *data)\n+{\n \tenum i40e_status_code ret_code = I40E_SUCCESS;\n \tu16 index, word;\n \n-\tDEBUGFUNC(\"i40e_read_nvm_buffer\");\n+\tDEBUGFUNC(\"i40e_read_nvm_buffer_srctl\");\n \n \t/* Loop thru the selected region */\n \tfor (word = 0; word < *words; word++) {\n \t\tindex = offset + word;\n-\t\tret_code = i40e_read_nvm_word(hw, index, &data[word]);\n+\t\tret_code = i40e_read_nvm_word_srctl(hw, index, &data[word]);\n \t\tif (ret_code != I40E_SUCCESS)\n \t\t\tbreak;\n \t}\n@@ -258,6 +325,114 @@ enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,\n \n \treturn ret_code;\n }\n+\n+/**\n+ * i40e_read_nvm_buffer_aq - Reads Shadow RAM buffer via AQ\n+ * @hw: pointer to the HW structure\n+ * @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).\n+ * @words: (in) number of words to read; (out) number of words actually read\n+ * @data: words read from the Shadow RAM\n+ *\n+ * Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_aq()\n+ * method. The buffer read is preceded by the NVM ownership take\n+ * and followed by the release.\n+ **/\n+enum i40e_status_code i40e_read_nvm_buffer_aq(struct i40e_hw *hw, u16 offset,\n+\t\t\t\t\t u16 *words, u16 *data)\n+{\n+\tenum i40e_status_code ret_code;\n+\tu16 read_size = *words;\n+\tbool last_cmd = false;\n+\tu16 words_read = 0;\n+\tu16 i = 0;\n+\n+\tDEBUGFUNC(\"i40e_read_nvm_buffer_aq\");\n+\n+\tdo {\n+\t\t/* Calculate number of bytes we should read in this step.\n+\t\t * FVL AQ do not allow to read more than one page at a time or\n+\t\t * to cross page boundaries.\n+\t\t */\n+\t\tif (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)\n+\t\t\tread_size = min(*words,\n+\t\t\t\t\t(u16)(I40E_SR_SECTOR_SIZE_IN_WORDS -\n+\t\t\t\t (offset % I40E_SR_SECTOR_SIZE_IN_WORDS)));\n+\t\telse\n+\t\t\tread_size = min((*words - words_read),\n+\t\t\t\t\tI40E_SR_SECTOR_SIZE_IN_WORDS);\n+\n+\t\t/* Check if this is last command, if so set proper flag */\n+\t\tif ((words_read + read_size) >= *words)\n+\t\t\tlast_cmd = true;\n+\n+\t\tret_code = i40e_read_nvm_aq(hw, 0x0, offset, read_size,\n+\t\t\t\t\t data + words_read, last_cmd);\n+\t\tif (ret_code != I40E_SUCCESS)\n+\t\t\tgoto read_nvm_buffer_aq_exit;\n+\n+\t\t/* Increment counter for words already read and move offset to\n+\t\t * new read location\n+\t\t */\n+\t\twords_read += read_size;\n+\t\toffset += read_size;\n+\t} while (words_read < *words);\n+\n+\tfor (i = 0; i < *words; i++)\n+\t\tdata[i] = LE16_TO_CPU(((__le16 *)data)[i]);\n+\n+read_nvm_buffer_aq_exit:\n+\t*words = words_read;\n+\treturn ret_code;\n+}\n+\n+/**\n+ * i40e_read_nvm_aq - Read Shadow RAM.\n+ * @hw: pointer to the HW structure.\n+ * @module_pointer: module pointer location in words from the NVM beginning\n+ * @offset: offset in words from module start\n+ * @words: number of words to write\n+ * @data: buffer with words to write to the Shadow RAM\n+ * @last_command: tells the AdminQ that this is the last command\n+ *\n+ * Writes a 16 bit words buffer to the Shadow RAM using the admin command.\n+ **/\n+enum i40e_status_code i40e_read_nvm_aq(struct i40e_hw *hw, u8 module_pointer,\n+\t\t\t\t u32 offset, u16 words, void *data,\n+\t\t\t\t bool last_command)\n+{\n+\tenum i40e_status_code ret_code = I40E_ERR_NVM;\n+\n+\tDEBUGFUNC(\"i40e_read_nvm_aq\");\n+\n+\t/* Here we are checking the SR limit only for the flat memory model.\n+\t * We cannot do it for the module-based model, as we did not acquire\n+\t * the NVM resource yet (we cannot get the module pointer value).\n+\t * Firmware will check the module-based model.\n+\t */\n+\tif ((offset + words) > hw->nvm.sr_size)\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM write error: offset %d beyond Shadow RAM limit %d\\n\",\n+\t\t\t (offset + words), hw->nvm.sr_size);\n+\telse if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)\n+\t\t/* We can write only up to 4KB (one sector), in one AQ write */\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM write fail error: tried to write %d words, limit is %d.\\n\",\n+\t\t\t words, I40E_SR_SECTOR_SIZE_IN_WORDS);\n+\telse if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)\n+\t\t != (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))\n+\t\t/* A single write cannot spread over two sectors */\n+\t\ti40e_debug(hw, I40E_DEBUG_NVM,\n+\t\t\t \"NVM write error: cannot spread over two sectors in a single write offset=%d words=%d\\n\",\n+\t\t\t offset, words);\n+\telse\n+\t\tret_code = i40e_aq_read_nvm(hw, module_pointer,\n+\t\t\t\t\t 2 * offset, /*bytes*/\n+\t\t\t\t\t 2 * words, /*bytes*/\n+\t\t\t\t\t data, last_command, NULL);\n+\n+\treturn ret_code;\n+}\n+\n /**\n * i40e_write_nvm_aq - Writes Shadow RAM.\n * @hw: pointer to the HW structure.\n@@ -316,6 +491,8 @@ enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,\n {\n \tDEBUGFUNC(\"i40e_write_nvm_word\");\n \n+\t*((__le16 *)data) = CPU_TO_LE16(*((u16 *)data));\n+\n \t/* Value 0x00 below means that we treat SR as a flat mem */\n \treturn i40e_write_nvm_aq(hw, 0x00, offset, 1, data, false);\n }\n@@ -337,8 +514,15 @@ enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,\n \t\t\t\t\t u8 module_pointer, u32 offset,\n \t\t\t\t\t u16 words, void *data)\n {\n+\t__le16 *le_word_ptr = (__le16 *)data;\n+\tu16 *word_ptr = (u16 *)data;\n+\tu32 i = 0;\n+\n \tDEBUGFUNC(\"i40e_write_nvm_buffer\");\n \n+\tfor (i = 0; i < words; i++)\n+\t\tle_word_ptr[i] = CPU_TO_LE16(word_ptr[i]);\n+\n \t/* Here we will only write one buffer as the size of the modules\n \t * mirrored in the Shadow RAM is always less than 4K.\n \t */\n", "prefixes": [ "dpdk-dev", "v2", "09/33" ] }