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GET /api/patches/56833/?format=api
{ "id": 56833, "url": "http://patchwork.dpdk.org/api/patches/56833/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1563786795-14027-10-git-send-email-matan@mellanox.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1563786795-14027-10-git-send-email-matan@mellanox.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1563786795-14027-10-git-send-email-matan@mellanox.com", "date": "2019-07-22T09:12:56", "name": "[09/28] net/mlx5: create advanced RxQ object using new API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "0d8d4da3108ea667fcee550bcc0f10ed7e61d56f", "submitter": { "id": 796, "url": "http://patchwork.dpdk.org/api/people/796/?format=api", "name": "Matan Azrad", "email": "matan@mellanox.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1563786795-14027-10-git-send-email-matan@mellanox.com/mbox/", "series": [ { "id": 5639, "url": "http://patchwork.dpdk.org/api/series/5639/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=5639", "date": "2019-07-22T09:12:48", "name": "net/mlx5: support LRO", "version": 1, "mbox": "http://patchwork.dpdk.org/series/5639/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/56833/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/56833/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 5CF5C1BE1E;\n\tMon, 22 Jul 2019 11:13:46 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n\tby dpdk.org (Postfix) with ESMTP id 50B571BDF2\n\tfor <dev@dpdk.org>; Mon, 22 Jul 2019 11:13:29 +0200 (CEST)", "from Internal Mail-Server by MTLPINE2 (envelope-from\n\tmatan@mellanox.com)\n\twith ESMTPS (AES256-SHA encrypted); 22 Jul 2019 12:13:23 +0300", "from pegasus07.mtr.labs.mlnx (pegasus07.mtr.labs.mlnx\n\t[10.210.16.112])\n\tby labmailer.mlnx (8.13.8/8.13.8) with ESMTP id x6M9DMjY010084;\n\tMon, 22 Jul 2019 12:13:23 +0300" ], "From": "Matan Azrad <matan@mellanox.com>", "To": "Shahaf Shuler <shahafs@mellanox.com>, Yongseok Koh <yskoh@mellanox.com>, \n\tViacheslav Ovsiienko <viacheslavo@mellanox.com>", "Cc": "dev@dpdk.org, Dekel Peled <dekelp@mellanox.com>", "Date": "Mon, 22 Jul 2019 09:12:56 +0000", "Message-Id": "<1563786795-14027-10-git-send-email-matan@mellanox.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "References": "<1563786795-14027-1-git-send-email-matan@mellanox.com>", "Subject": "[dpdk-dev] [PATCH 09/28] net/mlx5: create advanced RxQ object using\n\tnew API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Dekel Peled <dekelp@mellanox.com>\n\nImplement function mlx5_devx_cmd_create_rq() to create RQ object using\nDevX API.\nAdd related structs in mlx5.h and mlx5_prm.h.\n\nSigned-off-by: Dekel Peled <dekelp@mellanox.com>\nAcked-by: Matan Azrad <matan@mellanox.com>\n---\n drivers/net/mlx5/mlx5.h | 50 +++++++++++++++++\n drivers/net/mlx5/mlx5_devx_cmds.c | 102 +++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_prm.h | 110 ++++++++++++++++++++++++++++++++++++++\n 3 files changed, 262 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5.h b/drivers/net/mlx5/mlx5.h\nindex 471e220..7ad6687 100644\n--- a/drivers/net/mlx5/mlx5.h\n+++ b/drivers/net/mlx5/mlx5.h\n@@ -260,6 +260,52 @@ struct mlx5_dev_config {\n \tstruct mlx5_lro_config lro; /* LRO configuration. */\n };\n \n+struct mlx5_devx_wq_attr {\n+\tuint32_t wq_type:4;\n+\tuint32_t wq_signature:1;\n+\tuint32_t end_padding_mode:2;\n+\tuint32_t cd_slave:1;\n+\tuint32_t hds_skip_first_sge:1;\n+\tuint32_t log2_hds_buf_size:3;\n+\tuint32_t page_offset:5;\n+\tuint32_t lwm:16;\n+\tuint32_t pd:24;\n+\tuint32_t uar_page:24;\n+\tuint64_t dbr_addr;\n+\tuint32_t hw_counter;\n+\tuint32_t sw_counter;\n+\tuint32_t log_wq_stride:4;\n+\tuint32_t log_wq_pg_sz:5;\n+\tuint32_t log_wq_sz:5;\n+\tuint32_t dbr_umem_valid:1;\n+\tuint32_t wq_umem_valid:1;\n+\tuint32_t log_hairpin_num_packets:5;\n+\tuint32_t log_hairpin_data_sz:5;\n+\tuint32_t single_wqe_log_num_of_strides:4;\n+\tuint32_t two_byte_shift_en:1;\n+\tuint32_t single_stride_log_num_of_bytes:3;\n+\tuint32_t dbr_umem_id;\n+\tuint32_t wq_umem_id;\n+\tuint64_t wq_umem_offset;\n+};\n+\n+/* Create RQ attributes structure, used by create RQ operation. */\n+struct mlx5_devx_create_rq_attr {\n+\tuint32_t rlky:1;\n+\tuint32_t delay_drop_en:1;\n+\tuint32_t scatter_fcs:1;\n+\tuint32_t vsd:1;\n+\tuint32_t mem_rq_type:4;\n+\tuint32_t state:4;\n+\tuint32_t flush_in_error_en:1;\n+\tuint32_t hairpin:1;\n+\tuint32_t user_index:24;\n+\tuint32_t cqn:24;\n+\tuint32_t counter_set_id:8;\n+\tuint32_t rmpn:24;\n+\tstruct mlx5_devx_wq_attr wq_attr;\n+};\n+\n /**\n * Type of object being allocated.\n */\n@@ -745,4 +791,8 @@ struct mlx5_devx_obj *mlx5_devx_cmd_mkey_create(struct ibv_context *ctx,\n int mlx5_devx_get_out_command_status(void *out);\n int mlx5_devx_cmd_qp_query_tis_td(struct ibv_qp *qp, uint32_t tis_num,\n \t\t\t\t uint32_t *tis_td);\n+struct mlx5_devx_obj *mlx5_devx_cmd_create_rq(struct ibv_context *ctx,\n+\t\t\t\tstruct mlx5_devx_create_rq_attr *rq_attr,\n+\t\t\t\tint socket);\n+\n #endif /* RTE_PMD_MLX5_H_ */\ndiff --git a/drivers/net/mlx5/mlx5_devx_cmds.c b/drivers/net/mlx5/mlx5_devx_cmds.c\nindex 3d07fcf..f68c94b 100644\n--- a/drivers/net/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/net/mlx5/mlx5_devx_cmds.c\n@@ -424,3 +424,105 @@ struct mlx5_devx_obj *\n \t*tis_td = MLX5_GET(tisc, tis_ctx, transport_domain);\n \treturn 0;\n }\n+\n+/**\n+ * Fill WQ data for DevX API command.\n+ * Utility function for use when creating DevX objects containing a WQ.\n+ *\n+ * @param[in] wq_ctx\n+ * Pointer to WQ context to fill with data.\n+ * @param [in] wq_attr\n+ * Pointer to WQ attributes structure to fill in WQ context.\n+ */\n+static void\n+devx_cmd_fill_wq_data(void *wq_ctx, struct mlx5_devx_wq_attr *wq_attr)\n+{\n+\tMLX5_SET(wq, wq_ctx, wq_type, wq_attr->wq_type);\n+\tMLX5_SET(wq, wq_ctx, wq_signature, wq_attr->wq_signature);\n+\tMLX5_SET(wq, wq_ctx, end_padding_mode, wq_attr->end_padding_mode);\n+\tMLX5_SET(wq, wq_ctx, cd_slave, wq_attr->cd_slave);\n+\tMLX5_SET(wq, wq_ctx, hds_skip_first_sge, wq_attr->hds_skip_first_sge);\n+\tMLX5_SET(wq, wq_ctx, log2_hds_buf_size, wq_attr->log2_hds_buf_size);\n+\tMLX5_SET(wq, wq_ctx, page_offset, wq_attr->page_offset);\n+\tMLX5_SET(wq, wq_ctx, lwm, wq_attr->lwm);\n+\tMLX5_SET(wq, wq_ctx, pd, wq_attr->pd);\n+\tMLX5_SET(wq, wq_ctx, uar_page, wq_attr->uar_page);\n+\tMLX5_SET64(wq, wq_ctx, dbr_addr, wq_attr->dbr_addr);\n+\tMLX5_SET(wq, wq_ctx, hw_counter, wq_attr->hw_counter);\n+\tMLX5_SET(wq, wq_ctx, sw_counter, wq_attr->sw_counter);\n+\tMLX5_SET(wq, wq_ctx, log_wq_stride, wq_attr->log_wq_stride);\n+\tMLX5_SET(wq, wq_ctx, log_wq_pg_sz, wq_attr->log_wq_pg_sz);\n+\tMLX5_SET(wq, wq_ctx, log_wq_sz, wq_attr->log_wq_sz);\n+\tMLX5_SET(wq, wq_ctx, dbr_umem_valid, wq_attr->dbr_umem_valid);\n+\tMLX5_SET(wq, wq_ctx, wq_umem_valid, wq_attr->wq_umem_valid);\n+\tMLX5_SET(wq, wq_ctx, log_hairpin_num_packets,\n+\t\t wq_attr->log_hairpin_num_packets);\n+\tMLX5_SET(wq, wq_ctx, log_hairpin_data_sz, wq_attr->log_hairpin_data_sz);\n+\tMLX5_SET(wq, wq_ctx, single_wqe_log_num_of_strides,\n+\t\t wq_attr->single_wqe_log_num_of_strides);\n+\tMLX5_SET(wq, wq_ctx, two_byte_shift_en, wq_attr->two_byte_shift_en);\n+\tMLX5_SET(wq, wq_ctx, single_stride_log_num_of_bytes,\n+\t\t wq_attr->single_stride_log_num_of_bytes);\n+\tMLX5_SET(wq, wq_ctx, dbr_umem_id, wq_attr->dbr_umem_id);\n+\tMLX5_SET(wq, wq_ctx, wq_umem_id, wq_attr->wq_umem_id);\n+\tMLX5_SET64(wq, wq_ctx, wq_umem_offset, wq_attr->wq_umem_offset);\n+}\n+\n+/**\n+ * Create RQ using DevX API.\n+ *\n+ * @param[in] ctx\n+ * ibv_context returned from mlx5dv_open_device.\n+ * @param [in] rq_attr\n+ * Pointer to create RQ attributes structure.\n+ * @param [in] socket\n+ * CPU socket ID for allocations.\n+ *\n+ * @return\n+ * The DevX object created, NULL otherwise and rte_errno is set.\n+ */\n+struct mlx5_devx_obj *\n+mlx5_devx_cmd_create_rq(struct ibv_context *ctx,\n+\t\t\tstruct mlx5_devx_create_rq_attr *rq_attr,\n+\t\t\tint socket)\n+{\n+\tuint32_t in[MLX5_ST_SZ_DW(create_rq_in)] = {0};\n+\tuint32_t out[MLX5_ST_SZ_DW(create_rq_out)] = {0};\n+\tvoid *rq_ctx, *wq_ctx;\n+\tstruct mlx5_devx_wq_attr *wq_attr;\n+\tstruct mlx5_devx_obj *rq = NULL;\n+\n+\trq = rte_calloc_socket(__func__, 1, sizeof(*rq), 0, socket);\n+\tif (!rq) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate RQ data\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn NULL;\n+\t}\n+\tMLX5_SET(create_rq_in, in, opcode, MLX5_CMD_OP_CREATE_RQ);\n+\trq_ctx = MLX5_ADDR_OF(create_rq_in, in, ctx);\n+\tMLX5_SET(rqc, rq_ctx, rlky, rq_attr->rlky);\n+\tMLX5_SET(rqc, rq_ctx, delay_drop_en, rq_attr->delay_drop_en);\n+\tMLX5_SET(rqc, rq_ctx, scatter_fcs, rq_attr->scatter_fcs);\n+\tMLX5_SET(rqc, rq_ctx, vsd, rq_attr->vsd);\n+\tMLX5_SET(rqc, rq_ctx, mem_rq_type, rq_attr->mem_rq_type);\n+\tMLX5_SET(rqc, rq_ctx, state, rq_attr->state);\n+\tMLX5_SET(rqc, rq_ctx, flush_in_error_en, rq_attr->flush_in_error_en);\n+\tMLX5_SET(rqc, rq_ctx, hairpin, rq_attr->hairpin);\n+\tMLX5_SET(rqc, rq_ctx, user_index, rq_attr->user_index);\n+\tMLX5_SET(rqc, rq_ctx, cqn, rq_attr->cqn);\n+\tMLX5_SET(rqc, rq_ctx, counter_set_id, rq_attr->counter_set_id);\n+\tMLX5_SET(rqc, rq_ctx, rmpn, rq_attr->rmpn);\n+\twq_ctx = MLX5_ADDR_OF(rqc, rq_ctx, wq);\n+\twq_attr = &rq_attr->wq_attr;\n+\tdevx_cmd_fill_wq_data(wq_ctx, wq_attr);\n+\trq->obj = mlx5_glue->devx_obj_create(ctx, in, sizeof(in),\n+\t\t\t\t\t\t out, sizeof(out));\n+\tif (!rq->obj) {\n+\t\tDRV_LOG(ERR, \"Failed to create RQ using DevX\");\n+\t\trte_errno = errno;\n+\t\trte_free(rq);\n+\t\treturn NULL;\n+\t}\n+\trq->id = MLX5_GET(create_rq_out, out, rqn);\n+\treturn rq;\n+}\ndiff --git a/drivers/net/mlx5/mlx5_prm.h b/drivers/net/mlx5/mlx5_prm.h\nindex b5de0c3..fbf00a0 100644\n--- a/drivers/net/mlx5/mlx5_prm.h\n+++ b/drivers/net/mlx5/mlx5_prm.h\n@@ -627,6 +627,7 @@ enum {\n \tMLX5_CMD_OP_QUERY_HCA_CAP = 0x100,\n \tMLX5_CMD_OP_CREATE_MKEY = 0x200,\n \tMLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,\n+\tMLX5_CMD_OP_CREATE_RQ = 0x908,\n \tMLX5_CMD_OP_QUERY_TIS = 0x915,\n \tMLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,\n \tMLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,\n@@ -1268,6 +1269,115 @@ struct mlx5_ifc_query_tis_in_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+enum {\n+\tMLX5_WQ_TYPE_LINKED_LIST = 0x0,\n+\tMLX5_WQ_TYPE_CYCLIC = 0x1,\n+\tMLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,\n+\tMLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3,\n+};\n+\n+enum {\n+\tMLX5_WQ_END_PAD_MODE_NONE = 0x0,\n+\tMLX5_WQ_END_PAD_MODE_ALIGN = 0x1,\n+};\n+\n+struct mlx5_ifc_wq_bits {\n+\tu8 wq_type[0x4];\n+\tu8 wq_signature[0x1];\n+\tu8 end_padding_mode[0x2];\n+\tu8 cd_slave[0x1];\n+\tu8 reserved_at_8[0x18];\n+\tu8 hds_skip_first_sge[0x1];\n+\tu8 log2_hds_buf_size[0x3];\n+\tu8 reserved_at_24[0x7];\n+\tu8 page_offset[0x5];\n+\tu8 lwm[0x10];\n+\tu8 reserved_at_40[0x8];\n+\tu8 pd[0x18];\n+\tu8 reserved_at_60[0x8];\n+\tu8 uar_page[0x18];\n+\tu8 dbr_addr[0x40];\n+\tu8 hw_counter[0x20];\n+\tu8 sw_counter[0x20];\n+\tu8 reserved_at_100[0xc];\n+\tu8 log_wq_stride[0x4];\n+\tu8 reserved_at_110[0x3];\n+\tu8 log_wq_pg_sz[0x5];\n+\tu8 reserved_at_118[0x3];\n+\tu8 log_wq_sz[0x5];\n+\tu8 dbr_umem_valid[0x1];\n+\tu8 wq_umem_valid[0x1];\n+\tu8 reserved_at_122[0x1];\n+\tu8 log_hairpin_num_packets[0x5];\n+\tu8 reserved_at_128[0x3];\n+\tu8 log_hairpin_data_sz[0x5];\n+\tu8 reserved_at_130[0x4];\n+\tu8 single_wqe_log_num_of_strides[0x4];\n+\tu8 two_byte_shift_en[0x1];\n+\tu8 reserved_at_139[0x4];\n+\tu8 single_stride_log_num_of_bytes[0x3];\n+\tu8 dbr_umem_id[0x20];\n+\tu8 wq_umem_id[0x20];\n+\tu8 wq_umem_offset[0x40];\n+\tu8 reserved_at_1c0[0x440];\n+};\n+\n+enum {\n+\tMLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,\n+\tMLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,\n+};\n+\n+enum {\n+\tMLX5_RQC_STATE_RST = 0x0,\n+\tMLX5_RQC_STATE_RDY = 0x1,\n+\tMLX5_RQC_STATE_ERR = 0x3,\n+};\n+\n+struct mlx5_ifc_rqc_bits {\n+\tu8 rlky[0x1];\n+\tu8 delay_drop_en[0x1];\n+\tu8 scatter_fcs[0x1];\n+\tu8 vsd[0x1];\n+\tu8 mem_rq_type[0x4];\n+\tu8 state[0x4];\n+\tu8 reserved_at_c[0x1];\n+\tu8 flush_in_error_en[0x1];\n+\tu8 hairpin[0x1];\n+\tu8 reserved_at_f[0x11];\n+\tu8 reserved_at_20[0x8];\n+\tu8 user_index[0x18];\n+\tu8 reserved_at_40[0x8];\n+\tu8 cqn[0x18];\n+\tu8 counter_set_id[0x8];\n+\tu8 reserved_at_68[0x18];\n+\tu8 reserved_at_80[0x8];\n+\tu8 rmpn[0x18];\n+\tu8 reserved_at_a0[0x8];\n+\tu8 hairpin_peer_sq[0x18];\n+\tu8 reserved_at_c0[0x10];\n+\tu8 hairpin_peer_vhca[0x10];\n+\tu8 reserved_at_e0[0xa0];\n+\tstruct mlx5_ifc_wq_bits wq; /* Not used in LRO RQ. */\n+};\n+\n+struct mlx5_ifc_create_rq_out_bits {\n+\tu8 status[0x8];\n+\tu8 reserved_at_8[0x18];\n+\tu8 syndrome[0x20];\n+\tu8 reserved_at_40[0x8];\n+\tu8 rqn[0x18];\n+\tu8 reserved_at_60[0x20];\n+};\n+\n+struct mlx5_ifc_create_rq_in_bits {\n+\tu8 opcode[0x10];\n+\tu8 uid[0x10];\n+\tu8 reserved_at_20[0x10];\n+\tu8 op_mod[0x10];\n+\tu8 reserved_at_40[0xc0];\n+\tstruct mlx5_ifc_rqc_bits ctx;\n+};\n+\n /* CQE format mask. */\n #define MLX5E_CQE_FORMAT_MASK 0xc\n \n", "prefixes": [ "09/28" ] }