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GET /api/patches/58293/?format=api
{ "id": 58293, "url": "http://patchwork.dpdk.org/api/patches/58293/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1567146501-8224-7-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1567146501-8224-7-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1567146501-8224-7-git-send-email-anoobj@marvell.com", "date": "2019-08-30T06:28:16", "name": "[06/11] crypto/octeontx2: add queue pair functions", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "1823dc9be52fc252136a9771b909dddd6210ded7", "submitter": { "id": 1205, "url": "http://patchwork.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1567146501-8224-7-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 6176, "url": "http://patchwork.dpdk.org/api/series/6176/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6176", "date": "2019-08-30T06:28:10", "name": "add OCTEON TX2 crypto PMD", "version": 1, "mbox": "http://patchwork.dpdk.org/series/6176/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/58293/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/58293/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 79CA21E8B1;\n\tFri, 30 Aug 2019 08:32:27 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n\t[67.231.156.173]) by dpdk.org (Postfix) with ESMTP id AC46B1E56D\n\tfor <dev@dpdk.org>; Fri, 30 Aug 2019 08:32:25 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n\tby mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n\tx7U6ULgD027727; Thu, 29 Aug 2019 23:32:25 -0700", "from sc-exch03.marvell.com ([199.233.58.183])\n\tby mx0b-0016f401.pphosted.com with ESMTP id 2uk4rkyg3c-1\n\t(version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); \n\tThu, 29 Aug 2019 23:32:24 -0700", "from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH03.marvell.com\n\t(10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1367.3;\n\tThu, 29 Aug 2019 23:32:23 -0700", "from maili.marvell.com (10.93.176.43) by SC-EXCH01.marvell.com\n\t(10.93.176.81) with Microsoft SMTP Server id 15.0.1367.3 via Frontend\n\tTransport; Thu, 29 Aug 2019 23:32:23 -0700", "from ajoseph83.caveonetworks.com.com (unknown [10.29.45.56])\n\tby maili.marvell.com (Postfix) with ESMTP id EF61C3F703F;\n\tThu, 29 Aug 2019 23:32:19 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n\th=from : to : cc :\n\tsubject : date : message-id : in-reply-to : references : mime-version\n\t: content-transfer-encoding : content-type; s=pfpt0818;\n\tbh=KKVYX3NEj8PtPOwjxGbbvlcbsX1HJ4+tJihhs2Ppv5g=;\n\tb=hbuXxZSPwZVL75jtlolixzL+o+s7MGA7sfB4iRRO2NLine7z9HajM1aiKeWQy0j731hA\n\txemGynxkomcbfb9xwfojuLZOYaJ5dAUTpkLQBFg2otiR1vODUwWQCZ9teXV6WhhXZgoQ\n\toQjLWwtRt/pYR6SThNi8jzDxWnWW5ghJSEXQ6eTmjc+oigfOTcv/b/2WKCMsGC9rSw7j\n\tfwQ0Su6xjB/lDQwsGvXOawpn8BpkBg2oWp/Nd/ZhWR86e43hayNbBCbqhQDG6W3WklEb\n\tJER8BpUeXoWZuPlIp+34qg2Rw03aRcjrz41l8K8sLw0eTw2yRZvba7hqJ4y0jpbxdy2b\n\tpg== ", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <akhil.goyal@nxp.com>, Pablo de Lara\n\t<pablo.de.lara.guarch@intel.com>, Thomas Monjalon <thomas@monjalon.net>", "CC": "Anoob Joseph <anoobj@marvell.com>, Jerin Jacob <jerinj@marvell.com>,\n\tNarayana Prasad <pathreya@marvell.com>,\n\tAnkur Dwivedi <adwivedi@marvell.com>,\n\tTejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Fri, 30 Aug 2019 11:58:16 +0530", "Message-ID": "<1567146501-8224-7-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "References": "<1567146501-8224-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.70,1.0.8\n\tdefinitions=2019-08-30_02:2019-08-29,2019-08-30 signatures=0", "Subject": "[dpdk-dev] [PATCH 06/11] crypto/octeontx2: add queue pair functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch adds the queue pair setup and queue pair release functions\nfor OCTEON TX2 crypto pmd.\n\nSigned-off-by: Ankur Dwivedi <adwivedi@marvell.com>\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\nSigned-off-by: Tejasree Kondoj <ktejasree@marvell.com>\n---\n .../crypto/octeontx2/otx2_cryptodev_hw_access.c | 99 +++++++\n .../crypto/octeontx2/otx2_cryptodev_hw_access.h | 63 +++++\n drivers/crypto/octeontx2/otx2_cryptodev_mbox.c | 81 ++++++\n drivers/crypto/octeontx2/otx2_cryptodev_mbox.h | 6 +\n drivers/crypto/octeontx2/otx2_cryptodev_ops.c | 306 ++++++++++++++++++++-\n 5 files changed, 552 insertions(+), 3 deletions(-)", "diff": "diff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\nindex 88b5510..20ec60e 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.c\n@@ -1,12 +1,16 @@\n /* SPDX-License-Identifier: BSD-3-Clause\n * Copyright (C) 2019 Marvell International Ltd.\n */\n+#include <rte_cryptodev.h>\n \n #include \"cpt_pmd_logs.h\"\n \n #include \"otx2_common.h\"\n #include \"otx2_cryptodev.h\"\n #include \"otx2_cryptodev_hw_access.h\"\n+#include \"otx2_cryptodev_mbox.h\"\n+#include \"otx2_cryptodev_ops.h\"\n+#include \"otx2_dev.h\"\n \n static void\n otx2_cpt_lf_err_intr_handler(void *param)\n@@ -124,3 +128,98 @@ otx2_cpt_err_intr_register(const struct rte_cryptodev *dev)\n \t */\n \treturn 0;\n }\n+\n+int\n+otx2_cpt_iq_enable(const struct rte_cryptodev *dev,\n+\t\t const struct otx2_cpt_qp *qp, uint8_t grp_mask, uint8_t pri,\n+\t\t uint32_t size_div40)\n+{\n+\tunion otx2_cpt_af_lf_ctl af_lf_ctl;\n+\tunion otx2_cpt_lf_inprog inprog;\n+\tunion otx2_cpt_lf_q_base base;\n+\tunion otx2_cpt_lf_q_size size;\n+\tunion otx2_cpt_lf_ctl lf_ctl;\n+\tint ret;\n+\n+\t/* Set engine group mask and priority */\n+\n+\tret = otx2_cpt_af_reg_read(dev, OTX2_CPT_AF_LF_CTL(qp->id),\n+\t\t\t\t &af_lf_ctl.u);\n+\tif (ret)\n+\t\treturn ret;\n+\taf_lf_ctl.s.grp = grp_mask;\n+\taf_lf_ctl.s.pri = pri ? 1 : 0;\n+\tret = otx2_cpt_af_reg_write(dev, OTX2_CPT_AF_LF_CTL(qp->id),\n+\t\t\t\t af_lf_ctl.u);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/* Set instruction queue base address */\n+\n+\tbase.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_BASE);\n+\tbase.s.fault = 0;\n+\tbase.s.stopped = 0;\n+\tbase.s.addr = qp->iq_dma_addr >> 7;\n+\totx2_write64(base.u, qp->base + OTX2_CPT_LF_Q_BASE);\n+\n+\t/* Set instruction queue size */\n+\n+\tsize.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_SIZE);\n+\tsize.s.size_div40 = size_div40;\n+\totx2_write64(size.u, qp->base + OTX2_CPT_LF_Q_SIZE);\n+\n+\t/* Enable instruction queue */\n+\n+\tlf_ctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);\n+\tlf_ctl.s.ena = 1;\n+\totx2_write64(lf_ctl.u, qp->base + OTX2_CPT_LF_CTL);\n+\n+\t/* Start instruction execution */\n+\n+\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n+\tinprog.s.eena = 1;\n+\totx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);\n+\n+\treturn 0;\n+}\n+\n+void\n+otx2_cpt_iq_disable(struct otx2_cpt_qp *qp)\n+{\n+\tunion otx2_cpt_lf_q_grp_ptr grp_ptr;\n+\tunion otx2_cpt_lf_inprog inprog;\n+\tunion otx2_cpt_lf_ctl ctl;\n+\tint cnt;\n+\n+\t/* Stop instruction execution */\n+\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n+\tinprog.s.eena = 0x0;\n+\totx2_write64(inprog.u, qp->base + OTX2_CPT_LF_INPROG);\n+\n+\t/* Disable instructions enqueuing */\n+\tctl.u = otx2_read64(qp->base + OTX2_CPT_LF_CTL);\n+\tctl.s.ena = 0;\n+\totx2_write64(ctl.u, qp->base + OTX2_CPT_LF_CTL);\n+\n+\t/* Wait for instruction queue to become empty */\n+\tcnt = 0;\n+\tdo {\n+\t\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n+\t\tif (inprog.s.grb_partial)\n+\t\t\tcnt = 0;\n+\t\telse\n+\t\t\tcnt++;\n+\t\tgrp_ptr.u = otx2_read64(qp->base + OTX2_CPT_LF_Q_GRP_PTR);\n+\t} while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr));\n+\n+\tcnt = 0;\n+\tdo {\n+\t\tinprog.u = otx2_read64(qp->base + OTX2_CPT_LF_INPROG);\n+\t\tif ((inprog.s.inflight == 0) &&\n+\t\t (inprog.s.gwb_cnt < 40) &&\n+\t\t ((inprog.s.grb_cnt == 0) || (inprog.s.grb_cnt == 40)))\n+\t\t\tcnt++;\n+\t\telse\n+\t\t\tcnt = 0;\n+\t} while (cnt < 10);\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\nindex 441494e..82718df 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_hw_access.h\n@@ -5,10 +5,24 @@\n #ifndef _OTX2_CRYPTODEV_HW_ACCESS_H_\n #define _OTX2_CRYPTODEV_HW_ACCESS_H_\n \n+#include <stdint.h>\n+\n #include <rte_cryptodev.h>\n+#include <rte_memory.h>\n+\n+#include \"cpt_common.h\"\n+#include \"cpt_hw_types.h\"\n \n #include \"otx2_dev.h\"\n \n+/* CPT instruction queue length */\n+#define OTX2_CPT_IQ_LEN\t\t\t8200\n+\n+#define OTX2_CPT_DEFAULT_CMD_QLEN\tOTX2_CPT_IQ_LEN\n+\n+/* Mask which selects all engine groups */\n+#define OTX2_CPT_ENG_GRPS_MASK\t\t0xFF\n+\n /* Register offsets */\n \n /* LMT LF registers */\n@@ -22,6 +36,7 @@\n #define OTX2_CPT_LF_MISC_INT_ENA_W1C\t0xe0ull\n #define OTX2_CPT_LF_Q_BASE\t\t0xf0ull\n #define OTX2_CPT_LF_Q_SIZE\t\t0x100ull\n+#define OTX2_CPT_LF_Q_GRP_PTR\t\t0x120ull\n #define OTX2_CPT_LF_NQ(a)\t\t(0x400ull | (uint64_t)(a) << 3)\n \n #define OTX2_CPT_AF_LF_CTL(a)\t\t(0x27000ull | (uint64_t)(a) << 3)\n@@ -30,6 +45,8 @@\n \t\t((vf)->otx2_dev.bar2 + \\\n \t\t ((RVU_BLOCK_ADDR_CPT0 << 20) | ((q_id) << 12)))\n \n+#define OTX2_CPT_QUEUE_HI_PRIO 0x1\n+\n union otx2_cpt_lf_ctl {\n \tuint64_t u;\n \tstruct {\n@@ -137,8 +154,54 @@ union otx2_cpt_af_lf_ctl {\n \t} s;\n };\n \n+union otx2_cpt_lf_q_grp_ptr {\n+\tuint64_t u;\n+\tstruct {\n+#if (RTE_BYTE_ORDER == RTE_BIG_ENDIAN) /* Word 0 - Big Endian */\n+\t\tuint64_t xq_xor : 1;\n+\t\tuint64_t reserved_47_62 : 16;\n+\t\tuint64_t nq_ptr : 15;\n+\t\tuint64_t reserved_31_15 : 17;\n+\t\tuint64_t dq_ptr : 15;\n+#else /* Word 0 - Little Endian */\n+\t\tuint64_t dq_ptr : 15;\n+\t\tuint64_t reserved_31_15 : 17;\n+\t\tuint64_t nq_ptr : 15;\n+\t\tuint64_t reserved_47_62 : 16;\n+\t\tuint64_t xq_xor : 1;\n+#endif\n+\t} s;\n+};\n+\n+struct otx2_cpt_qp {\n+\tuint32_t id;\n+\t/**< Queue pair id */\n+\tuintptr_t base;\n+\t/**< Base address where BAR is mapped */\n+\tvoid *lmtline;\n+\t/**< Address of LMTLINE */\n+\trte_iova_t lf_nq_reg;\n+\t/**< LF enqueue register address */\n+\tstruct pending_queue pend_q;\n+\t/**< Pending queue */\n+\tstruct rte_mempool *sess_mp;\n+\t/**< Session mempool */\n+\tstruct rte_mempool *sess_mp_priv;\n+\t/**< Session private data mempool */\n+\tstruct cpt_qp_meta_info meta_info;\n+\t/**< Metabuf info required to support operations on the queue pair */\n+\trte_iova_t iq_dma_addr;\n+\t/**< Instruction queue address */\n+};\n+\n void otx2_cpt_err_intr_unregister(const struct rte_cryptodev *dev);\n \n int otx2_cpt_err_intr_register(const struct rte_cryptodev *dev);\n \n+int otx2_cpt_iq_enable(const struct rte_cryptodev *dev,\n+\t\t const struct otx2_cpt_qp *qp, uint8_t grp_mask,\n+\t\t uint8_t pri, uint32_t size_div40);\n+\n+void otx2_cpt_iq_disable(struct otx2_cpt_qp *qp);\n+\n #endif /* _OTX2_CRYPTODEV_HW_ACCESS_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\nindex a11aef5..7e7b2d9 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.c\n@@ -92,3 +92,84 @@ otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev)\n \n \treturn 0;\n }\n+\n+static int\n+otx2_cpt_send_mbox_msg(struct otx2_cpt_vf *vf)\n+{\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tint ret;\n+\n+\totx2_mbox_msg_send(mbox, 0);\n+\n+\tret = otx2_mbox_wait_for_rsp(mbox, 0);\n+\tif (ret < 0) {\n+\t\tCPT_LOG_ERR(\"Could not get mailbox response\");\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n+\t\t uint64_t *val)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tstruct otx2_mbox_dev *mdev = &mbox->dev[0];\n+\tstruct cpt_rd_wr_reg_msg *msg;\n+\tint ret, off;\n+\n+\tmsg = (struct cpt_rd_wr_reg_msg *)\n+\t\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),\n+\t\t\t\t\t\tsizeof(*msg));\n+\tif (msg == NULL) {\n+\t\tCPT_LOG_ERR(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tmsg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;\n+\tmsg->hdr.sig = OTX2_MBOX_REQ_SIG;\n+\tmsg->hdr.pcifunc = vf->otx2_dev.pf_func;\n+\tmsg->is_write = 0;\n+\tmsg->reg_offset = reg;\n+\tmsg->ret_val = val;\n+\n+\tret = otx2_cpt_send_mbox_msg(vf);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\toff = mbox->rx_start +\n+\t\t\tRTE_ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN);\n+\tmsg = (struct cpt_rd_wr_reg_msg *) ((uintptr_t)mdev->mbase + off);\n+\n+\t*val = msg->val;\n+\n+\treturn 0;\n+}\n+\n+int\n+otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n+\t\t uint64_t val)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tstruct otx2_mbox *mbox = vf->otx2_dev.mbox;\n+\tstruct cpt_rd_wr_reg_msg *msg;\n+\n+\tmsg = (struct cpt_rd_wr_reg_msg *)\n+\t\t\totx2_mbox_alloc_msg_rsp(mbox, 0, sizeof(*msg),\n+\t\t\t\t\t\tsizeof(*msg));\n+\tif (msg == NULL) {\n+\t\tCPT_LOG_ERR(\"Could not allocate mailbox message\");\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tmsg->hdr.id = MBOX_MSG_CPT_RD_WR_REGISTER;\n+\tmsg->hdr.sig = OTX2_MBOX_REQ_SIG;\n+\tmsg->hdr.pcifunc = vf->otx2_dev.pf_func;\n+\tmsg->is_write = 1;\n+\tmsg->reg_offset = reg;\n+\tmsg->val = val;\n+\n+\treturn otx2_cpt_send_mbox_msg(vf);\n+}\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\nindex 0a43061..a298718 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_mbox.h\n@@ -16,4 +16,10 @@ int otx2_cpt_queues_detach(const struct rte_cryptodev *dev);\n \n int otx2_cpt_msix_offsets_get(const struct rte_cryptodev *dev);\n \n+int otx2_cpt_af_reg_read(const struct rte_cryptodev *dev, uint64_t reg,\n+\t\t\t uint64_t *val);\n+\n+int otx2_cpt_af_reg_write(const struct rte_cryptodev *dev, uint64_t reg,\n+\t\t\t uint64_t val);\n+\n #endif /* _OTX2_CRYPTODEV_MBOX_H_ */\ndiff --git a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\nindex eafb2d3..b2d459e 100644\n--- a/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n+++ b/drivers/crypto/octeontx2/otx2_cryptodev_ops.c\n@@ -2,10 +2,14 @@\n * Copyright (C) 2019 Marvell International Ltd.\n */\n \n+#include <unistd.h>\n+\n #include <rte_cryptodev_pmd.h>\n+#include <rte_errno.h>\n \n #include \"cpt_hw_types.h\"\n #include \"cpt_pmd_logs.h\"\n+#include \"cpt_pmd_ops_helper.h\"\n \n #include \"otx2_cryptodev.h\"\n #include \"otx2_cryptodev_capabilities.h\"\n@@ -14,6 +18,232 @@\n #include \"otx2_cryptodev_ops.h\"\n #include \"otx2_mbox.h\"\n \n+#define METABUF_POOL_CACHE_SIZE\t512\n+\n+/* Forward declarations */\n+\n+static int\n+otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id);\n+\n+static void\n+qp_memzone_name_get(char *name, int size, int dev_id, int qp_id)\n+{\n+\tsnprintf(name, size, \"otx2_cpt_lf_mem_%u:%u\", dev_id, qp_id);\n+}\n+\n+static int\n+otx2_cpt_metabuf_mempool_create(const struct rte_cryptodev *dev,\n+\t\t\t\tstruct otx2_cpt_qp *qp, uint8_t qp_id,\n+\t\t\t\tint nb_elements)\n+{\n+\tchar mempool_name[RTE_MEMPOOL_NAMESIZE];\n+\tint sg_mlen, lb_mlen, max_mlen, ret;\n+\tstruct cpt_qp_meta_info *meta_info;\n+\tstruct rte_mempool *pool;\n+\n+\t/* Get meta len for scatter gather mode */\n+\tsg_mlen = cpt_pmd_ops_helper_get_mlen_sg_mode();\n+\n+\t/* Extra 32B saved for future considerations */\n+\tsg_mlen += 4 * sizeof(uint64_t);\n+\n+\t/* Get meta len for linear buffer (direct) mode */\n+\tlb_mlen = cpt_pmd_ops_helper_get_mlen_direct_mode();\n+\n+\t/* Extra 32B saved for future considerations */\n+\tlb_mlen += 4 * sizeof(uint64_t);\n+\n+\t/* Check max requirement for meta buffer */\n+\tmax_mlen = RTE_MAX(lb_mlen, sg_mlen);\n+\n+\t/* Allocate mempool */\n+\n+\tsnprintf(mempool_name, RTE_MEMPOOL_NAMESIZE, \"otx2_cpt_mb_%u:%u\",\n+\t\t dev->data->dev_id, qp_id);\n+\n+\tpool = rte_mempool_create_empty(mempool_name, nb_elements, max_mlen,\n+\t\t\t\t\tMETABUF_POOL_CACHE_SIZE, 0,\n+\t\t\t\t\trte_socket_id(), 0);\n+\n+\tif (pool == NULL) {\n+\t\tCPT_LOG_ERR(\"Could not create mempool for metabuf\");\n+\t\treturn rte_errno;\n+\t}\n+\n+\tret = rte_mempool_set_ops_byname(pool, RTE_MBUF_DEFAULT_MEMPOOL_OPS,\n+\t\t\t\t\t NULL);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not set mempool ops\");\n+\t\tgoto mempool_free;\n+\t}\n+\n+\tret = rte_mempool_populate_default(pool);\n+\tif (ret <= 0) {\n+\t\tCPT_LOG_ERR(\"Could not populate metabuf pool\");\n+\t\tgoto mempool_free;\n+\t}\n+\n+\tmeta_info = &qp->meta_info;\n+\n+\tmeta_info->pool = pool;\n+\tmeta_info->lb_mlen = lb_mlen;\n+\tmeta_info->sg_mlen = sg_mlen;\n+\n+\treturn 0;\n+\n+mempool_free:\n+\trte_mempool_free(pool);\n+\treturn ret;\n+}\n+\n+static void\n+otx2_cpt_metabuf_mempool_destroy(struct otx2_cpt_qp *qp)\n+{\n+\tstruct cpt_qp_meta_info *meta_info = &qp->meta_info;\n+\n+\trte_mempool_free(meta_info->pool);\n+\n+\tmeta_info->pool = NULL;\n+\tmeta_info->lb_mlen = 0;\n+\tmeta_info->sg_mlen = 0;\n+}\n+\n+static struct otx2_cpt_qp *\n+otx2_cpt_qp_create(const struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t uint8_t group)\n+{\n+\tstruct otx2_cpt_vf *vf = dev->data->dev_private;\n+\tuint64_t pg_sz = sysconf(_SC_PAGESIZE);\n+\tconst struct rte_memzone *lf_mem;\n+\tuint32_t len, iq_len, size_div40;\n+\tchar name[RTE_MEMZONE_NAMESIZE];\n+\tuint64_t used_len, iova;\n+\tstruct otx2_cpt_qp *qp;\n+\tuint64_t lmtline;\n+\tuint8_t *va;\n+\tint ret;\n+\n+\t/* Allocate queue pair */\n+\tqp = rte_zmalloc_socket(\"OCTEON TX2 Crypto PMD Queue Pair\", sizeof(*qp),\n+\t\t\t\tOTX2_ALIGN, 0);\n+\tif (qp == NULL) {\n+\t\tCPT_LOG_ERR(\"Could not allocate queue pair\");\n+\t\treturn NULL;\n+\t}\n+\n+\tiq_len = OTX2_CPT_IQ_LEN;\n+\n+\t/*\n+\t * Queue size must be a multiple of 40 and effective queue size to\n+\t * software is (size_div40 - 1) * 40\n+\t */\n+\tsize_div40 = (iq_len + 40 - 1) / 40 + 1;\n+\n+\t/* For pending queue */\n+\tlen = iq_len * RTE_ALIGN(sizeof(struct rid), 8);\n+\n+\t/* Space for instruction group memory */\n+\tlen += size_div40 * 16;\n+\n+\t/* So that instruction queues start as pg size aligned */\n+\tlen = RTE_ALIGN(len, pg_sz);\n+\n+\t/* For instruction queues */\n+\tlen += OTX2_CPT_IQ_LEN * sizeof(union cpt_inst_s);\n+\n+\t/* Wastage after instruction queues */\n+\tlen = RTE_ALIGN(len, pg_sz);\n+\n+\tqp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,\n+\t\t\t qp_id);\n+\n+\tlf_mem = rte_memzone_reserve_aligned(name, len, vf->otx2_dev.node,\n+\t\t\tRTE_MEMZONE_SIZE_HINT_ONLY | RTE_MEMZONE_256MB,\n+\t\t\tRTE_CACHE_LINE_SIZE);\n+\tif (lf_mem == NULL) {\n+\t\tCPT_LOG_ERR(\"Could not allocate reserved memzone\");\n+\t\tgoto qp_free;\n+\t}\n+\n+\tva = lf_mem->addr;\n+\tiova = lf_mem->iova;\n+\n+\tmemset(va, 0, len);\n+\n+\tret = otx2_cpt_metabuf_mempool_create(dev, qp, qp_id, iq_len);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not create mempool for metabuf\");\n+\t\tgoto lf_mem_free;\n+\t}\n+\n+\t/* Initialize pending queue */\n+\tqp->pend_q.rid_queue = (struct rid *)va;\n+\tqp->pend_q.enq_tail = 0;\n+\tqp->pend_q.deq_head = 0;\n+\tqp->pend_q.pending_count = 0;\n+\n+\tused_len = iq_len * RTE_ALIGN(sizeof(struct rid), 8);\n+\tused_len += size_div40 * 16;\n+\tused_len = RTE_ALIGN(used_len, pg_sz);\n+\tiova += used_len;\n+\n+\tqp->iq_dma_addr = iova;\n+\tqp->id = qp_id;\n+\tqp->base = OTX2_CPT_LF_BAR2(vf, qp_id);\n+\n+\tlmtline = vf->otx2_dev.bar2 +\n+\t\t (RVU_BLOCK_ADDR_LMT << 20 | qp_id << 12) +\n+\t\t OTX2_LMT_LF_LMTLINE(0);\n+\n+\tqp->lmtline = (void *)lmtline;\n+\n+\tqp->lf_nq_reg = qp->base + OTX2_CPT_LF_NQ(0);\n+\n+\totx2_cpt_iq_disable(qp);\n+\n+\tret = otx2_cpt_iq_enable(dev, qp, group, OTX2_CPT_QUEUE_HI_PRIO,\n+\t\t\t\t size_div40);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not enable instruction queue\");\n+\t\tgoto mempool_destroy;\n+\t}\n+\n+\treturn qp;\n+\n+mempool_destroy:\n+\totx2_cpt_metabuf_mempool_destroy(qp);\n+lf_mem_free:\n+\trte_memzone_free(lf_mem);\n+qp_free:\n+\trte_free(qp);\n+\treturn NULL;\n+}\n+\n+static int\n+otx2_cpt_qp_destroy(const struct rte_cryptodev *dev, struct otx2_cpt_qp *qp)\n+{\n+\tconst struct rte_memzone *lf_mem;\n+\tchar name[RTE_MEMZONE_NAMESIZE];\n+\tint ret;\n+\n+\totx2_cpt_iq_disable(qp);\n+\n+\totx2_cpt_metabuf_mempool_destroy(qp);\n+\n+\tqp_memzone_name_get(name, RTE_MEMZONE_NAMESIZE, dev->data->dev_id,\n+\t\t\t qp->id);\n+\n+\tlf_mem = rte_memzone_lookup(name);\n+\n+\tret = rte_memzone_free(lf_mem);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\trte_free(qp);\n+\n+\treturn 0;\n+}\n+\n /* PMD ops */\n \n static int\n@@ -92,7 +322,13 @@ otx2_cpt_dev_stop(struct rte_cryptodev *dev)\n static int\n otx2_cpt_dev_close(struct rte_cryptodev *dev)\n {\n-\tint ret;\n+\tint i, ret;\n+\n+\tfor (i = 0; i < dev->data->nb_queue_pairs; i++) {\n+\t\tret = otx2_cpt_queue_pair_release(dev, i);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t}\n \n \totx2_cpt_err_intr_unregister(dev);\n \n@@ -120,6 +356,70 @@ otx2_cpt_dev_info_get(struct rte_cryptodev *dev,\n \t}\n }\n \n+static int\n+otx2_cpt_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n+\t\t\t const struct rte_cryptodev_qp_conf *conf,\n+\t\t\t int socket_id __rte_unused)\n+{\n+\tuint8_t grp_mask = OTX2_CPT_ENG_GRPS_MASK;\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct otx2_cpt_qp *qp;\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\tif (dev->data->queue_pairs[qp_id] != NULL)\n+\t\totx2_cpt_queue_pair_release(dev, qp_id);\n+\n+\tif (conf->nb_descriptors > OTX2_CPT_DEFAULT_CMD_QLEN) {\n+\t\tCPT_LOG_ERR(\"Could not setup queue pair for %u descriptors\",\n+\t\t\t conf->nb_descriptors);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpci_dev = RTE_DEV_TO_PCI(dev->device);\n+\n+\tif (pci_dev->mem_resource[2].addr == NULL) {\n+\t\tCPT_LOG_ERR(\"Invalid PCI mem address\");\n+\t\treturn -EIO;\n+\t}\n+\n+\tqp = otx2_cpt_qp_create(dev, qp_id, grp_mask);\n+\tif (qp == NULL) {\n+\t\tCPT_LOG_ERR(\"Could not create queue pair %d\", qp_id);\n+\t\treturn -ENOMEM;\n+\t}\n+\n+\tqp->sess_mp = conf->mp_session;\n+\tqp->sess_mp_priv = conf->mp_session_private;\n+\tdev->data->queue_pairs[qp_id] = qp;\n+\n+\treturn 0;\n+}\n+\n+static int\n+otx2_cpt_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n+{\n+\tstruct otx2_cpt_qp *qp = dev->data->queue_pairs[qp_id];\n+\tint ret;\n+\n+\tCPT_PMD_INIT_FUNC_TRACE();\n+\n+\tif (qp == NULL)\n+\t\treturn -EINVAL;\n+\n+\tCPT_LOG_INFO(\"Releasing queue pair %d\", qp_id);\n+\n+\tret = otx2_cpt_qp_destroy(dev, qp);\n+\tif (ret) {\n+\t\tCPT_LOG_ERR(\"Could not destroy queue pair %d\", qp_id);\n+\t\treturn ret;\n+\t}\n+\n+\tdev->data->queue_pairs[qp_id] = NULL;\n+\n+\treturn 0;\n+}\n+\n struct rte_cryptodev_ops otx2_cpt_ops = {\n \t/* Device control ops */\n \t.dev_configure = otx2_cpt_dev_config,\n@@ -130,8 +430,8 @@ struct rte_cryptodev_ops otx2_cpt_ops = {\n \n \t.stats_get = NULL,\n \t.stats_reset = NULL,\n-\t.queue_pair_setup = NULL,\n-\t.queue_pair_release = NULL,\n+\t.queue_pair_setup = otx2_cpt_queue_pair_setup,\n+\t.queue_pair_release = otx2_cpt_queue_pair_release,\n \t.queue_pair_count = NULL,\n \n \t/* Symmetric crypto ops */\n", "prefixes": [ "06/11" ] }