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{
    "id": 58865,
    "url": "http://patchwork.dpdk.org/api/patches/58865/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20190906131330.40185-4-roy.fan.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190906131330.40185-4-roy.fan.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190906131330.40185-4-roy.fan.zhang@intel.com",
    "date": "2019-09-06T13:13:23",
    "name": "[03/10] app/test: add security cpu crypto autotest",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "a5cfbe0ad16a0925fdc631f000176246e851b37a",
    "submitter": {
        "id": 304,
        "url": "http://patchwork.dpdk.org/api/people/304/?format=api",
        "name": "Fan Zhang",
        "email": "roy.fan.zhang@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20190906131330.40185-4-roy.fan.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 6303,
            "url": "http://patchwork.dpdk.org/api/series/6303/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6303",
            "date": "2019-09-06T13:13:20",
            "name": "security: add software synchronous crypto process",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/6303/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/58865/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/58865/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 420731F384;\n\tFri,  6 Sep 2019 15:13:44 +0200 (CEST)",
            "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id C1AF01F37A\n\tfor <dev@dpdk.org>; Fri,  6 Sep 2019 15:13:39 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t06 Sep 2019 06:13:39 -0700",
            "from silpixa00398673.ir.intel.com (HELO\n\tsilpixa00398673.ger.corp.intel.com) ([10.237.223.136])\n\tby fmsmga002.fm.intel.com with ESMTP; 06 Sep 2019 06:13:37 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.64,473,1559545200\"; d=\"scan'208\";a=\"213140733\"",
        "From": "Fan Zhang <roy.fan.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "konstantin.ananyev@intel.com, declan.doherty@intel.com,\n\takhil.goyal@nxp.com, Fan Zhang <roy.fan.zhang@intel.com>",
        "Date": "Fri,  6 Sep 2019 14:13:23 +0100",
        "Message-Id": "<20190906131330.40185-4-roy.fan.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.14.5",
        "In-Reply-To": "<20190906131330.40185-1-roy.fan.zhang@intel.com>",
        "References": "<20190903154046.55992-1-roy.fan.zhang@intel.com>\n\t<20190906131330.40185-1-roy.fan.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 03/10] app/test: add security cpu crypto autotest",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch adds cpu crypto unit test for AESNI_GCM PMD.\n\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\n---\n app/test/Makefile                   |   1 +\n app/test/meson.build                |   1 +\n app/test/test_security_cpu_crypto.c | 564 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 566 insertions(+)\n create mode 100644 app/test/test_security_cpu_crypto.c",
    "diff": "diff --git a/app/test/Makefile b/app/test/Makefile\nindex 26ba6fe2b..090c55746 100644\n--- a/app/test/Makefile\n+++ b/app/test/Makefile\n@@ -196,6 +196,7 @@ SRCS-$(CONFIG_RTE_LIBRTE_PMD_RING) += test_pmd_ring_perf.c\n SRCS-$(CONFIG_RTE_LIBRTE_CRYPTODEV) += test_cryptodev_blockcipher.c\n SRCS-$(CONFIG_RTE_LIBRTE_CRYPTODEV) += test_cryptodev.c\n SRCS-$(CONFIG_RTE_LIBRTE_CRYPTODEV) += test_cryptodev_asym.c\n+SRCS-$(CONFIG_RTE_LIBRTE_CRYPTODEV) += test_security_cpu_crypto.c\n \n SRCS-$(CONFIG_RTE_LIBRTE_METRICS) += test_metrics.c\n \ndiff --git a/app/test/meson.build b/app/test/meson.build\nindex ec40943bd..b7834ff21 100644\n--- a/app/test/meson.build\n+++ b/app/test/meson.build\n@@ -103,6 +103,7 @@ test_sources = files('commands.c',\n \t'test_ring_perf.c',\n \t'test_rwlock.c',\n \t'test_sched.c',\n+\t'test_security_cpu_crypto.c',\n \t'test_service_cores.c',\n \t'test_spinlock.c',\n \t'test_stack.c',\ndiff --git a/app/test/test_security_cpu_crypto.c b/app/test/test_security_cpu_crypto.c\nnew file mode 100644\nindex 000000000..d345922b2\n--- /dev/null\n+++ b/app/test/test_security_cpu_crypto.c\n@@ -0,0 +1,564 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2019 Intel Corporation\n+ */\n+\n+#include <rte_common.h>\n+#include <rte_hexdump.h>\n+#include <rte_mbuf.h>\n+#include <rte_malloc.h>\n+#include <rte_memcpy.h>\n+#include <rte_pause.h>\n+#include <rte_bus_vdev.h>\n+#include <rte_random.h>\n+\n+#include <rte_security.h>\n+\n+#include <rte_crypto.h>\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+\n+#include \"test.h\"\n+#include \"test_cryptodev.h\"\n+#include \"test_cryptodev_aead_test_vectors.h\"\n+\n+#define CPU_CRYPTO_TEST_MAX_AAD_LENGTH\t16\n+#define MAX_NB_SIGMENTS\t\t\t4\n+\n+enum buffer_assemble_option {\n+\tSGL_MAX_SEG,\n+\tSGL_ONE_SEG,\n+};\n+\n+struct cpu_crypto_test_case {\n+\tstruct {\n+\t\tuint8_t seg[MBUF_DATAPAYLOAD_SIZE];\n+\t\tuint32_t seg_len;\n+\t} seg_buf[MAX_NB_SIGMENTS];\n+\tuint8_t iv[MAXIMUM_IV_LENGTH];\n+\tuint8_t aad[CPU_CRYPTO_TEST_MAX_AAD_LENGTH];\n+\tuint8_t digest[DIGEST_BYTE_LENGTH_SHA512];\n+} __rte_cache_aligned;\n+\n+struct cpu_crypto_test_obj {\n+\tstruct iovec vec[MAX_NUM_OPS_INFLIGHT][MAX_NB_SIGMENTS];\n+\tstruct rte_security_vec sec_buf[MAX_NUM_OPS_INFLIGHT];\n+\tvoid *iv[MAX_NUM_OPS_INFLIGHT];\n+\tvoid *digest[MAX_NUM_OPS_INFLIGHT];\n+\tvoid *aad[MAX_NUM_OPS_INFLIGHT];\n+\tint status[MAX_NUM_OPS_INFLIGHT];\n+};\n+\n+struct cpu_crypto_testsuite_params {\n+\tstruct rte_mempool *buf_pool;\n+\tstruct rte_mempool *session_priv_mpool;\n+\tstruct rte_security_ctx *ctx;\n+};\n+\n+struct cpu_crypto_unittest_params {\n+\tstruct rte_security_session *sess;\n+\tvoid *test_datas[MAX_NUM_OPS_INFLIGHT];\n+\tstruct cpu_crypto_test_obj test_obj;\n+\tuint32_t nb_bufs;\n+};\n+\n+static struct cpu_crypto_testsuite_params testsuite_params = { NULL };\n+static struct cpu_crypto_unittest_params unittest_params;\n+\n+static int gbl_driver_id;\n+\n+static int\n+testsuite_setup(void)\n+{\n+\tstruct cpu_crypto_testsuite_params *ts_params = &testsuite_params;\n+\tstruct rte_cryptodev_info info;\n+\tuint32_t i;\n+\tuint32_t nb_devs;\n+\tuint32_t sess_sz;\n+\tint ret;\n+\n+\tmemset(ts_params, 0, sizeof(*ts_params));\n+\n+\tts_params->buf_pool = rte_mempool_lookup(\"CPU_CRYPTO_MBUFPOOL\");\n+\tif (ts_params->buf_pool == NULL) {\n+\t\t/* Not already created so create */\n+\t\tts_params->buf_pool = rte_pktmbuf_pool_create(\n+\t\t\t\t\"CRYPTO_MBUFPOOL\",\n+\t\t\t\tNUM_MBUFS, MBUF_CACHE_SIZE, 0,\n+\t\t\t\tsizeof(struct cpu_crypto_test_case),\n+\t\t\t\trte_socket_id());\n+\t\tif (ts_params->buf_pool == NULL) {\n+\t\t\tRTE_LOG(ERR, USER1, \"Can't create CRYPTO_MBUFPOOL\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\t}\n+\n+\t/* Create an AESNI MB device if required */\n+\tif (gbl_driver_id == rte_cryptodev_driver_id_get(\n+\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD))) {\n+\t\tnb_devs = rte_cryptodev_device_count_by_driver(\n+\t\t\t\trte_cryptodev_driver_id_get(\n+\t\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD)));\n+\t\tif (nb_devs < 1) {\n+\t\t\tret = rte_vdev_init(\n+\t\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD), NULL);\n+\n+\t\t\tTEST_ASSERT(ret == 0,\n+\t\t\t\t\"Failed to create instance of\"\n+\t\t\t\t\" pmd : %s\",\n+\t\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD));\n+\t\t}\n+\t}\n+\n+\t/* Create an AESNI GCM device if required */\n+\tif (gbl_driver_id == rte_cryptodev_driver_id_get(\n+\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD))) {\n+\t\tnb_devs = rte_cryptodev_device_count_by_driver(\n+\t\t\t\trte_cryptodev_driver_id_get(\n+\t\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD)));\n+\t\tif (nb_devs < 1) {\n+\t\t\tTEST_ASSERT_SUCCESS(rte_vdev_init(\n+\t\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD), NULL),\n+\t\t\t\t\"Failed to create instance of\"\n+\t\t\t\t\" pmd : %s\",\n+\t\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));\n+\t\t}\n+\t}\n+\n+\tnb_devs = rte_cryptodev_count();\n+\tif (nb_devs < 1) {\n+\t\tRTE_LOG(ERR, USER1, \"No crypto devices found?\\n\");\n+\t\treturn TEST_FAILED;\n+\t}\n+\n+\t/* Get security context */\n+\tfor (i = 0; i < nb_devs; i++) {\n+\t\trte_cryptodev_info_get(i, &info);\n+\t\tif (info.driver_id != gbl_driver_id)\n+\t\t\tcontinue;\n+\n+\t\tts_params->ctx = rte_cryptodev_get_sec_ctx(i);\n+\t\tif (!ts_params->ctx) {\n+\t\t\tRTE_LOG(ERR, USER1, \"Rte_security is not supported\\n\");\n+\t\t\treturn TEST_FAILED;\n+\t\t}\n+\t}\n+\n+\tsess_sz = rte_security_session_get_size(ts_params->ctx);\n+\tts_params->session_priv_mpool = rte_mempool_create(\n+\t\t\t\"cpu_crypto_test_sess_mp\", 2, sess_sz, 0, 0,\n+\t\t\tNULL, NULL, NULL, NULL,\n+\t\t\tSOCKET_ID_ANY, 0);\n+\tif (!ts_params->session_priv_mpool) {\n+\t\tRTE_LOG(ERR, USER1, \"Not enough memory\\n\");\n+\t\treturn TEST_FAILED;\n+\t}\n+\n+\treturn TEST_SUCCESS;\n+}\n+\n+static void\n+testsuite_teardown(void)\n+{\n+\tstruct cpu_crypto_testsuite_params *ts_params = &testsuite_params;\n+\n+\tif (ts_params->buf_pool)\n+\t\trte_mempool_free(ts_params->buf_pool);\n+\n+\tif (ts_params->session_priv_mpool)\n+\t\trte_mempool_free(ts_params->session_priv_mpool);\n+}\n+\n+static int\n+ut_setup(void)\n+{\n+\tstruct cpu_crypto_unittest_params *ut_params = &unittest_params;\n+\n+\tmemset(ut_params, 0, sizeof(*ut_params));\n+\treturn TEST_SUCCESS;\n+}\n+\n+static void\n+ut_teardown(void)\n+{\n+\tstruct cpu_crypto_testsuite_params *ts_params = &testsuite_params;\n+\tstruct cpu_crypto_unittest_params *ut_params = &unittest_params;\n+\n+\tif (ut_params->sess)\n+\t\trte_security_session_destroy(ts_params->ctx, ut_params->sess);\n+\n+\tif (ut_params->nb_bufs) {\n+\t\tuint32_t i;\n+\n+\t\tfor (i = 0; i < ut_params->nb_bufs; i++)\n+\t\t\tmemset(ut_params->test_datas[i], 0,\n+\t\t\t\tsizeof(struct cpu_crypto_test_case));\n+\n+\t\trte_mempool_put_bulk(ts_params->buf_pool, ut_params->test_datas,\n+\t\t\t\tut_params->nb_bufs);\n+\t}\n+}\n+\n+static int\n+allocate_buf(uint32_t n)\n+{\n+\tstruct cpu_crypto_testsuite_params *ts_params = &testsuite_params;\n+\tstruct cpu_crypto_unittest_params *ut_params = &unittest_params;\n+\tint ret;\n+\n+\tret = rte_mempool_get_bulk(ts_params->buf_pool, ut_params->test_datas,\n+\t\t\tn);\n+\n+\tif (ret == 0)\n+\t\tut_params->nb_bufs = n;\n+\n+\treturn ret;\n+}\n+\n+static int\n+check_status(struct cpu_crypto_test_obj *obj, uint32_t n)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < n; i++)\n+\t\tif (obj->status[i] < 0)\n+\t\t\treturn -1;\n+\n+\treturn 0;\n+}\n+\n+static struct rte_security_session *\n+create_aead_session(struct rte_security_ctx *ctx,\n+\t\tstruct rte_mempool *sess_mp,\n+\t\tenum rte_crypto_aead_operation op,\n+\t\tconst struct aead_test_data *test_data,\n+\t\tuint32_t is_unit_test)\n+{\n+\tstruct rte_security_session_conf sess_conf = {0};\n+\tstruct rte_crypto_sym_xform xform = {0};\n+\n+\tif (is_unit_test)\n+\t\tdebug_hexdump(stdout, \"key:\", test_data->key.data,\n+\t\t\t\ttest_data->key.len);\n+\n+\t/* Setup AEAD Parameters */\n+\txform.type = RTE_CRYPTO_SYM_XFORM_AEAD;\n+\txform.next = NULL;\n+\txform.aead.algo = test_data->algo;\n+\txform.aead.op = op;\n+\txform.aead.key.data = test_data->key.data;\n+\txform.aead.key.length = test_data->key.len;\n+\txform.aead.iv.offset = 0;\n+\txform.aead.iv.length = test_data->iv.len;\n+\txform.aead.digest_length = test_data->auth_tag.len;\n+\txform.aead.aad_length = test_data->aad.len;\n+\n+\tsess_conf.action_type = RTE_SECURITY_ACTION_TYPE_CPU_CRYPTO;\n+\tsess_conf.crypto_xform = &xform;\n+\n+\treturn rte_security_session_create(ctx, &sess_conf, sess_mp);\n+}\n+\n+static inline int\n+assemble_aead_buf(struct cpu_crypto_test_case *data,\n+\t\tstruct cpu_crypto_test_obj *obj,\n+\t\tuint32_t obj_idx,\n+\t\tenum rte_crypto_aead_operation op,\n+\t\tconst struct aead_test_data *test_data,\n+\t\tenum buffer_assemble_option sgl_option,\n+\t\tuint32_t is_unit_test)\n+{\n+\tconst uint8_t *src;\n+\tuint32_t src_len;\n+\tuint32_t seg_idx;\n+\tuint32_t bytes_per_seg;\n+\tuint32_t left;\n+\n+\tif (op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {\n+\t\tsrc = test_data->plaintext.data;\n+\t\tsrc_len = test_data->plaintext.len;\n+\t\tif (is_unit_test)\n+\t\t\tdebug_hexdump(stdout, \"plaintext:\", src, src_len);\n+\t} else {\n+\t\tsrc = test_data->ciphertext.data;\n+\t\tsrc_len = test_data->ciphertext.len;\n+\t\tmemcpy(data->digest, test_data->auth_tag.data,\n+\t\t\t\ttest_data->auth_tag.len);\n+\t\tif (is_unit_test) {\n+\t\t\tdebug_hexdump(stdout, \"ciphertext:\", src, src_len);\n+\t\t\tdebug_hexdump(stdout, \"digest:\",\n+\t\t\t\t\ttest_data->auth_tag.data,\n+\t\t\t\t\ttest_data->auth_tag.len);\n+\t\t}\n+\t}\n+\n+\tif (src_len > MBUF_DATAPAYLOAD_SIZE)\n+\t\treturn -ENOMEM;\n+\n+\tswitch (sgl_option) {\n+\tcase SGL_MAX_SEG:\n+\t\tseg_idx = 0;\n+\t\tbytes_per_seg = src_len / MAX_NB_SIGMENTS + 1;\n+\t\tleft = src_len;\n+\n+\t\tif (bytes_per_seg > (MBUF_DATAPAYLOAD_SIZE / MAX_NB_SIGMENTS))\n+\t\t\treturn -ENOMEM;\n+\n+\t\twhile (left) {\n+\t\t\tuint32_t cp_len = RTE_MIN(left, bytes_per_seg);\n+\t\t\tmemcpy(data->seg_buf[seg_idx].seg, src, cp_len);\n+\t\t\tdata->seg_buf[seg_idx].seg_len = cp_len;\n+\t\t\tobj->vec[obj_idx][seg_idx].iov_base =\n+\t\t\t\t\t(void *)data->seg_buf[seg_idx].seg;\n+\t\t\tobj->vec[obj_idx][seg_idx].iov_len = cp_len;\n+\t\t\tsrc += cp_len;\n+\t\t\tleft -= cp_len;\n+\t\t\tseg_idx++;\n+\t\t}\n+\n+\t\tif (left)\n+\t\t\treturn -ENOMEM;\n+\n+\t\tobj->sec_buf[obj_idx].vec = obj->vec[obj_idx];\n+\t\tobj->sec_buf[obj_idx].num = seg_idx;\n+\n+\t\tbreak;\n+\tcase SGL_ONE_SEG:\n+\t\tmemcpy(data->seg_buf[0].seg, src, src_len);\n+\t\tdata->seg_buf[0].seg_len = src_len;\n+\t\tobj->vec[obj_idx][0].iov_base =\n+\t\t\t\t(void *)data->seg_buf[0].seg;\n+\t\tobj->vec[obj_idx][0].iov_len = src_len;\n+\n+\t\tobj->sec_buf[obj_idx].vec = obj->vec[obj_idx];\n+\t\tobj->sec_buf[obj_idx].num = 1;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn -1;\n+\t}\n+\n+\tif (test_data->algo == RTE_CRYPTO_AEAD_AES_CCM) {\n+\t\tmemcpy(data->iv + 1, test_data->iv.data, test_data->iv.len);\n+\t\tmemcpy(data->aad + 18, test_data->aad.data, test_data->aad.len);\n+\t} else {\n+\t\tmemcpy(data->iv, test_data->iv.data, test_data->iv.len);\n+\t\tmemcpy(data->aad, test_data->aad.data, test_data->aad.len);\n+\t}\n+\n+\tif (is_unit_test) {\n+\t\tdebug_hexdump(stdout, \"iv:\", test_data->iv.data,\n+\t\t\t\ttest_data->iv.len);\n+\t\tdebug_hexdump(stdout, \"aad:\", test_data->aad.data,\n+\t\t\t\ttest_data->aad.len);\n+\t}\n+\n+\tobj->iv[obj_idx] = (void *)data->iv;\n+\tobj->digest[obj_idx] = (void *)data->digest;\n+\tobj->aad[obj_idx] = (void *)data->aad;\n+\n+\treturn 0;\n+}\n+\n+#define CPU_CRYPTO_ERR_EXP_CT\t\"expect ciphertext:\"\n+#define CPU_CRYPTO_ERR_GEN_CT\t\"gen ciphertext:\"\n+#define CPU_CRYPTO_ERR_EXP_PT\t\"expect plaintext:\"\n+#define CPU_CRYPTO_ERR_GEN_PT\t\"gen plaintext:\"\n+\n+static int\n+check_aead_result(struct cpu_crypto_test_case *tcase,\n+\t\tenum rte_crypto_aead_operation op,\n+\t\tconst struct aead_test_data *tdata)\n+{\n+\tconst char *err_msg1, *err_msg2;\n+\tconst uint8_t *src_pt_ct;\n+\tconst uint8_t *tmp_src;\n+\tuint32_t src_len;\n+\tuint32_t left;\n+\tuint32_t i = 0;\n+\tint ret;\n+\n+\tif (op == RTE_CRYPTO_AEAD_OP_ENCRYPT) {\n+\t\terr_msg1 = CPU_CRYPTO_ERR_EXP_CT;\n+\t\terr_msg2 = CPU_CRYPTO_ERR_GEN_CT;\n+\n+\t\tsrc_pt_ct = tdata->ciphertext.data;\n+\t\tsrc_len = tdata->ciphertext.len;\n+\n+\t\tret = memcmp(tcase->digest, tdata->auth_tag.data,\n+\t\t\t\ttdata->auth_tag.len);\n+\t\tif (ret != 0) {\n+\t\t\tdebug_hexdump(stdout, \"expect digest:\",\n+\t\t\t\t\ttdata->auth_tag.data,\n+\t\t\t\t\ttdata->auth_tag.len);\n+\t\t\tdebug_hexdump(stdout, \"gen digest:\",\n+\t\t\t\t\ttcase->digest,\n+\t\t\t\t\ttdata->auth_tag.len);\n+\t\t\treturn -1;\n+\t\t}\n+\t} else {\n+\t\tsrc_pt_ct = tdata->plaintext.data;\n+\t\tsrc_len = tdata->plaintext.len;\n+\t\terr_msg1 = CPU_CRYPTO_ERR_EXP_PT;\n+\t\terr_msg2 = CPU_CRYPTO_ERR_GEN_PT;\n+\t}\n+\n+\ttmp_src = src_pt_ct;\n+\tleft = src_len;\n+\n+\twhile (left && i < MAX_NB_SIGMENTS) {\n+\t\tret = memcmp(tcase->seg_buf[i].seg, tmp_src,\n+\t\t\t\ttcase->seg_buf[i].seg_len);\n+\t\tif (ret != 0)\n+\t\t\tgoto sgl_err_dump;\n+\t\ttmp_src += tcase->seg_buf[i].seg_len;\n+\t\tleft -= tcase->seg_buf[i].seg_len;\n+\t\ti++;\n+\t}\n+\n+\tif (left) {\n+\t\tret = -ENOMEM;\n+\t\tgoto sgl_err_dump;\n+\t}\n+\n+\treturn 0;\n+\n+sgl_err_dump:\n+\tleft = src_len;\n+\ti = 0;\n+\n+\tdebug_hexdump(stdout, err_msg1,\n+\t\t\ttdata->ciphertext.data,\n+\t\t\ttdata->ciphertext.len);\n+\n+\twhile (left && i < MAX_NB_SIGMENTS) {\n+\t\tdebug_hexdump(stdout, err_msg2,\n+\t\t\t\ttcase->seg_buf[i].seg,\n+\t\t\t\ttcase->seg_buf[i].seg_len);\n+\t\tleft -= tcase->seg_buf[i].seg_len;\n+\t\ti++;\n+\t}\n+\treturn ret;\n+}\n+\n+static inline void\n+run_test(struct rte_security_ctx *ctx, struct rte_security_session *sess,\n+\t\tstruct cpu_crypto_test_obj *obj, uint32_t n)\n+{\n+\trte_security_process_cpu_crypto_bulk(ctx, sess, obj->sec_buf,\n+\t\t\tobj->iv, obj->aad, obj->digest, obj->status, n);\n+}\n+\n+static int\n+cpu_crypto_test_aead(const struct aead_test_data *tdata,\n+\t\tenum rte_crypto_aead_operation dir,\n+\t\tenum buffer_assemble_option sgl_option)\n+{\n+\tstruct cpu_crypto_testsuite_params *ts_params = &testsuite_params;\n+\tstruct cpu_crypto_unittest_params *ut_params = &unittest_params;\n+\tstruct cpu_crypto_test_obj *obj = &ut_params->test_obj;\n+\tstruct cpu_crypto_test_case *tcase;\n+\tint ret;\n+\n+\tut_params->sess = create_aead_session(ts_params->ctx,\n+\t\t\tts_params->session_priv_mpool,\n+\t\t\tdir,\n+\t\t\ttdata,\n+\t\t\t1);\n+\tif (!ut_params->sess)\n+\t\treturn -1;\n+\n+\tret = allocate_buf(1);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\ttcase = ut_params->test_datas[0];\n+\tret = assemble_aead_buf(tcase, obj, 0, dir, tdata, sgl_option, 1);\n+\tif (ret < 0) {\n+\t\tprintf(\"Test is not supported by the driver\\n\");\n+\t\treturn ret;\n+\t}\n+\n+\trun_test(ts_params->ctx, ut_params->sess, obj, 1);\n+\n+\tret = check_status(obj, 1);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tret = check_aead_result(tcase, dir, tdata);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+/* test-vector/sgl-option */\n+#define all_gcm_unit_test_cases(type)\t\t\\\n+\tTEST_EXPAND(gcm_test_case_1, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_2, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_3, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_4, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_5, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_6, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_7, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_8, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_192_1, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_192_2, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_192_3, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_192_4, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_192_5, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_192_6, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_192_7, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_256_1, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_256_2, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_256_3, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_256_4, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_256_5, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_256_6, type)\t\\\n+\tTEST_EXPAND(gcm_test_case_256_7, type)\n+\n+\n+#define TEST_EXPAND(t, o)\t\t\t\t\t\t\\\n+static int\t\t\t\t\t\t\t\t\\\n+cpu_crypto_aead_enc_test_##t##_##o(void)\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\treturn cpu_crypto_test_aead(&t, RTE_CRYPTO_AEAD_OP_ENCRYPT, o);\t\\\n+}\t\t\t\t\t\t\t\t\t\\\n+static int\t\t\t\t\t\t\t\t\\\n+cpu_crypto_aead_dec_test_##t##_##o(void)\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\treturn cpu_crypto_test_aead(&t, RTE_CRYPTO_AEAD_OP_DECRYPT, o);\t\\\n+}\t\t\t\t\t\t\t\t\t\\\n+\n+all_gcm_unit_test_cases(SGL_ONE_SEG)\n+all_gcm_unit_test_cases(SGL_MAX_SEG)\n+#undef TEST_EXPAND\n+\n+static struct unit_test_suite security_cpu_crypto_aesgcm_testsuite  = {\n+\t.suite_name = \"Security CPU Crypto AESNI-GCM Unit Test Suite\",\n+\t.setup = testsuite_setup,\n+\t.teardown = testsuite_teardown,\n+\t.unit_test_cases = {\n+#define TEST_EXPAND(t, o)\t\t\t\t\t\t\\\n+\tTEST_CASE_ST(ut_setup, ut_teardown,\t\t\t\t\\\n+\t\t\tcpu_crypto_aead_enc_test_##t##_##o),\t\t\\\n+\tTEST_CASE_ST(ut_setup, ut_teardown,\t\t\t\t\\\n+\t\t\tcpu_crypto_aead_dec_test_##t##_##o),\t\t\\\n+\n+\tall_gcm_unit_test_cases(SGL_ONE_SEG)\n+\tall_gcm_unit_test_cases(SGL_MAX_SEG)\n+#undef TEST_EXPAND\n+\n+\tTEST_CASES_END() /**< NULL terminate unit test array */\n+\t},\n+};\n+\n+static int\n+test_security_cpu_crypto_aesni_gcm(void)\n+{\n+\tgbl_driver_id =\trte_cryptodev_driver_id_get(\n+\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));\n+\n+\treturn unit_test_suite_runner(&security_cpu_crypto_aesgcm_testsuite);\n+}\n+\n+REGISTER_TEST_COMMAND(security_aesni_gcm_autotest,\n+\t\ttest_security_cpu_crypto_aesni_gcm);\n",
    "prefixes": [
        "03/10"
    ]
}