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{
    "id": 58866,
    "url": "http://patchwork.dpdk.org/api/patches/58866/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20190906131330.40185-5-roy.fan.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20190906131330.40185-5-roy.fan.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20190906131330.40185-5-roy.fan.zhang@intel.com",
    "date": "2019-09-06T13:13:24",
    "name": "[04/10] app/test: add security cpu crypto perftest",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "83dc121325d313339d616e3f1fae58d87da428f5",
    "submitter": {
        "id": 304,
        "url": "http://patchwork.dpdk.org/api/people/304/?format=api",
        "name": "Fan Zhang",
        "email": "roy.fan.zhang@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20190906131330.40185-5-roy.fan.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 6303,
            "url": "http://patchwork.dpdk.org/api/series/6303/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6303",
            "date": "2019-09-06T13:13:20",
            "name": "security: add software synchronous crypto process",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/6303/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/58866/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/58866/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@dpdk.org",
        "Delivered-To": "patchwork@dpdk.org",
        "Received": [
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 0B16C1F39B;\n\tFri,  6 Sep 2019 15:13:47 +0200 (CEST)",
            "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id 4B5091F384\n\tfor <dev@dpdk.org>; Fri,  6 Sep 2019 15:13:41 +0200 (CEST)",
            "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t06 Sep 2019 06:13:40 -0700",
            "from silpixa00398673.ir.intel.com (HELO\n\tsilpixa00398673.ger.corp.intel.com) ([10.237.223.136])\n\tby fmsmga002.fm.intel.com with ESMTP; 06 Sep 2019 06:13:39 -0700"
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.64,473,1559545200\"; d=\"scan'208\";a=\"213140740\"",
        "From": "Fan Zhang <roy.fan.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "konstantin.ananyev@intel.com, declan.doherty@intel.com,\n\takhil.goyal@nxp.com, Fan Zhang <roy.fan.zhang@intel.com>",
        "Date": "Fri,  6 Sep 2019 14:13:24 +0100",
        "Message-Id": "<20190906131330.40185-5-roy.fan.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.14.5",
        "In-Reply-To": "<20190906131330.40185-1-roy.fan.zhang@intel.com>",
        "References": "<20190903154046.55992-1-roy.fan.zhang@intel.com>\n\t<20190906131330.40185-1-roy.fan.zhang@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 04/10] app/test: add security cpu crypto perftest",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Since crypto perf application does not support rte_security, this patch\nadds a simple GCM CPU crypto performance test to crypto unittest\napplication. The test includes different key and data sizes test with\nsingle buffer and SGL buffer test items and will display the throughput\nas well as cycle count performance information.\n\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\n---\n app/test/test_security_cpu_crypto.c | 201 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 201 insertions(+)",
    "diff": "diff --git a/app/test/test_security_cpu_crypto.c b/app/test/test_security_cpu_crypto.c\nindex d345922b2..ca9a8dae6 100644\n--- a/app/test/test_security_cpu_crypto.c\n+++ b/app/test/test_security_cpu_crypto.c\n@@ -23,6 +23,7 @@\n \n #define CPU_CRYPTO_TEST_MAX_AAD_LENGTH\t16\n #define MAX_NB_SIGMENTS\t\t\t4\n+#define CACHE_WARM_ITER\t\t\t2048\n \n enum buffer_assemble_option {\n \tSGL_MAX_SEG,\n@@ -560,5 +561,205 @@ test_security_cpu_crypto_aesni_gcm(void)\n \treturn unit_test_suite_runner(&security_cpu_crypto_aesgcm_testsuite);\n }\n \n+\n+static inline void\n+gen_rand(uint8_t *data, uint32_t len)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < len; i++)\n+\t\tdata[i] = (uint8_t)rte_rand();\n+}\n+\n+static inline void\n+switch_aead_enc_to_dec(struct aead_test_data *tdata,\n+\t\tstruct cpu_crypto_test_case *tcase,\n+\t\tenum buffer_assemble_option sgl_option)\n+{\n+\tuint32_t i;\n+\tuint8_t *dst = tdata->ciphertext.data;\n+\n+\tswitch (sgl_option) {\n+\tcase SGL_ONE_SEG:\n+\t\tmemcpy(dst, tcase->seg_buf[0].seg, tcase->seg_buf[0].seg_len);\n+\t\ttdata->ciphertext.len = tcase->seg_buf[0].seg_len;\n+\t\tbreak;\n+\tcase SGL_MAX_SEG:\n+\t\ttdata->ciphertext.len = 0;\n+\t\tfor (i = 0; i < MAX_NB_SIGMENTS; i++) {\n+\t\t\tmemcpy(dst, tcase->seg_buf[i].seg,\n+\t\t\t\t\ttcase->seg_buf[i].seg_len);\n+\t\t\ttdata->ciphertext.len += tcase->seg_buf[i].seg_len;\n+\t\t}\n+\t\tbreak;\n+\t}\n+\n+\tmemcpy(tdata->auth_tag.data, tcase->digest, tdata->auth_tag.len);\n+}\n+\n+static int\n+cpu_crypto_test_aead_perf(enum buffer_assemble_option sgl_option,\n+\t\tuint32_t key_sz)\n+{\n+\tstruct aead_test_data tdata = {0};\n+\tstruct cpu_crypto_testsuite_params *ts_params = &testsuite_params;\n+\tstruct cpu_crypto_unittest_params *ut_params = &unittest_params;\n+\tstruct cpu_crypto_test_obj *obj = &ut_params->test_obj;\n+\tstruct cpu_crypto_test_case *tcase;\n+\tuint64_t hz = rte_get_tsc_hz(), time_start, time_now;\n+\tdouble rate, cycles_per_buf;\n+\tuint32_t test_data_szs[] = {64, 128, 256, 512, 1024, 2048};\n+\tuint32_t i, j;\n+\tuint8_t aad[16];\n+\tint ret;\n+\n+\ttdata.key.len = key_sz;\n+\tgen_rand(tdata.key.data, tdata.key.len);\n+\ttdata.algo = RTE_CRYPTO_AEAD_AES_GCM;\n+\ttdata.aad.data = aad;\n+\n+\tut_params->sess = create_aead_session(ts_params->ctx,\n+\t\t\tts_params->session_priv_mpool,\n+\t\t\tRTE_CRYPTO_AEAD_OP_DECRYPT,\n+\t\t\t&tdata,\n+\t\t\t0);\n+\tif (!ut_params->sess)\n+\t\treturn -1;\n+\n+\tret = allocate_buf(MAX_NUM_OPS_INFLIGHT);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < RTE_DIM(test_data_szs); i++) {\n+\t\tfor (j = 0; j < MAX_NUM_OPS_INFLIGHT; j++) {\n+\t\t\ttdata.plaintext.len = test_data_szs[i];\n+\t\t\tgen_rand(tdata.plaintext.data,\n+\t\t\t\t\ttdata.plaintext.len);\n+\n+\t\t\ttdata.aad.len = 12;\n+\t\t\tgen_rand(tdata.aad.data, tdata.aad.len);\n+\n+\t\t\ttdata.auth_tag.len = 16;\n+\n+\t\t\ttdata.iv.len = 16;\n+\t\t\tgen_rand(tdata.iv.data, tdata.iv.len);\n+\n+\t\t\ttcase = ut_params->test_datas[j];\n+\t\t\tret = assemble_aead_buf(tcase, obj, j,\n+\t\t\t\t\tRTE_CRYPTO_AEAD_OP_ENCRYPT,\n+\t\t\t\t\t&tdata, sgl_option, 0);\n+\t\t\tif (ret < 0) {\n+\t\t\t\tprintf(\"Test is not supported by the driver\\n\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* warm up cache */\n+\t\tfor (j = 0; j < CACHE_WARM_ITER; j++)\n+\t\t\trun_test(ts_params->ctx, ut_params->sess, obj,\n+\t\t\t\t\tMAX_NUM_OPS_INFLIGHT);\n+\n+\t\ttime_start = rte_rdtsc();\n+\n+\t\trun_test(ts_params->ctx, ut_params->sess, obj,\n+\t\t\t\tMAX_NUM_OPS_INFLIGHT);\n+\n+\t\ttime_now = rte_rdtsc();\n+\n+\t\trate = time_now - time_start;\n+\t\tcycles_per_buf = rate / MAX_NUM_OPS_INFLIGHT;\n+\n+\t\trate = ((hz / cycles_per_buf)) / 1000000;\n+\n+\t\tprintf(\"AES-GCM-%u(%4uB) Enc %03.3fMpps (%03.3fGbps) \",\n+\t\t\t\tkey_sz * 8, test_data_szs[i], rate,\n+\t\t\t\trate  * test_data_szs[i] * 8 / 1000);\n+\t\tprintf(\"cycles per buf %03.3f per byte %03.3f\\n\",\n+\t\t\t\tcycles_per_buf,\n+\t\t\t\tcycles_per_buf / test_data_szs[i]);\n+\n+\t\tfor (j = 0; j < MAX_NUM_OPS_INFLIGHT; j++) {\n+\t\t\ttcase = ut_params->test_datas[j];\n+\n+\t\t\tswitch_aead_enc_to_dec(&tdata, tcase, sgl_option);\n+\t\t\tret = assemble_aead_buf(tcase, obj, j,\n+\t\t\t\t\tRTE_CRYPTO_AEAD_OP_DECRYPT,\n+\t\t\t\t\t&tdata, sgl_option, 0);\n+\t\t\tif (ret < 0) {\n+\t\t\t\tprintf(\"Test is not supported by the driver\\n\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\ttime_start = rte_get_timer_cycles();\n+\n+\t\trun_test(ts_params->ctx, ut_params->sess, obj,\n+\t\t\t\tMAX_NUM_OPS_INFLIGHT);\n+\n+\t\ttime_now = rte_get_timer_cycles();\n+\n+\t\trate = time_now - time_start;\n+\t\tcycles_per_buf = rate / MAX_NUM_OPS_INFLIGHT;\n+\n+\t\trate = ((hz / cycles_per_buf)) / 1000000;\n+\n+\t\tprintf(\"AES-GCM-%u(%4uB) Dec %03.3fMpps (%03.3fGbps) \",\n+\t\t\t\tkey_sz * 8, test_data_szs[i], rate,\n+\t\t\t\trate  * test_data_szs[i] * 8 / 1000);\n+\t\tprintf(\"cycles per buf %03.3f per byte %03.3f\\n\",\n+\t\t\t\tcycles_per_buf,\n+\t\t\t\tcycles_per_buf / test_data_szs[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* test-perfix/key-size/sgl-type */\n+#define all_gcm_perf_test_cases(type)\t\t\t\t\t\\\n+\tTEST_EXPAND(_128, 16, type)\t\t\t\t\t\\\n+\tTEST_EXPAND(_192, 24, type)\t\t\t\t\t\\\n+\tTEST_EXPAND(_256, 32, type)\n+\n+#define TEST_EXPAND(a, b, c)\t\t\t\t\t\t\\\n+static int\t\t\t\t\t\t\t\t\\\n+cpu_crypto_gcm_perf##a##_##c(void)\t\t\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\treturn cpu_crypto_test_aead_perf(c, b);\t\t\t\t\\\n+}\t\t\t\t\t\t\t\t\t\\\n+\n+all_gcm_perf_test_cases(SGL_ONE_SEG)\n+all_gcm_perf_test_cases(SGL_MAX_SEG)\n+#undef TEST_EXPAND\n+\n+static struct unit_test_suite security_cpu_crypto_aesgcm_perf_testsuite  = {\n+\t\t.suite_name = \"Security CPU Crypto AESNI-GCM Perf Test Suite\",\n+\t\t.setup = testsuite_setup,\n+\t\t.teardown = testsuite_teardown,\n+\t\t.unit_test_cases = {\n+#define TEST_EXPAND(a, b, c)\t\t\t\t\t\t\\\n+\t\tTEST_CASE_ST(ut_setup, ut_teardown,\t\t\t\\\n+\t\t\t\tcpu_crypto_gcm_perf##a##_##c),\t\t\\\n+\n+\t\tall_gcm_perf_test_cases(SGL_ONE_SEG)\n+\t\tall_gcm_perf_test_cases(SGL_MAX_SEG)\n+#undef TEST_EXPAND\n+\n+\t\tTEST_CASES_END() /**< NULL terminate unit test array */\n+\t\t},\n+};\n+\n+static int\n+test_security_cpu_crypto_aesni_gcm_perf(void)\n+{\n+\tgbl_driver_id =\trte_cryptodev_driver_id_get(\n+\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_GCM_PMD));\n+\n+\treturn unit_test_suite_runner(\n+\t\t\t&security_cpu_crypto_aesgcm_perf_testsuite);\n+}\n+\n REGISTER_TEST_COMMAND(security_aesni_gcm_autotest,\n \t\ttest_security_cpu_crypto_aesni_gcm);\n+\n+REGISTER_TEST_COMMAND(security_aesni_gcm_perftest,\n+\t\ttest_security_cpu_crypto_aesni_gcm_perf);\n",
    "prefixes": [
        "04/10"
    ]
}