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GET /api/patches/58869/?format=api
{ "id": 58869, "url": "http://patchwork.dpdk.org/api/patches/58869/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20190906131330.40185-8-roy.fan.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20190906131330.40185-8-roy.fan.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20190906131330.40185-8-roy.fan.zhang@intel.com", "date": "2019-09-06T13:13:27", "name": "[07/10] app/test: add aesni_mb security cpu crypto perftest", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "fc60e0c1777b587fa405523108fb549dd3968df9", "submitter": { "id": 304, "url": "http://patchwork.dpdk.org/api/people/304/?format=api", "name": "Fan Zhang", "email": "roy.fan.zhang@intel.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20190906131330.40185-8-roy.fan.zhang@intel.com/mbox/", "series": [ { "id": 6303, "url": "http://patchwork.dpdk.org/api/series/6303/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=6303", "date": "2019-09-06T13:13:20", "name": "security: add software synchronous crypto process", "version": 1, "mbox": "http://patchwork.dpdk.org/series/6303/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/58869/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/58869/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 117A11F3B4;\n\tFri, 6 Sep 2019 15:14:00 +0200 (CEST)", "from mga18.intel.com (mga18.intel.com [134.134.136.126])\n\tby dpdk.org (Postfix) with ESMTP id 32D751F392\n\tfor <dev@dpdk.org>; Fri, 6 Sep 2019 15:13:46 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n\tby orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t06 Sep 2019 06:13:45 -0700", "from silpixa00398673.ir.intel.com (HELO\n\tsilpixa00398673.ger.corp.intel.com) ([10.237.223.136])\n\tby fmsmga002.fm.intel.com with ESMTP; 06 Sep 2019 06:13:44 -0700" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.64,473,1559545200\"; d=\"scan'208\";a=\"213140773\"", "From": "Fan Zhang <roy.fan.zhang@intel.com>", "To": "dev@dpdk.org", "Cc": "konstantin.ananyev@intel.com, declan.doherty@intel.com,\n\takhil.goyal@nxp.com, Fan Zhang <roy.fan.zhang@intel.com>", "Date": "Fri, 6 Sep 2019 14:13:27 +0100", "Message-Id": "<20190906131330.40185-8-roy.fan.zhang@intel.com>", "X-Mailer": "git-send-email 2.14.5", "In-Reply-To": "<20190906131330.40185-1-roy.fan.zhang@intel.com>", "References": "<20190903154046.55992-1-roy.fan.zhang@intel.com>\n\t<20190906131330.40185-1-roy.fan.zhang@intel.com>", "Subject": "[dpdk-dev] [PATCH 07/10] app/test: add aesni_mb security cpu crypto\n\tperftest", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Since crypto perf application does not support rte_security, this patch\nadds a simple AES-CBC-SHA1-HMAC CPU crypto performance test to crypto\nunittest application. The test includes different key and data sizes test\nwith single buffer test items and will display the throughput as well as\ncycle count performance information.\n\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\n---\n app/test/test_security_cpu_crypto.c | 194 ++++++++++++++++++++++++++++++++++++\n 1 file changed, 194 insertions(+)", "diff": "diff --git a/app/test/test_security_cpu_crypto.c b/app/test/test_security_cpu_crypto.c\nindex 0ea406390..6e012672e 100644\n--- a/app/test/test_security_cpu_crypto.c\n+++ b/app/test/test_security_cpu_crypto.c\n@@ -1122,6 +1122,197 @@ test_security_cpu_crypto_aesni_mb(void)\n \treturn unit_test_suite_runner(&security_cpu_crypto_aesni_mb_testsuite);\n }\n \n+static inline void\n+switch_blockcipher_enc_to_dec(struct blockcipher_test_data *tdata,\n+\t\tstruct cpu_crypto_test_case *tcase, uint8_t *dst)\n+{\n+\tmemcpy(dst, tcase->seg_buf[0].seg, tcase->seg_buf[0].seg_len);\n+\ttdata->ciphertext.len = tcase->seg_buf[0].seg_len;\n+\tmemcpy(tdata->digest.data, tcase->digest, tdata->digest.len);\n+}\n+\n+static int\n+cpu_crypto_test_blockcipher_perf(\n+\t\tconst enum rte_crypto_cipher_algorithm cipher_algo,\n+\t\tuint32_t cipher_key_sz,\n+\t\tconst enum rte_crypto_auth_algorithm auth_algo,\n+\t\tuint32_t auth_key_sz, uint32_t digest_sz,\n+\t\tuint32_t op_mask)\n+{\n+\tstruct blockcipher_test_data tdata = {0};\n+\tuint8_t plaintext[3000], ciphertext[3000];\n+\tstruct cpu_crypto_testsuite_params *ts_params = &testsuite_params;\n+\tstruct cpu_crypto_unittest_params *ut_params = &unittest_params;\n+\tstruct cpu_crypto_test_obj *obj = &ut_params->test_obj;\n+\tstruct cpu_crypto_test_case *tcase;\n+\tuint64_t hz = rte_get_tsc_hz(), time_start, time_now;\n+\tdouble rate, cycles_per_buf;\n+\tuint32_t test_data_szs[] = {64, 128, 256, 512, 1024, 2048};\n+\tuint32_t i, j;\n+\tuint32_t op_mask_opp = 0;\n+\tint ret;\n+\n+\tif (op_mask & BLOCKCIPHER_TEST_OP_CIPHER)\n+\t\top_mask_opp |= (~op_mask & BLOCKCIPHER_TEST_OP_CIPHER);\n+\tif (op_mask & BLOCKCIPHER_TEST_OP_AUTH)\n+\t\top_mask_opp |= (~op_mask & BLOCKCIPHER_TEST_OP_AUTH);\n+\n+\ttdata.plaintext.data = plaintext;\n+\ttdata.ciphertext.data = ciphertext;\n+\n+\ttdata.cipher_key.len = cipher_key_sz;\n+\ttdata.auth_key.len = auth_key_sz;\n+\n+\tgen_rand(tdata.cipher_key.data, cipher_key_sz / 8);\n+\tgen_rand(tdata.auth_key.data, auth_key_sz / 8);\n+\n+\ttdata.crypto_algo = cipher_algo;\n+\ttdata.auth_algo = auth_algo;\n+\n+\ttdata.digest.len = digest_sz;\n+\n+\tut_params->sess = create_blockcipher_session(ts_params->ctx,\n+\t\t\tts_params->session_priv_mpool,\n+\t\t\top_mask,\n+\t\t\t&tdata,\n+\t\t\t0);\n+\tif (!ut_params->sess)\n+\t\treturn -1;\n+\n+\tret = allocate_buf(MAX_NUM_OPS_INFLIGHT);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < RTE_DIM(test_data_szs); i++) {\n+\t\tfor (j = 0; j < MAX_NUM_OPS_INFLIGHT; j++) {\n+\t\t\ttdata.plaintext.len = test_data_szs[i];\n+\t\t\tgen_rand(plaintext, tdata.plaintext.len);\n+\n+\t\t\ttdata.iv.len = 16;\n+\t\t\tgen_rand(tdata.iv.data, tdata.iv.len);\n+\n+\t\t\ttcase = ut_params->test_datas[j];\n+\t\t\tret = assemble_blockcipher_buf(tcase, obj, j,\n+\t\t\t\t\top_mask,\n+\t\t\t\t\t&tdata,\n+\t\t\t\t\t0);\n+\t\t\tif (ret < 0) {\n+\t\t\t\tprintf(\"Test is not supported by the driver\\n\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\t/* warm up cache */\n+\t\tfor (j = 0; j < CACHE_WARM_ITER; j++)\n+\t\t\trun_test(ts_params->ctx, ut_params->sess, obj,\n+\t\t\t\t\tMAX_NUM_OPS_INFLIGHT);\n+\n+\t\ttime_start = rte_rdtsc();\n+\n+\t\trun_test(ts_params->ctx, ut_params->sess, obj,\n+\t\t\t\tMAX_NUM_OPS_INFLIGHT);\n+\n+\t\ttime_now = rte_rdtsc();\n+\n+\t\trate = time_now - time_start;\n+\t\tcycles_per_buf = rate / MAX_NUM_OPS_INFLIGHT;\n+\n+\t\trate = ((hz / cycles_per_buf)) / 1000000;\n+\n+\t\tprintf(\"%s-%u-%s(%4uB) Enc %03.3fMpps (%03.3fGbps) \",\n+\t\t\trte_crypto_cipher_algorithm_strings[cipher_algo],\n+\t\t\tcipher_key_sz * 8,\n+\t\t\trte_crypto_auth_algorithm_strings[auth_algo],\n+\t\t\ttest_data_szs[i],\n+\t\t\trate, rate * test_data_szs[i] * 8 / 1000);\n+\t\tprintf(\"cycles per buf %03.3f per byte %03.3f\\n\",\n+\t\t\tcycles_per_buf, cycles_per_buf / test_data_szs[i]);\n+\n+\t\tfor (j = 0; j < MAX_NUM_OPS_INFLIGHT; j++) {\n+\t\t\ttcase = ut_params->test_datas[j];\n+\n+\t\t\tswitch_blockcipher_enc_to_dec(&tdata, tcase,\n+\t\t\t\t\tciphertext);\n+\t\t\tret = assemble_blockcipher_buf(tcase, obj, j,\n+\t\t\t\t\top_mask_opp,\n+\t\t\t\t\t&tdata,\n+\t\t\t\t\t0);\n+\t\t\tif (ret < 0) {\n+\t\t\t\tprintf(\"Test is not supported by the driver\\n\");\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\t\t}\n+\n+\t\ttime_start = rte_get_timer_cycles();\n+\n+\t\trun_test(ts_params->ctx, ut_params->sess, obj,\n+\t\t\t\tMAX_NUM_OPS_INFLIGHT);\n+\n+\t\ttime_now = rte_get_timer_cycles();\n+\n+\t\trate = time_now - time_start;\n+\t\tcycles_per_buf = rate / MAX_NUM_OPS_INFLIGHT;\n+\n+\t\trate = ((hz / cycles_per_buf)) / 1000000;\n+\n+\t\tprintf(\"%s-%u-%s(%4uB) Dec %03.3fMpps (%03.3fGbps) \",\n+\t\t\trte_crypto_cipher_algorithm_strings[cipher_algo],\n+\t\t\tcipher_key_sz * 8,\n+\t\t\trte_crypto_auth_algorithm_strings[auth_algo],\n+\t\t\ttest_data_szs[i],\n+\t\t\trate, rate * test_data_szs[i] * 8 / 1000);\n+\t\tprintf(\"cycles per buf %03.3f per byte %03.3f\\n\",\n+\t\t\t\tcycles_per_buf,\n+\t\t\t\tcycles_per_buf / test_data_szs[i]);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/* cipher-algo/cipher-key-len/auth-algo/auth-key-len/digest-len/op */\n+#define all_block_cipher_perf_test_cases\t\t\t\t\\\n+\tTEST_EXPAND(_AES_CBC, 128, _NULL, 0, 0, TOP_ENC)\t\t\\\n+\tTEST_EXPAND(_NULL, 0, _SHA1_HMAC, 160, 20, TOP_AUTH_GEN)\t\\\n+\tTEST_EXPAND(_AES_CBC, 128, _SHA1_HMAC, 160, 20, TOP_ENC_AUTH)\n+\n+#define TEST_EXPAND(a, b, c, d, e, f)\t\t\t\t\t\\\n+static int\t\t\t\t\t\t\t\t\\\n+cpu_crypto_blockcipher_perf##a##_##b##c##_##f(void)\t\t\t\\\n+{\t\t\t\t\t\t\t\t\t\\\n+\treturn cpu_crypto_test_blockcipher_perf(RTE_CRYPTO_CIPHER##a,\t\\\n+\t\t\tb / 8, RTE_CRYPTO_AUTH##c, d / 8, e, f);\t\\\n+}\t\t\t\t\t\t\t\t\t\\\n+\n+all_block_cipher_perf_test_cases\n+#undef TEST_EXPAND\n+\n+static struct unit_test_suite security_cpu_crypto_aesni_mb_perf_testsuite = {\n+\t.suite_name = \"Security CPU Crypto AESNI-MB Perf Test Suite\",\n+\t.setup = testsuite_setup,\n+\t.teardown = testsuite_teardown,\n+\t.unit_test_cases = {\n+#define TEST_EXPAND(a, b, c, d, e, f)\t\t\t\t\t\\\n+\tTEST_CASE_ST(ut_setup, ut_teardown,\t\t\t\t\\\n+\t\tcpu_crypto_blockcipher_perf##a##_##b##c##_##f),\t\\\n+\n+\tall_block_cipher_perf_test_cases\n+#undef TEST_EXPAND\n+\n+\tTEST_CASES_END() /**< NULL terminate unit test array */\n+\t},\n+};\n+\n+static int\n+test_security_cpu_crypto_aesni_mb_perf(void)\n+{\n+\tgbl_driver_id =\trte_cryptodev_driver_id_get(\n+\t\t\tRTE_STR(CRYPTODEV_NAME_AESNI_MB_PMD));\n+\n+\treturn unit_test_suite_runner(\n+\t\t\t&security_cpu_crypto_aesni_mb_perf_testsuite);\n+}\n+\n+\n REGISTER_TEST_COMMAND(security_aesni_gcm_autotest,\n \t\ttest_security_cpu_crypto_aesni_gcm);\n \n@@ -1130,3 +1321,6 @@ REGISTER_TEST_COMMAND(security_aesni_gcm_perftest,\n \n REGISTER_TEST_COMMAND(security_aesni_mb_autotest,\n \t\ttest_security_cpu_crypto_aesni_mb);\n+\n+REGISTER_TEST_COMMAND(security_aesni_mb_perftest,\n+\t\ttest_security_cpu_crypto_aesni_mb_perf);\n", "prefixes": [ "07/10" ] }