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GET /api/patches/624/?format=api
{ "id": 624, "url": "http://patchwork.dpdk.org/api/patches/624/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1411974986-28137-5-git-send-email-changchun.ouyang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1411974986-28137-5-git-send-email-changchun.ouyang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1411974986-28137-5-git-send-email-changchun.ouyang@intel.com", "date": "2014-09-29T07:16:12", "name": "[dpdk-dev,v2,04/18] ixgbe: Support cloud mode in IXGBE base code", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "01bdd57112924113eefffc56a705c7f9ae181d65", "submitter": { "id": 31, "url": "http://patchwork.dpdk.org/api/people/31/?format=api", "name": "Ouyang Changchun", "email": "changchun.ouyang@intel.com" }, "delegate": null, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1411974986-28137-5-git-send-email-changchun.ouyang@intel.com/mbox/", "series": [], "comments": "http://patchwork.dpdk.org/api/patches/624/comments/", "check": "pending", "checks": "http://patchwork.dpdk.org/api/patches/624/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@dpdk.org", "Delivered-To": "patchwork@dpdk.org", "Received": [ "from [92.243.14.124] (localhost [IPv6:::1])\n\tby dpdk.org (Postfix) with ESMTP id F03137E38;\n\tMon, 29 Sep 2014 09:10:36 +0200 (CEST)", "from mga01.intel.com (mga01.intel.com [192.55.52.88])\n\tby dpdk.org (Postfix) with ESMTP id 959037E17\n\tfor <dev@dpdk.org>; Mon, 29 Sep 2014 09:10:23 +0200 (CEST)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n\tby fmsmga101.fm.intel.com with ESMTP; 29 Sep 2014 00:16:57 -0700", "from shvmail01.sh.intel.com ([10.239.29.42])\n\tby fmsmga001.fm.intel.com with ESMTP; 29 Sep 2014 00:16:57 -0700", "from shecgisg004.sh.intel.com (shecgisg004.sh.intel.com\n\t[10.239.29.89])\n\tby shvmail01.sh.intel.com with ESMTP id s8T7Gtpk012668;\n\tMon, 29 Sep 2014 15:16:55 +0800", "from shecgisg004.sh.intel.com (localhost [127.0.0.1])\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/SuSE Linux 0.8) with ESMTP\n\tid s8T7GrYT028362; Mon, 29 Sep 2014 15:16:55 +0800", "(from couyang@localhost)\n\tby shecgisg004.sh.intel.com (8.13.6/8.13.6/Submit) id s8T7GrXP028358; \n\tMon, 29 Sep 2014 15:16:53 +0800" ], "X-ExtLoop1": "1", "X-IronPort-AV": "E=Sophos;i=\"5.04,618,1406617200\"; d=\"scan'208\";a=\"598147144\"", "From": "Ouyang Changchun <changchun.ouyang@intel.com>", "To": "dev@dpdk.org", "Date": "Mon, 29 Sep 2014 15:16:12 +0800", "Message-Id": "<1411974986-28137-5-git-send-email-changchun.ouyang@intel.com>", "X-Mailer": "git-send-email 1.7.4.1", "In-Reply-To": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "References": "<1411974986-28137-1-git-send-email-changchun.ouyang@intel.com>", "Subject": "[dpdk-dev] [PATCH v2 04/18] ixgbe: Support cloud mode in IXGBE base\n\tcode", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "patches and discussions about DPDK <dev.dpdk.org>", "List-Unsubscribe": "<http://dpdk.org/ml/options/dev>,\n\t<mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://dpdk.org/ml/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<http://dpdk.org/ml/listinfo/dev>,\n\t<mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "This patch supports cloud mode in IXGBE base code.\n\nSigned-off-by: Changchun Ouyang <changchun.ouyang@intel.com>\n---\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c | 70 ++++++++++++++++++++++++++++++++\n lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h | 10 +++++\n 2 files changed, 80 insertions(+)", "diff": "diff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\nindex 126aa24..adf0e52 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_82599.c\n@@ -1497,6 +1497,9 @@ s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,\n \t\t (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |\n \t\t (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);\n \n+\tif (cloud_mode)\n+\t\tfdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<\n+\t\t\t\t\tIXGBE_FDIRCTRL_FILTERMODE_SHIFT);\n \n \t/* write hashes and fdirctrl register, poll for completion */\n \tixgbe_fdir_enable_82599(hw, fdirctrl);\n@@ -1766,6 +1769,7 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \t/* mask IPv6 since it is currently not supported */\n \tu32 fdirm = IXGBE_FDIRM_DIPv6;\n \tu32 fdirtcpm;\n+\tu32 fdirip6m;\n \tDEBUGFUNC(\"ixgbe_fdir_set_atr_input_mask_82599\");\n \n \t/*\n@@ -1838,6 +1842,49 @@ s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,\n \t\treturn IXGBE_ERR_CONFIG;\n \t}\n \n+\tif (cloud_mode) {\n+\t\tfdirm |= IXGBE_FDIRM_L3P;\n+\t\tfdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);\n+\t\tfdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;\n+\n+\t\tswitch (input_mask->formatted.inner_mac[0] & 0xFF) {\n+\t\tcase 0x00:\n+\t\t\t/* Mask inner MAC, fall through */\n+\t\t\tfdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;\n+\t\tcase 0xFF:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDEBUGOUT(\" Error on inner_mac byte mask\\n\");\n+\t\t\treturn IXGBE_ERR_CONFIG;\n+\t\t}\n+\n+\t\tswitch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {\n+\t\tcase 0x0:\n+\t\t\t/* Mask vxlan id */\n+\t\t\tfdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;\n+\t\t\tbreak;\n+\t\tcase 0x00FFFFFF:\n+\t\t\tfdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;\n+\t\t\tbreak;\n+\t\tcase 0xFFFFFFFF:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDEBUGOUT(\" Error on TNI/VNI byte mask\\n\");\n+\t\t\treturn IXGBE_ERR_CONFIG;\n+\t\t}\n+\n+\t\tswitch (input_mask->formatted.tunnel_type & 0xFFFF) {\n+\t\tcase 0x0:\n+\t\t\t/* Mask turnnel type, fall through */\n+\t\t\tfdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;\n+\t\tcase 0xFFFF:\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tDEBUGOUT(\" Error on tunnel type byte mask\\n\");\n+\t\t\treturn IXGBE_ERR_CONFIG;\n+\t\t}\n+\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);\n+\t}\n \n \t/* Now mask VM pool and destination IPv6 - bits 5 and 2 */\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);\n@@ -1863,6 +1910,9 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n \t\t\t\t\t u16 soft_id, u8 queue, bool cloud_mode)\n {\n \tu32 fdirport, fdirvlan, fdirhash, fdircmd;\n+\tu32 addr_low, addr_high;\n+\tu32 cloud_type = 0;\n+\ts32 err;\n \n \tDEBUGFUNC(\"ixgbe_fdir_write_perfect_filter_82599\");\n \n@@ -1892,6 +1942,21 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n \tfdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);\n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);\n \n+\tif (cloud_mode) {\n+\t\tif (input->formatted.tunnel_type != 0)\n+\t\t\tcloud_type = 0x80000000;\n+\n+\t\taddr_low = ((u32)input->formatted.inner_mac[0] |\n+\t\t\t\t((u32)input->formatted.inner_mac[1] << 8) |\n+\t\t\t\t((u32)input->formatted.inner_mac[2] << 16) |\n+\t\t\t\t((u32)input->formatted.inner_mac[3] << 24));\n+\t\taddr_high = ((u32)input->formatted.inner_mac[4] |\n+\t\t\t\t((u32)input->formatted.inner_mac[5] << 8));\n+\t\tcloud_type |= addr_high;\n+\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);\n+\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);\n+\t\tIXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);\n+\t}\n \n \t/* configure FDIRHASH register */\n \tfdirhash = input->formatted.bkt_hash;\n@@ -1916,6 +1981,11 @@ s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,\n \tfdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;\n \n \tIXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);\n+\terr = ixgbe_fdir_check_cmd_complete(hw);\n+\tif (err) {\n+\t\tDEBUGOUT(\"Flow Director command did not complete!\\n\");\n+\t\treturn err;\n+\t}\n \n \treturn IXGBE_SUCCESS;\n }\ndiff --git a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\nindex 18ac227..f4c2534 100644\n--- a/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n+++ b/lib/librte_pmd_ixgbe/ixgbe/ixgbe_type.h\n@@ -2369,6 +2369,9 @@ enum ixgbe_fdir_pballoc_type {\n #define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS\t0x00000080\n #define IXGBE_FDIRCTRL_DROP_Q_SHIFT\t\t8\n #define IXGBE_FDIRCTRL_FLEX_SHIFT\t\t16\n+#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT\t\t21\n+#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN\t0x0001 /* bit 23:21, 001b */\n+#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD\t\t0x0002 /* bit 23:21, 010b */\n #define IXGBE_FDIRCTRL_SEARCHLIM\t\t0x00800000\n #define IXGBE_FDIRCTRL_FILTERMODE_MASK\t\t0x00E00000\n #define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT\t\t24\n@@ -2384,6 +2387,13 @@ enum ixgbe_fdir_pballoc_type {\n #define IXGBE_FDIRM_L4P\t\t\t\t0x00000008\n #define IXGBE_FDIRM_FLEX\t\t\t0x00000010\n #define IXGBE_FDIRM_DIPv6\t\t\t0x00000020\n+#define IXGBE_FDIRM_L3P\t\t\t\t0x00000040\n+\n+#define IXGBE_FDIRIP6M_INNER_MAC\t0x03F0 /* bit 9:4 */\n+#define IXGBE_FDIRIP6M_TUNNEL_TYPE\t0x0800 /* bit 11 */\n+#define IXGBE_FDIRIP6M_TNI_VNI\t\t0xF000 /* bit 15:12 */\n+#define IXGBE_FDIRIP6M_TNI_VNI_24\t0x1000 /* bit 12 */\n+#define IXGBE_FDIRIP6M_ALWAYS_MASK\t0x040F /* bit 10, 3:0 */\n \n #define IXGBE_FDIRFREE_FREE_MASK\t\t0xFFFF\n #define IXGBE_FDIRFREE_FREE_SHIFT\t\t0\n", "prefixes": [ "dpdk-dev", "v2", "04/18" ] }