Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 69222,
    "url": "http://patchwork.dpdk.org/api/patches/69222/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200424032159.992-5-joyce.kong@arm.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200424032159.992-5-joyce.kong@arm.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200424032159.992-5-joyce.kong@arm.com",
    "date": "2020-04-24T03:21:57",
    "name": "[v9,4/6] net/bnx2x: use common rte bit operation APIs instead",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "aaf45769388c3a2b0cd6aaf12e51e215ac47de3b",
    "submitter": {
        "id": 970,
        "url": "http://patchwork.dpdk.org/api/people/970/?format=api",
        "name": "Joyce Kong",
        "email": "joyce.kong@arm.com"
    },
    "delegate": {
        "id": 24651,
        "url": "http://patchwork.dpdk.org/api/users/24651/?format=api",
        "username": "dmarchand",
        "first_name": "David",
        "last_name": "Marchand",
        "email": "david.marchand@redhat.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200424032159.992-5-joyce.kong@arm.com/mbox/",
    "series": [
        {
            "id": 9606,
            "url": "http://patchwork.dpdk.org/api/series/9606/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=9606",
            "date": "2020-04-24T03:21:53",
            "name": "implement common bit operation APIs",
            "version": 9,
            "mbox": "http://patchwork.dpdk.org/series/9606/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/69222/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/69222/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 79FA6A00C4;\n\tFri, 24 Apr 2020 05:23:09 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id E848A1BFE9;\n\tFri, 24 Apr 2020 05:22:58 +0200 (CEST)",
            "from foss.arm.com (foss.arm.com [217.140.110.172])\n by dpdk.org (Postfix) with ESMTP id B4916493D\n for <dev@dpdk.org>; Fri, 24 Apr 2020 05:22:57 +0200 (CEST)",
            "from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14])\n by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 32644C14;\n Thu, 23 Apr 2020 20:22:57 -0700 (PDT)",
            "from net-arm-thunderx2-03.shanghai.arm.com\n (net-arm-thunderx2-03.shanghai.arm.com [10.169.41.185])\n by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 1E3983F68F;\n Thu, 23 Apr 2020 20:22:51 -0700 (PDT)"
        ],
        "From": "Joyce Kong <joyce.kong@arm.com>",
        "To": "thomas@monjalon.net, stephen@networkplumber.org,\n david.marchand@redhat.com,\n mb@smartsharesystems.com, jerinj@marvell.com, bruce.richardson@intel.com,\n ravi1.kumar@amd.com, rmody@marvell.com, shshaikh@marvell.com,\n xuanziyang2@huawei.com, cloud.wangxiaoyun@huawei.com,\n zhouguoyang@huawei.com, honnappa.nagarahalli@arm.com, gavin.hu@arm.com,\n phil.yang@arm.com",
        "Cc": "nd@arm.com,\n\tdev@dpdk.org",
        "Date": "Fri, 24 Apr 2020 11:21:57 +0800",
        "Message-Id": "<20200424032159.992-5-joyce.kong@arm.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": [
            "<20200424032159.992-1-joyce.kong@arm.com>",
            "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>"
        ],
        "References": [
            "<20200424032159.992-1-joyce.kong@arm.com>",
            "<1571125801-45773-1-git-send-email-joyce.kong@arm.com>"
        ],
        "Subject": "[dpdk-dev] [PATCH v9 4/6] net/bnx2x: use common rte bit operation\n\tAPIs instead",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Remove its own bit operation APIs and use the common one,\nthis can reduce the code duplication largely.\n\nSigned-off-by: Joyce Kong <joyce.kong@arm.com>\nReviewed-by: Gavin Hu <gavin.hu@arm.com>\n---\n drivers/net/bnx2x/bnx2x.c    | 271 +++++++++++++++++------------------\n drivers/net/bnx2x/bnx2x.h    |  10 +-\n drivers/net/bnx2x/ecore_sp.c |  68 ++++-----\n drivers/net/bnx2x/ecore_sp.h | 106 +++++++-------\n 4 files changed, 221 insertions(+), 234 deletions(-)",
    "diff": "diff --git a/drivers/net/bnx2x/bnx2x.c b/drivers/net/bnx2x/bnx2x.c\nindex 0b4030e2b..eaed6274a 100644\n--- a/drivers/net/bnx2x/bnx2x.c\n+++ b/drivers/net/bnx2x/bnx2x.c\n@@ -25,6 +25,7 @@\n #include <sys/stat.h>\n #include <fcntl.h>\n #include <zlib.h>\n+#include <rte_bitops.h>\n #include <rte_string_fns.h>\n \n #define BNX2X_PMD_VER_PREFIX \"BNX2X PMD\"\n@@ -129,32 +130,6 @@ static void bnx2x_ack_sb(struct bnx2x_softc *sc, uint8_t igu_sb_id,\n \t\t\t uint8_t storm, uint16_t index, uint8_t op,\n \t\t\t uint8_t update);\n \n-int bnx2x_test_bit(int nr, volatile unsigned long *addr)\n-{\n-\tint res;\n-\n-\tmb();\n-\tres = ((*addr) & (1UL << nr)) != 0;\n-\tmb();\n-\treturn res;\n-}\n-\n-void bnx2x_set_bit(unsigned int nr, volatile unsigned long *addr)\n-{\n-\t__sync_fetch_and_or(addr, (1UL << nr));\n-}\n-\n-void bnx2x_clear_bit(int nr, volatile unsigned long *addr)\n-{\n-\t__sync_fetch_and_and(addr, ~(1UL << nr));\n-}\n-\n-int bnx2x_test_and_clear_bit(int nr, volatile unsigned long *addr)\n-{\n-\tunsigned long mask = (1UL << nr);\n-\treturn __sync_fetch_and_and(addr, ~mask) & mask;\n-}\n-\n int bnx2x_cmpxchg(volatile int *addr, int old, int new)\n {\n \treturn __sync_val_compare_and_swap(addr, old, new);\n@@ -1434,16 +1409,16 @@ static int\n bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,\n \t\t int mac_type, uint8_t wait_for_comp)\n {\n-\tunsigned long ramrod_flags = 0, vlan_mac_flags = 0;\n+\tuint32_t ramrod_flags = 0, vlan_mac_flags = 0;\n \tint rc;\n \n \t/* wait for completion of requested */\n \tif (wait_for_comp) {\n-\t\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n+\t\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags);\n \t}\n \n \t/* Set the mac type of addresses we want to clear */\n-\tbnx2x_set_bit(mac_type, &vlan_mac_flags);\n+\trte_set_bit32_relaxed(mac_type, &vlan_mac_flags);\n \n \trc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);\n \tif (rc < 0)\n@@ -1454,8 +1429,7 @@ bnx2x_del_all_macs(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *mac_obj,\n \n static int\n bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,\n-\t\t\tunsigned long *rx_accept_flags,\n-\t\t\tunsigned long *tx_accept_flags)\n+\t\t\tuint32_t *rx_accept_flags, uint32_t *tx_accept_flags)\n {\n \t/* Clear the flags first */\n \t*rx_accept_flags = 0;\n@@ -1470,26 +1444,28 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,\n \t\tbreak;\n \n \tcase BNX2X_RX_MODE_NORMAL:\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_MULTICAST, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n \n \t\t/* internal switching mode */\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_MULTICAST, tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n \n \t\tbreak;\n \n \tcase BNX2X_RX_MODE_ALLMULTI:\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST,\n+\t\t\t\t      rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n \n \t\t/* internal switching mode */\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST,\n+\t\t\t\t      tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n \n \t\tbreak;\n \n@@ -1500,19 +1476,23 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,\n \t\t * should receive matched and unmatched (in resolution of port)\n \t\t * unicast packets.\n \t\t */\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_UNMATCHED, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST,\n+\t\t\t\t      rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, rx_accept_flags);\n \n \t\t/* internal switching mode */\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_ALL_MULTICAST,\n+\t\t\t\t      tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_BROADCAST, tx_accept_flags);\n \n \t\tif (IS_MF_SI(sc)) {\n-\t\t\tbnx2x_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags);\n+\t\t\trte_set_bit32_relaxed(ECORE_ACCEPT_ALL_UNICAST,\n+\t\t\t\t\ttx_accept_flags);\n \t\t} else {\n-\t\t\tbnx2x_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags);\n+\t\t\trte_set_bit32_relaxed(ECORE_ACCEPT_UNICAST,\n+\t\t\t\t\t      tx_accept_flags);\n \t\t}\n \n \t\tbreak;\n@@ -1524,8 +1504,8 @@ bnx2x_fill_accept_flags(struct bnx2x_softc *sc, uint32_t rx_mode,\n \n \t/* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */\n \tif (rx_mode != BNX2X_RX_MODE_NONE) {\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);\n-\t\tbnx2x_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags);\n+\t\trte_set_bit32_relaxed(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags);\n \t}\n \n \treturn 0;\n@@ -1554,7 +1534,7 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,\n \tramrod_param.rdata = BNX2X_SP(sc, rx_mode_rdata);\n \tramrod_param.rdata_mapping =\n \t    (rte_iova_t)BNX2X_SP_MAPPING(sc, rx_mode_rdata),\n-\t    bnx2x_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);\n+\t    rte_set_bit32_relaxed(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);\n \n \tramrod_param.ramrod_flags = ramrod_flags;\n \tramrod_param.rx_mode_flags = rx_mode_flags;\n@@ -1573,8 +1553,8 @@ bnx2x_set_q_rx_mode(struct bnx2x_softc *sc, uint8_t cl_id,\n \n int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)\n {\n-\tunsigned long rx_mode_flags = 0, ramrod_flags = 0;\n-\tunsigned long rx_accept_flags = 0, tx_accept_flags = 0;\n+\tuint32_t rx_mode_flags = 0, ramrod_flags = 0;\n+\tuint32_t rx_accept_flags = 0, tx_accept_flags = 0;\n \tint rc;\n \n \trc = bnx2x_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags,\n@@ -1583,9 +1563,9 @@ int bnx2x_set_storm_rx_mode(struct bnx2x_softc *sc)\n \t\treturn rc;\n \t}\n \n-\tbnx2x_set_bit(RAMROD_RX, &ramrod_flags);\n-\tbnx2x_set_bit(RAMROD_TX, &ramrod_flags);\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_RX, &ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_TX, &ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags);\n \n \treturn bnx2x_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags,\n \t\t\t\t rx_accept_flags, tx_accept_flags,\n@@ -1710,7 +1690,8 @@ static int bnx2x_func_wait_started(struct bnx2x_softc *sc)\n \t\t\t    \"Forcing STARTED-->TX_STOPPED-->STARTED\");\n \n \t\tfunc_params.f_obj = &sc->func_obj;\n-\t\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);\n+\t\trte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY,\n+\t\t\t\t      &func_params.ramrod_flags);\n \n \t\t/* STARTED-->TX_STOPPED */\n \t\tfunc_params.cmd = ECORE_F_CMD_TX_STOP;\n@@ -1734,7 +1715,7 @@ static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)\n \n \tq_params.q_obj = &sc->sp_objs[fp->index].q_obj;\n \t/* We want to wait for completion in this context */\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &q_params.ramrod_flags);\n \n \t/* Stop the primary connection: */\n \n@@ -1763,26 +1744,25 @@ static int bnx2x_stop_queue(struct bnx2x_softc *sc, int index)\n }\n \n /* wait for the outstanding SP commands */\n-static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, unsigned long mask)\n+static uint8_t bnx2x_wait_sp_comp(struct bnx2x_softc *sc, uint32_t mask)\n {\n-\tunsigned long tmp;\n+\tuint32_t tmp;\n \tint tout = 5000;\t/* wait for 5 secs tops */\n \n \twhile (tout--) {\n \t\tmb();\n-\t\tif (!(atomic_load_acq_long(&sc->sp_state) & mask)) {\n+\t\tif (!(atomic_load_acq_int(&sc->sp_state) & mask))\n \t\t\treturn TRUE;\n-\t\t}\n \n \t\tDELAY(1000);\n \t}\n \n \tmb();\n \n-\ttmp = atomic_load_acq_long(&sc->sp_state);\n+\ttmp = atomic_load_acq_int(&sc->sp_state);\n \tif (tmp & mask) {\n \t\tPMD_DRV_LOG(INFO, sc, \"Filtering completion timed out: \"\n-\t\t\t    \"sp_state 0x%lx, mask 0x%lx\", tmp, mask);\n+\t\t\t    \"sp_state 0x%x, mask 0x%x\", tmp, mask);\n \t\treturn FALSE;\n \t}\n \n@@ -1795,7 +1775,7 @@ static int bnx2x_func_stop(struct bnx2x_softc *sc)\n \tint rc;\n \n \t/* prepare parameters for function state transitions */\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n \tfunc_params.f_obj = &sc->func_obj;\n \tfunc_params.cmd = ECORE_F_CMD_STOP;\n \n@@ -1809,7 +1789,8 @@ static int bnx2x_func_stop(struct bnx2x_softc *sc)\n \tif (rc) {\n \t\tPMD_DRV_LOG(NOTICE, sc, \"FUNC_STOP ramrod failed. \"\n \t\t\t    \"Running a dry transaction\");\n-\t\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags);\n+\t\trte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY,\n+\t\t\t\t      &func_params.ramrod_flags);\n \t\treturn ecore_func_state_change(sc, &func_params);\n \t}\n \n@@ -1821,7 +1802,7 @@ static int bnx2x_reset_hw(struct bnx2x_softc *sc, uint32_t load_code)\n \tstruct ecore_func_state_params func_params = { NULL };\n \n \t/* Prepare parameters for function state transitions */\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n \n \tfunc_params.f_obj = &sc->func_obj;\n \tfunc_params.cmd = ECORE_F_CMD_HW_RESET;\n@@ -1878,11 +1859,11 @@ bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_li\n \t * a race between the completion code and this code.\n \t */\n \n-\tif (bnx2x_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) {\n-\t\tbnx2x_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state);\n-\t} else {\n+\tif (rte_get_bit32_relaxed(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state))\n+\t\trte_set_bit32_relaxed(ECORE_FILTER_RX_MODE_SCHED,\n+\t\t\t\t      &sc->sp_state);\n+\telse\n \t\tbnx2x_set_storm_rx_mode(sc);\n-\t}\n \n \t/* Clean up multicast configuration */\n \trparam.mcast_obj = &sc->mcast_obj;\n@@ -1922,9 +1903,8 @@ bnx2x_chip_cleanup(struct bnx2x_softc *sc, uint32_t unload_mode, uint8_t keep_li\n \t * If SP settings didn't get completed so far - something\n \t * very wrong has happen.\n \t */\n-\tif (!bnx2x_wait_sp_comp(sc, ~0x0UL)) {\n+\tif (!bnx2x_wait_sp_comp(sc, ~0x0U))\n \t\tPMD_DRV_LOG(NOTICE, sc, \"Common slow path ramrods got stuck!\");\n-\t}\n \n unload_error:\n \n@@ -1964,7 +1944,7 @@ static void bnx2x_disable_close_the_gate(struct bnx2x_softc *sc)\n  */\n static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)\n {\n-\tunsigned long ramrod_flags = 0, vlan_mac_flags = 0;\n+\tuint32_t ramrod_flags = 0, vlan_mac_flags = 0;\n \tstruct ecore_mcast_ramrod_params rparam = { NULL };\n \tstruct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj;\n \tint rc;\n@@ -1972,12 +1952,12 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)\n \t/* Cleanup MACs' object first... */\n \n \t/* Wait for completion of requested */\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags);\n \t/* Perform a dry cleanup */\n-\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY, &ramrod_flags);\n \n \t/* Clean ETH primary MAC */\n-\tbnx2x_set_bit(ECORE_ETH_MAC, &vlan_mac_flags);\n+\trte_set_bit32_relaxed(ECORE_ETH_MAC, &vlan_mac_flags);\n \trc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags,\n \t\t\t\t &ramrod_flags);\n \tif (rc != 0) {\n@@ -1986,7 +1966,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)\n \n \t/* Cleanup UC list */\n \tvlan_mac_flags = 0;\n-\tbnx2x_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags);\n+\trte_set_bit32_relaxed(ECORE_UC_LIST_MAC, &vlan_mac_flags);\n \trc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags);\n \tif (rc != 0) {\n \t\tPMD_DRV_LOG(NOTICE, sc,\n@@ -1996,7 +1976,7 @@ static void bnx2x_squeeze_objects(struct bnx2x_softc *sc)\n \t/* Now clean mcast object... */\n \n \trparam.mcast_obj = &sc->mcast_obj;\n-\tbnx2x_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags);\n \n \t/* Add a DEL command... */\n \trc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL);\n@@ -4294,13 +4274,13 @@ static void bnx2x_handle_mcast_eqe(struct bnx2x_softc *sc)\n static void\n bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *elem)\n {\n-\tunsigned long ramrod_flags = 0;\n+\tuint32_t ramrod_flags = 0;\n \tint rc = 0;\n \tuint32_t cid = elem->message.data.eth_event.echo & BNX2X_SWCID_MASK;\n \tstruct ecore_vlan_mac_obj *vlan_mac_obj;\n \n \t/* always push next commands out, don't wait here */\n-\tbnx2x_set_bit(RAMROD_CONT, &ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_CONT, &ramrod_flags);\n \n \tswitch (le32toh(elem->message.data.eth_event.echo) >> BNX2X_SWCID_SHIFT) {\n \tcase ECORE_FILTER_MAC_PENDING:\n@@ -4331,12 +4311,12 @@ bnx2x_handle_classification_eqe(struct bnx2x_softc *sc, union event_ring_elem *e\n \n static void bnx2x_handle_rx_mode_eqe(struct bnx2x_softc *sc)\n {\n-\tbnx2x_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);\n+\trte_clear_bit32_relaxed(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state);\n \n \t/* send rx_mode command again if was requested */\n-\tif (bnx2x_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state)) {\n+\tif (rte_test_and_clear_bit32_relaxed(ECORE_FILTER_RX_MODE_SCHED,\n+\t\t\t\t\t\t&sc->sp_state))\n \t\tbnx2x_set_storm_rx_mode(sc);\n-\t}\n }\n \n static void bnx2x_update_eq_prod(struct bnx2x_softc *sc, uint16_t prod)\n@@ -4705,7 +4685,7 @@ static int bnx2x_init_hw(struct bnx2x_softc *sc, uint32_t load_code)\n \tPMD_INIT_FUNC_TRACE(sc);\n \n \t/* prepare the parameters for function state transitions */\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n \n \tfunc_params.f_obj = &sc->func_obj;\n \tfunc_params.cmd = ECORE_F_CMD_HW_INIT;\n@@ -4953,7 +4933,7 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)\n {\n \tstruct bnx2x_fastpath *fp = &sc->fp[idx];\n \tuint32_t cids[ECORE_MULTI_TX_COS] = { 0 };\n-\tunsigned long q_type = 0;\n+\tuint32_t q_type = 0;\n \tint cos;\n \n \tfp->sc = sc;\n@@ -5000,8 +4980,8 @@ static void bnx2x_init_eth_fp(struct bnx2x_softc *sc, int idx)\n \tbnx2x_update_fp_sb_idx(fp);\n \n \t/* Configure Queue State object */\n-\tbnx2x_set_bit(ECORE_Q_TYPE_HAS_RX, &q_type);\n-\tbnx2x_set_bit(ECORE_Q_TYPE_HAS_TX, &q_type);\n+\trte_set_bit32_relaxed(ECORE_Q_TYPE_HAS_RX, &q_type);\n+\trte_set_bit32_relaxed(ECORE_Q_TYPE_HAS_TX, &q_type);\n \n \tecore_init_queue_obj(sc,\n \t\t\t     &sc->sp_objs[idx].q_obj,\n@@ -5815,7 +5795,7 @@ static int bnx2x_func_start(struct bnx2x_softc *sc)\n \t    &func_params.params.start;\n \n \t/* Prepare parameters for function state transitions */\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &func_params.ramrod_flags);\n \n \tfunc_params.f_obj = &sc->func_obj;\n \tfunc_params.cmd = ECORE_F_CMD_START;\n@@ -6391,11 +6371,11 @@ bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n \tuint8_t cos;\n \tint cxt_index, cxt_offset;\n \n-\tbnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags);\n-\tbnx2x_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_HC, &init_params->rx.flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_HC, &init_params->tx.flags);\n \n-\tbnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);\n-\tbnx2x_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_HC_EN, &init_params->rx.flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_HC_EN, &init_params->tx.flags);\n \n \t/* HC rate */\n \tinit_params->rx.hc_rate =\n@@ -6426,10 +6406,10 @@ bnx2x_pf_q_prep_init(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp,\n static unsigned long\n bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)\n {\n-\tunsigned long flags = 0;\n+\tuint32_t flags = 0;\n \n \t/* PF driver will always initialize the Queue to an ACTIVE state */\n-\tbnx2x_set_bit(ECORE_Q_FLG_ACTIVE, &flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_ACTIVE, &flags);\n \n \t/*\n \t * tx only connections collect statistics (on the same index as the\n@@ -6437,9 +6417,9 @@ bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)\n \t * connection is initialized.\n \t */\n \n-\tbnx2x_set_bit(ECORE_Q_FLG_STATS, &flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_STATS, &flags);\n \tif (zero_stats) {\n-\t\tbnx2x_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags);\n+\t\trte_set_bit32_relaxed(ECORE_Q_FLG_ZERO_STATS, &flags);\n \t}\n \n \t/*\n@@ -6447,28 +6427,28 @@ bnx2x_get_common_flags(struct bnx2x_softc *sc, uint8_t zero_stats)\n \t * CoS-ness doesn't survive the loopback\n \t */\n \tif (sc->flags & BNX2X_TX_SWITCHING) {\n-\t\tbnx2x_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags);\n+\t\trte_set_bit32_relaxed(ECORE_Q_FLG_TX_SWITCH, &flags);\n \t}\n \n-\tbnx2x_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_PCSUM_ON_PKT, &flags);\n \n \treturn flags;\n }\n \n static unsigned long bnx2x_get_q_flags(struct bnx2x_softc *sc, uint8_t leading)\n {\n-\tunsigned long flags = 0;\n+\tuint32_t flags = 0;\n \n \tif (IS_MF_SD(sc)) {\n-\t\tbnx2x_set_bit(ECORE_Q_FLG_OV, &flags);\n+\t\trte_set_bit32_relaxed(ECORE_Q_FLG_OV, &flags);\n \t}\n \n \tif (leading) {\n-\t\tbnx2x_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags);\n-\t\tbnx2x_set_bit(ECORE_Q_FLG_MCAST, &flags);\n+\t\trte_set_bit32_relaxed(ECORE_Q_FLG_LEADING_RSS, &flags);\n+\t\trte_set_bit32_relaxed(ECORE_Q_FLG_MCAST, &flags);\n \t}\n \n-\tbnx2x_set_bit(ECORE_Q_FLG_VLAN, &flags);\n+\trte_set_bit32_relaxed(ECORE_Q_FLG_VLAN, &flags);\n \n \t/* merge with common flags */\n \treturn flags | bnx2x_get_common_flags(sc, TRUE);\n@@ -6589,7 +6569,7 @@ bnx2x_setup_queue(struct bnx2x_softc *sc, struct bnx2x_fastpath *fp, uint8_t lea\n \tq_params.q_obj = &BNX2X_SP_OBJ(sc, fp).q_obj;\n \n \t/* we want to wait for completion in this context */\n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &q_params.ramrod_flags);\n \n \t/* prepare the INIT parameters */\n \tbnx2x_pf_q_prep_init(sc, fp, &q_params.params.init);\n@@ -6657,20 +6637,20 @@ bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj\n \n \tparams.rss_obj = rss_obj;\n \n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &params.ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &params.ramrod_flags);\n \n-\tbnx2x_set_bit(ECORE_RSS_MODE_REGULAR, &params.rss_flags);\n+\trte_set_bit32_relaxed(ECORE_RSS_MODE_REGULAR, &params.rss_flags);\n \n \t/* RSS configuration */\n-\tbnx2x_set_bit(ECORE_RSS_IPV4, &params.rss_flags);\n-\tbnx2x_set_bit(ECORE_RSS_IPV4_TCP, &params.rss_flags);\n-\tbnx2x_set_bit(ECORE_RSS_IPV6, &params.rss_flags);\n-\tbnx2x_set_bit(ECORE_RSS_IPV6_TCP, &params.rss_flags);\n+\trte_set_bit32_relaxed(ECORE_RSS_IPV4, &params.rss_flags);\n+\trte_set_bit32_relaxed(ECORE_RSS_IPV4_TCP, &params.rss_flags);\n+\trte_set_bit32_relaxed(ECORE_RSS_IPV6, &params.rss_flags);\n+\trte_set_bit32_relaxed(ECORE_RSS_IPV6_TCP, &params.rss_flags);\n \tif (rss_obj->udp_rss_v4) {\n-\t\tbnx2x_set_bit(ECORE_RSS_IPV4_UDP, &params.rss_flags);\n+\t\trte_set_bit32_relaxed(ECORE_RSS_IPV4_UDP, &params.rss_flags);\n \t}\n \tif (rss_obj->udp_rss_v6) {\n-\t\tbnx2x_set_bit(ECORE_RSS_IPV6_UDP, &params.rss_flags);\n+\t\trte_set_bit32_relaxed(ECORE_RSS_IPV6_UDP, &params.rss_flags);\n \t}\n \n \t/* Hash bits */\n@@ -6685,7 +6665,7 @@ bnx2x_config_rss_pf(struct bnx2x_softc *sc, struct ecore_rss_config_obj *rss_obj\n \t\t\tparams.rss_key[i] = (uint32_t) rte_rand();\n \t\t}\n \n-\t\tbnx2x_set_bit(ECORE_RSS_SET_SRCH, &params.rss_flags);\n+\t\trte_set_bit32_relaxed(ECORE_RSS_SET_SRCH, &params.rss_flags);\n \t}\n \n \tif (IS_PF(sc))\n@@ -6730,7 +6710,7 @@ static int bnx2x_init_rss_pf(struct bnx2x_softc *sc)\n static int\n bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,\n \t\tstruct ecore_vlan_mac_obj *obj, uint8_t set, int mac_type,\n-\t\tunsigned long *ramrod_flags)\n+\t\tuint32_t *ramrod_flags)\n {\n \tstruct ecore_vlan_mac_ramrod_params ramrod_param;\n \tint rc;\n@@ -6742,11 +6722,12 @@ bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,\n \tramrod_param.ramrod_flags = *ramrod_flags;\n \n \t/* fill a user request section if needed */\n-\tif (!bnx2x_test_bit(RAMROD_CONT, ramrod_flags)) {\n+\tif (!rte_get_bit32_relaxed(RAMROD_CONT, ramrod_flags)) {\n \t\trte_memcpy(ramrod_param.user_req.u.mac.mac, mac,\n \t\t\t\t ETH_ALEN);\n \n-\t\tbnx2x_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags);\n+\t\trte_set_bit32_relaxed(mac_type,\n+\t\t\t\t      &ramrod_param.user_req.vlan_mac_flags);\n \n /* Set the command: ADD or DEL */\n \t\tramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD :\n@@ -6769,11 +6750,11 @@ bnx2x_set_mac_one(struct bnx2x_softc *sc, uint8_t * mac,\n \n static int bnx2x_set_eth_mac(struct bnx2x_softc *sc, uint8_t set)\n {\n-\tunsigned long ramrod_flags = 0;\n+\tuint32_t ramrod_flags = 0;\n \n \tPMD_DRV_LOG(DEBUG, sc, \"Adding Ethernet MAC\");\n \n-\tbnx2x_set_bit(RAMROD_COMP_WAIT, &ramrod_flags);\n+\trte_set_bit32_relaxed(RAMROD_COMP_WAIT, &ramrod_flags);\n \n \t/* Eth MAC is set on RSS leading client (fp[0]) */\n \treturn bnx2x_set_mac_one(sc, sc->link_params.mac_addr,\n@@ -6905,24 +6886,26 @@ bnx2x_fill_report_data(struct bnx2x_softc *sc, struct bnx2x_link_report_data *da\n \n \t/* Link is down */\n \tif (!sc->link_vars.link_up || (sc->flags & BNX2X_MF_FUNC_DIS)) {\n-\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n+\t\trte_set_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN,\n \t\t\t    &data->link_report_flags);\n \t}\n \n \t/* Full DUPLEX */\n \tif (sc->link_vars.duplex == DUPLEX_FULL) {\n-\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,\n+\t\trte_set_bit32_relaxed(BNX2X_LINK_REPORT_FULL_DUPLEX,\n \t\t\t    &data->link_report_flags);\n \t}\n \n \t/* Rx Flow Control is ON */\n \tif (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) {\n-\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_RX_FC_ON, &data->link_report_flags);\n+\t\trte_set_bit32_relaxed(BNX2X_LINK_REPORT_RX_FC_ON,\n+\t\t\t\t&data->link_report_flags);\n \t}\n \n \t/* Tx Flow Control is ON */\n \tif (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) {\n-\t\tbnx2x_set_bit(BNX2X_LINK_REPORT_TX_FC_ON, &data->link_report_flags);\n+\t\trte_set_bit32_relaxed(BNX2X_LINK_REPORT_TX_FC_ON,\n+\t\t\t\t&data->link_report_flags);\n \t}\n }\n \n@@ -6941,14 +6924,14 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc)\n \n \t/* Don't report link down or exactly the same link status twice */\n \tif (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) ||\n-\t    (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n+\t    (rte_get_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN,\n \t\t\t  &sc->last_reported_link.link_report_flags) &&\n-\t     bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n+\t     rte_get_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN,\n \t\t\t  &cur_data.link_report_flags))) {\n \t\treturn;\n \t}\n \n-\tELINK_DEBUG_P2(sc, \"Change in link status : cur_data = %lx, last_reported_link = %lx\",\n+\tELINK_DEBUG_P2(sc, \"Change in link status : cur_data = %x, last_reported_link = %x\",\n \t\t       cur_data.link_report_flags,\n \t\t       sc->last_reported_link.link_report_flags);\n \n@@ -6958,15 +6941,16 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc)\n \t/* report new link params and remember the state for the next time */\n \trte_memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data));\n \n-\tif (bnx2x_test_bit(BNX2X_LINK_REPORT_LINK_DOWN,\n+\tif (rte_get_bit32_relaxed(BNX2X_LINK_REPORT_LINK_DOWN,\n \t\t\t &cur_data.link_report_flags)) {\n \t\tELINK_DEBUG_P0(sc, \"NIC Link is Down\");\n \t} else {\n \t\t__rte_unused const char *duplex;\n \t\t__rte_unused const char *flow;\n \n-\t\tif (bnx2x_test_and_clear_bit(BNX2X_LINK_REPORT_FULL_DUPLEX,\n-\t\t\t\t\t   &cur_data.link_report_flags)) {\n+\t\tif (rte_test_and_clear_bit32_relaxed\n+\t\t\t\t\t(BNX2X_LINK_REPORT_FULL_DUPLEX,\n+\t\t\t\t\t &cur_data.link_report_flags)) {\n \t\t\tduplex = \"full\";\n \t\t\t\tELINK_DEBUG_P0(sc, \"link set to full duplex\");\n \t\t} else {\n@@ -6980,20 +6964,25 @@ static void bnx2x_link_report_locked(struct bnx2x_softc *sc)\n  * enabled.\n  */\n \t\tif (cur_data.link_report_flags) {\n-\t\t\tif (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,\n+\t\t\tif (rte_get_bit32_relaxed\n+\t\t\t\t\t(BNX2X_LINK_REPORT_RX_FC_ON,\n \t\t\t\t\t &cur_data.link_report_flags) &&\n-\t\t\t    bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,\n+\t\t\t    rte_get_bit32_relaxed(BNX2X_LINK_REPORT_TX_FC_ON,\n \t\t\t\t\t &cur_data.link_report_flags)) {\n \t\t\t\tflow = \"ON - receive & transmit\";\n-\t\t\t} else if (bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,\n-\t\t\t\t\t\t&cur_data.link_report_flags) &&\n-\t\t\t\t   !bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,\n+\t\t\t} else if (rte_get_bit32_relaxed\n+\t\t\t\t\t\t(BNX2X_LINK_REPORT_RX_FC_ON,\n+\t\t\t\t\t\t &cur_data.link_report_flags) &&\n+\t\t\t\t   !rte_get_bit32_relaxed\n+\t\t\t\t\t\t(BNX2X_LINK_REPORT_TX_FC_ON,\n \t\t\t\t\t\t &cur_data.link_report_flags)) {\n \t\t\t\tflow = \"ON - receive\";\n-\t\t\t} else if (!bnx2x_test_bit(BNX2X_LINK_REPORT_RX_FC_ON,\n+\t\t\t} else if (!rte_get_bit32_relaxed\n+\t\t\t\t\t\t(BNX2X_LINK_REPORT_RX_FC_ON,\n \t\t\t\t\t\t &cur_data.link_report_flags) &&\n-\t\t\t\t   bnx2x_test_bit(BNX2X_LINK_REPORT_TX_FC_ON,\n-\t\t\t\t\t\t&cur_data.link_report_flags)) {\n+\t\t\t\t   rte_get_bit32_relaxed\n+\t\t\t\t\t\t(BNX2X_LINK_REPORT_TX_FC_ON,\n+\t\t\t\t\t\t &cur_data.link_report_flags)) {\n \t\t\t\tflow = \"ON - transmit\";\n \t\t\t} else {\n \t\t\t\tflow = \"none\";\t/* possible? */\n@@ -7413,7 +7402,7 @@ int bnx2x_nic_load(struct bnx2x_softc *sc)\n \tbnx2x_set_rx_mode(sc);\n \n \t/* wait for all pending SP commands to complete */\n-\tif (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0UL)) {\n+\tif (IS_PF(sc) && !bnx2x_wait_sp_comp(sc, ~0x0U)) {\n \t\tPMD_DRV_LOG(NOTICE, sc, \"Timeout waiting for all SPs to complete!\");\n \t\tbnx2x_periodic_stop(sc);\n \t\tbnx2x_nic_unload(sc, UNLOAD_CLOSE, FALSE);\ndiff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h\nindex 1dbc98197..63be72a5b 100644\n--- a/drivers/net/bnx2x/bnx2x.h\n+++ b/drivers/net/bnx2x/bnx2x.h\n@@ -1000,8 +1000,8 @@ struct bnx2x_sp_objs {\n  * link parameters twice.\n  */\n struct bnx2x_link_report_data {\n-\tuint16_t      line_speed;        /* Effective line speed */\n-\tunsigned long link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */\n+\tuint16_t line_speed;        /* Effective line speed */\n+\tuint32_t link_report_flags; /* BNX2X_LINK_REPORT_XXX flags */\n };\n \n enum {\n@@ -1232,7 +1232,7 @@ struct bnx2x_softc {\n \t/* slow path */\n \tstruct bnx2x_dma      sp_dma;\n \tstruct bnx2x_slowpath *sp;\n-\tunsigned long       sp_state;\n+\tuint32_t\t    sp_state;\n \n \t/* slow path queue */\n \tstruct bnx2x_dma spq_dma;\n@@ -1812,10 +1812,6 @@ static const uint32_t dmae_reg_go_c[] = {\n #define PCI_PM_D0    1\n #define PCI_PM_D3hot 2\n \n-int  bnx2x_test_bit(int nr, volatile unsigned long * addr);\n-void bnx2x_set_bit(unsigned int nr, volatile unsigned long * addr);\n-void bnx2x_clear_bit(int nr, volatile unsigned long * addr);\n-int  bnx2x_test_and_clear_bit(int nr, volatile unsigned long * addr);\n int  bnx2x_cmpxchg(volatile int *addr, int old, int new);\n \n int bnx2x_dma_alloc(struct bnx2x_softc *sc, size_t size,\ndiff --git a/drivers/net/bnx2x/ecore_sp.c b/drivers/net/bnx2x/ecore_sp.c\nindex 00c33a317..61f99c640 100644\n--- a/drivers/net/bnx2x/ecore_sp.c\n+++ b/drivers/net/bnx2x/ecore_sp.c\n@@ -161,7 +161,7 @@ static inline void ecore_exe_queue_reset_pending(struct bnx2x_softc *sc,\n  */\n static int ecore_exe_queue_step(struct bnx2x_softc *sc,\n \t\t\t\tstruct ecore_exe_queue_obj *o,\n-\t\t\t\tunsigned long *ramrod_flags)\n+\t\t\t\tuint32_t *ramrod_flags)\n {\n \tstruct ecore_exeq_elem *elem, spacer;\n \tint cur_len = 0, rc;\n@@ -282,7 +282,7 @@ static void ecore_raw_set_pending(struct ecore_raw_obj *o)\n  *\n  */\n static int ecore_state_wait(struct bnx2x_softc *sc, int state,\n-\t\t\t    unsigned long *pstate)\n+\t\t\t    uint32_t *pstate)\n {\n \t/* can take a while if any port is running */\n \tint cnt = 5000;\n@@ -396,9 +396,9 @@ static void __ecore_vlan_mac_h_exec_pending(struct bnx2x_softc *sc,\n \t\t\t\t\t    struct ecore_vlan_mac_obj *o)\n {\n \tint rc;\n-\tunsigned long ramrod_flags = o->saved_ramrod_flags;\n+\tuint32_t ramrod_flags = o->saved_ramrod_flags;\n \n-\tECORE_MSG(sc, \"vlan_mac_lock execute pending command with ramrod flags %lu\",\n+\tECORE_MSG(sc, \"vlan_mac_lock execute pending command with ramrod flags %u\",\n \t\t  ramrod_flags);\n \to->head_exe_request = FALSE;\n \to->saved_ramrod_flags = 0;\n@@ -425,11 +425,11 @@ static void __ecore_vlan_mac_h_exec_pending(struct bnx2x_softc *sc,\n  */\n static void __ecore_vlan_mac_h_pend(struct bnx2x_softc *sc __rte_unused,\n \t\t\t\t    struct ecore_vlan_mac_obj *o,\n-\t\t\t\t    unsigned long ramrod_flags)\n+\t\t\t\t    uint32_t ramrod_flags)\n {\n \to->head_exe_request = TRUE;\n \to->saved_ramrod_flags = ramrod_flags;\n-\tECORE_MSG(sc, \"Placing pending execution with ramrod flags %lu\",\n+\tECORE_MSG(sc, \"Placing pending execution with ramrod flags %u\",\n \t\t  ramrod_flags);\n }\n \n@@ -804,7 +804,7 @@ static void ecore_set_one_mac_e2(struct bnx2x_softc *sc,\n \tint rule_cnt = rule_idx + 1, cmd = elem->cmd_data.vlan_mac.cmd;\n \tunion eth_classify_rule_cmd *rule_entry = &data->rules[rule_idx];\n \tbool add = (cmd == ECORE_VLAN_MAC_ADD) ? TRUE : FALSE;\n-\tunsigned long *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;\n+\tuint32_t *vlan_mac_flags = &elem->cmd_data.vlan_mac.vlan_mac_flags;\n \tuint8_t *mac = elem->cmd_data.vlan_mac.u.mac.mac;\n \n \t/* Set LLH CAM entry: currently only iSCSI and ETH macs are\n@@ -1326,7 +1326,7 @@ static int ecore_wait_vlan_mac(struct bnx2x_softc *sc,\n \n static int __ecore_vlan_mac_execute_step(struct bnx2x_softc *sc,\n \t\t\t\t\t struct ecore_vlan_mac_obj *o,\n-\t\t\t\t\t unsigned long *ramrod_flags)\n+\t\t\t\t\t uint32_t *ramrod_flags)\n {\n \tint rc = ECORE_SUCCESS;\n \n@@ -1362,7 +1362,7 @@ static int __ecore_vlan_mac_execute_step(struct bnx2x_softc *sc,\n static int ecore_complete_vlan_mac(struct bnx2x_softc *sc,\n \t\t\t\t   struct ecore_vlan_mac_obj *o,\n \t\t\t\t   union event_ring_elem *cqe,\n-\t\t\t\t   unsigned long *ramrod_flags)\n+\t\t\t\t   uint32_t *ramrod_flags)\n {\n \tstruct ecore_raw_obj *r = &o->raw;\n \tint rc;\n@@ -1518,7 +1518,7 @@ static int ecore_vlan_mac_get_registry_elem(struct bnx2x_softc *sc,\n static int ecore_execute_vlan_mac(struct bnx2x_softc *sc,\n \t\t\t\t  union ecore_qable_obj *qo,\n \t\t\t\t  ecore_list_t * exe_chunk,\n-\t\t\t\t  unsigned long *ramrod_flags)\n+\t\t\t\t  uint32_t *ramrod_flags)\n {\n \tstruct ecore_exeq_elem *elem;\n \tstruct ecore_vlan_mac_obj *o = &qo->vlan_mac, *cam_obj;\n@@ -1678,7 +1678,7 @@ int ecore_config_vlan_mac(struct bnx2x_softc *sc,\n {\n \tint rc = ECORE_SUCCESS;\n \tstruct ecore_vlan_mac_obj *o = p->vlan_mac_obj;\n-\tunsigned long *ramrod_flags = &p->ramrod_flags;\n+\tuint32_t *ramrod_flags = &p->ramrod_flags;\n \tint cont = ECORE_TEST_BIT(RAMROD_CONT, ramrod_flags);\n \tstruct ecore_raw_obj *raw = &o->raw;\n \n@@ -1758,8 +1758,8 @@ int ecore_config_vlan_mac(struct bnx2x_softc *sc,\n  */\n static int ecore_vlan_mac_del_all(struct bnx2x_softc *sc,\n \t\t\t\t  struct ecore_vlan_mac_obj *o,\n-\t\t\t\t  unsigned long *vlan_mac_flags,\n-\t\t\t\t  unsigned long *ramrod_flags)\n+\t\t\t\t  uint32_t *vlan_mac_flags,\n+\t\t\t\t  uint32_t *ramrod_flags)\n {\n \tstruct ecore_vlan_mac_registry_elem *pos = NULL;\n \tint rc = 0, read_lock;\n@@ -1836,7 +1836,7 @@ static void ecore_init_raw_obj(struct ecore_raw_obj *raw, uint8_t cl_id,\n \t\t\t       uint32_t cid, uint8_t func_id,\n \t\t\t       void *rdata,\n \t\t\t       ecore_dma_addr_t rdata_mapping, int state,\n-\t\t\t       unsigned long *pstate, ecore_obj_type type)\n+\t\t\t       uint32_t *pstate, ecore_obj_type type)\n {\n \traw->func_id = func_id;\n \traw->cid = cid;\n@@ -1856,7 +1856,7 @@ static void ecore_init_vlan_mac_common(struct ecore_vlan_mac_obj *o,\n \t\t\t\t       uint8_t cl_id, uint32_t cid,\n \t\t\t\t       uint8_t func_id, void *rdata,\n \t\t\t\t       ecore_dma_addr_t rdata_mapping,\n-\t\t\t\t       int state, unsigned long *pstate,\n+\t\t\t\t       int state, uint32_t *pstate,\n \t\t\t\t       ecore_obj_type type,\n \t\t\t\t       struct ecore_credit_pool_obj\n \t\t\t\t       *macs_pool, struct ecore_credit_pool_obj\n@@ -1883,7 +1883,7 @@ void ecore_init_mac_obj(struct bnx2x_softc *sc,\n \t\t\tstruct ecore_vlan_mac_obj *mac_obj,\n \t\t\tuint8_t cl_id, uint32_t cid, uint8_t func_id,\n \t\t\tvoid *rdata, ecore_dma_addr_t rdata_mapping, int state,\n-\t\t\tunsigned long *pstate, ecore_obj_type type,\n+\t\t\tuint32_t *pstate, ecore_obj_type type,\n \t\t\tstruct ecore_credit_pool_obj *macs_pool)\n {\n \tunion ecore_qable_obj *qable_obj = (union ecore_qable_obj *)mac_obj;\n@@ -2034,8 +2034,8 @@ static void ecore_rx_mode_set_rdata_hdr_e2(uint32_t cid, struct eth_classify_hea\n \thdr->rule_cnt = rule_cnt;\n }\n \n-static void ecore_rx_mode_set_cmd_state_e2(unsigned long *accept_flags, struct eth_filter_rules_cmd\n-\t\t\t\t\t   *cmd, int clear_accept_all)\n+static void ecore_rx_mode_set_cmd_state_e2(uint32_t *accept_flags,\n+\t\t\tstruct eth_filter_rules_cmd *cmd, int clear_accept_all)\n {\n \tuint16_t state;\n \n@@ -2157,7 +2157,7 @@ static int ecore_set_rx_mode_e2(struct bnx2x_softc *sc,\n \tecore_rx_mode_set_rdata_hdr_e2(p->cid, &data->header, rule_idx);\n \n \t    ECORE_MSG\n-\t    (sc, \"About to configure %d rules, rx_accept_flags 0x%lx, tx_accept_flags 0x%lx\",\n+\t    (sc, \"About to configure %d rules, rx_accept_flags 0x%x, tx_accept_flags 0x%x\",\n \t     data->header.rule_cnt, p->rx_accept_flags, p->tx_accept_flags);\n \n \t/* No need for an explicit memory barrier here as long we would\n@@ -3132,7 +3132,7 @@ void ecore_init_mcast_obj(struct bnx2x_softc *sc,\n \t\t\t  uint8_t mcast_cl_id, uint32_t mcast_cid,\n \t\t\t  uint8_t func_id, uint8_t engine_id, void *rdata,\n \t\t\t  ecore_dma_addr_t rdata_mapping, int state,\n-\t\t\t  unsigned long *pstate, ecore_obj_type type)\n+\t\t\t  uint32_t *pstate, ecore_obj_type type)\n {\n \tECORE_MEMSET(mcast_obj, 0, sizeof(*mcast_obj));\n \n@@ -3598,7 +3598,7 @@ void ecore_init_rss_config_obj(struct bnx2x_softc *sc __rte_unused,\n \t\t\t       uint8_t cl_id, uint32_t cid, uint8_t func_id,\n \t\t\t       uint8_t engine_id,\n \t\t\t       void *rdata, ecore_dma_addr_t rdata_mapping,\n-\t\t\t       int state, unsigned long *pstate,\n+\t\t\t       int state, uint32_t *pstate,\n \t\t\t       ecore_obj_type type)\n {\n \tecore_init_raw_obj(&rss_obj->raw, cl_id, cid, func_id, rdata,\n@@ -3627,7 +3627,7 @@ int ecore_queue_state_change(struct bnx2x_softc *sc,\n {\n \tstruct ecore_queue_sp_obj *o = params->q_obj;\n \tint rc, pending_bit;\n-\tunsigned long *pending = &o->pending;\n+\tuint32_t *pending = &o->pending;\n \n \t/* Check that the requested transition is legal */\n \trc = o->check_transition(sc, o, params);\n@@ -3638,9 +3638,9 @@ int ecore_queue_state_change(struct bnx2x_softc *sc,\n \t}\n \n \t/* Set \"pending\" bit */\n-\tECORE_MSG(sc, \"pending bit was=%lx\", o->pending);\n+\tECORE_MSG(sc, \"pending bit was=%x\", o->pending);\n \tpending_bit = o->set_pending(o, params);\n-\tECORE_MSG(sc, \"pending bit now=%lx\", o->pending);\n+\tECORE_MSG(sc, \"pending bit now=%x\", o->pending);\n \n \t/* Don't send a command if only driver cleanup was requested */\n \tif (ECORE_TEST_BIT(RAMROD_DRV_CLR_ONLY, &params->ramrod_flags))\n@@ -3704,11 +3704,11 @@ static int ecore_queue_comp_cmd(struct bnx2x_softc *sc __rte_unused,\n \t\t\t\tstruct ecore_queue_sp_obj *o,\n \t\t\t\tenum ecore_queue_cmd cmd)\n {\n-\tunsigned long cur_pending = o->pending;\n+\tuint32_t cur_pending = o->pending;\n \n \tif (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {\n \t\tPMD_DRV_LOG(ERR, sc,\n-\t\t\t    \"Bad MC reply %d for queue %d in state %d pending 0x%lx, next_state %d\",\n+\t\t\t    \"Bad MC reply %d for queue %d in state %d pending 0x%x, next_state %d\",\n \t\t\t    cmd, o->cids[ECORE_PRIMARY_CID_INDEX], o->state,\n \t\t\t    cur_pending, o->next_state);\n \t\treturn ECORE_INVAL;\n@@ -3762,7 +3762,7 @@ static void ecore_q_fill_init_general_data(struct bnx2x_softc *sc __rte_unused,\n \t\t\t\t\t   struct ecore_queue_sp_obj *o,\n \t\t\t\t\t   struct ecore_general_setup_params\n \t\t\t\t\t   *params, struct client_init_general_data\n-\t\t\t\t\t   *gen_data, unsigned long *flags)\n+\t\t\t\t\t   *gen_data, uint32_t *flags)\n {\n \tgen_data->client_id = o->cl_id;\n \n@@ -3794,7 +3794,7 @@ static void ecore_q_fill_init_general_data(struct bnx2x_softc *sc __rte_unused,\n \n static void ecore_q_fill_init_tx_data(struct ecore_txq_setup_params *params,\n \t\t\t\t      struct client_init_tx_data *tx_data,\n-\t\t\t\t      unsigned long *flags)\n+\t\t\t\t      uint32_t *flags)\n {\n \ttx_data->enforce_security_flg =\n \t    ECORE_TEST_BIT(ECORE_Q_FLG_TX_SEC, flags);\n@@ -3840,7 +3840,7 @@ static void ecore_q_fill_init_pause_data(struct rxq_pause_params *params,\n \n static void ecore_q_fill_init_rx_data(struct ecore_rxq_setup_params *params,\n \t\t\t\t      struct client_init_rx_data *rx_data,\n-\t\t\t\t      unsigned long *flags)\n+\t\t\t\t      uint32_t *flags)\n {\n \trx_data->tpa_en = ECORE_TEST_BIT(ECORE_Q_FLG_TPA, flags) *\n \t    CLIENT_INIT_RX_DATA_TPA_EN_IPV4;\n@@ -4421,7 +4421,7 @@ static int ecore_queue_chk_transition(struct bnx2x_softc *sc __rte_unused,\n \t * the previous one.\n \t */\n \tif (o->pending) {\n-\t\tPMD_DRV_LOG(ERR, sc, \"Blocking transition since pending was %lx\",\n+\t\tPMD_DRV_LOG(ERR, sc, \"Blocking transition since pending was %x\",\n \t\t\t    o->pending);\n \t\treturn ECORE_BUSY;\n \t}\n@@ -4630,7 +4630,7 @@ void ecore_init_queue_obj(struct bnx2x_softc *sc,\n \t\t\t  struct ecore_queue_sp_obj *obj,\n \t\t\t  uint8_t cl_id, uint32_t * cids, uint8_t cid_cnt,\n \t\t\t  uint8_t func_id, void *rdata,\n-\t\t\t  ecore_dma_addr_t rdata_mapping, unsigned long type)\n+\t\t\t  ecore_dma_addr_t rdata_mapping, uint32_t type)\n {\n \tECORE_MEMSET(obj, 0, sizeof(*obj));\n \n@@ -4699,11 +4699,11 @@ ecore_func_state_change_comp(struct bnx2x_softc *sc __rte_unused,\n \t\t\t     struct ecore_func_sp_obj *o,\n \t\t\t     enum ecore_func_cmd cmd)\n {\n-\tunsigned long cur_pending = o->pending;\n+\tuint32_t cur_pending = o->pending;\n \n \tif (!ECORE_TEST_AND_CLEAR_BIT(cmd, &cur_pending)) {\n \t\tPMD_DRV_LOG(ERR, sc,\n-\t\t\t    \"Bad MC reply %d for func %d in state %d pending 0x%lx, next_state %d\",\n+\t\t\t    \"Bad MC reply %d for func %d in state %d pending 0x%x, next_state %d\",\n \t\t\t    cmd, ECORE_FUNC_ID(sc), o->state, cur_pending,\n \t\t\t    o->next_state);\n \t\treturn ECORE_INVAL;\n@@ -5311,7 +5311,7 @@ int ecore_func_state_change(struct bnx2x_softc *sc,\n \tstruct ecore_func_sp_obj *o = params->f_obj;\n \tint rc, cnt = 300;\n \tenum ecore_func_cmd cmd = params->cmd;\n-\tunsigned long *pending = &o->pending;\n+\tuint32_t *pending = &o->pending;\n \n \tECORE_MUTEX_LOCK(&o->one_pending_mutex);\n \ndiff --git a/drivers/net/bnx2x/ecore_sp.h b/drivers/net/bnx2x/ecore_sp.h\nindex cc1db377a..7a86ed0ce 100644\n--- a/drivers/net/bnx2x/ecore_sp.h\n+++ b/drivers/net/bnx2x/ecore_sp.h\n@@ -14,6 +14,7 @@\n #ifndef ECORE_SP_H\n #define ECORE_SP_H\n \n+#include <rte_bitops.h>\n #include <rte_byteorder.h>\n \n #if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN\n@@ -73,10 +74,11 @@ typedef rte_spinlock_t ECORE_MUTEX_SPIN;\n #define ECORE_SET_BIT_NA(bit, var)         (*var |= (1 << bit))\n #define ECORE_CLEAR_BIT_NA(bit, var)       (*var &= ~(1 << bit))\n \n-#define ECORE_TEST_BIT(bit, var)           bnx2x_test_bit(bit, var)\n-#define ECORE_SET_BIT(bit, var)            bnx2x_set_bit(bit, var)\n-#define ECORE_CLEAR_BIT(bit, var)          bnx2x_clear_bit(bit, var)\n-#define ECORE_TEST_AND_CLEAR_BIT(bit, var) bnx2x_test_and_clear_bit(bit, var)\n+#define ECORE_TEST_BIT(bit, var)           rte_get_bit32_relaxed(bit, var)\n+#define ECORE_SET_BIT(bit, var)            rte_set_bit32_relaxed(bit, var)\n+#define ECORE_CLEAR_BIT(bit, var)          rte_clear_bit32_relaxed(bit, var)\n+#define ECORE_TEST_AND_CLEAR_BIT(bit, var) \\\n+\trte_test_and_clear_bit32_relaxed(bit, var)\n \n #define atomic_load_acq_int                (int)*\n #define atomic_store_rel_int(a, v)         (*a = v)\n@@ -485,7 +487,7 @@ struct ecore_raw_obj {\n \n \t/* Ramrod state params */\n \tint\t\tstate;   /* \"ramrod is pending\" state bit */\n-\tunsigned long\t*pstate; /* pointer to state buffer */\n+\tuint32_t\t*pstate; /* pointer to state buffer */\n \n \tecore_obj_type\tobj_type;\n \n@@ -538,7 +540,7 @@ struct ecore_vlan_mac_data {\n \t/* used to contain the data related vlan_mac_flags bits from\n \t * ramrod parameters.\n \t */\n-\tunsigned long vlan_mac_flags;\n+\tuint32_t vlan_mac_flags;\n \n \t/* Needed for MOVE command */\n \tstruct ecore_vlan_mac_obj *target_obj;\n@@ -589,7 +591,7 @@ typedef int (*exe_q_optimize)(struct bnx2x_softc *sc,\n typedef int (*exe_q_execute)(struct bnx2x_softc *sc,\n \t\t\t     union ecore_qable_obj *o,\n \t\t\t     ecore_list_t *exe_chunk,\n-\t\t\t     unsigned long *ramrod_flags);\n+\t\t\t     uint32_t *ramrod_flags);\n typedef struct ecore_exeq_elem *\n \t\t\t(*exe_q_get)(struct ecore_exe_queue_obj *o,\n \t\t\t\t     struct ecore_exeq_elem *elem);\n@@ -659,7 +661,7 @@ struct ecore_vlan_mac_registry_elem {\n \tint\t\t\tcam_offset;\n \n \t/* Needed for DEL and RESTORE flows */\n-\tunsigned long\t\tvlan_mac_flags;\n+\tuint32_t\t\tvlan_mac_flags;\n \n \tunion ecore_classification_ramrod_data u;\n };\n@@ -688,7 +690,7 @@ struct ecore_vlan_mac_ramrod_params {\n \tstruct ecore_vlan_mac_obj *vlan_mac_obj;\n \n \t/* General command flags: COMP_WAIT, etc. */\n-\tunsigned long ramrod_flags;\n+\tuint32_t ramrod_flags;\n \n \t/* Command specific configuration request */\n \tstruct ecore_vlan_mac_data user_req;\n@@ -706,7 +708,7 @@ struct ecore_vlan_mac_obj {\n \t */\n \tuint8_t\t\thead_reader; /* Num. of readers accessing head list */\n \tbool\t\thead_exe_request; /* Pending execution request. */\n-\tunsigned long\tsaved_ramrod_flags; /* Ramrods of pending execution */\n+\tuint32_t\tsaved_ramrod_flags; /* Ramrods of pending execution */\n \n \t/* Execution queue interface instance */\n \tstruct ecore_exe_queue_obj\texe_queue;\n@@ -801,8 +803,8 @@ struct ecore_vlan_mac_obj {\n \t */\n \tint (*delete_all)(struct bnx2x_softc *sc,\n \t\t\t  struct ecore_vlan_mac_obj *o,\n-\t\t\t  unsigned long *vlan_mac_flags,\n-\t\t\t  unsigned long *ramrod_flags);\n+\t\t\t  uint32_t *vlan_mac_flags,\n+\t\t\t  uint32_t *ramrod_flags);\n \n \t/**\n \t * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously\n@@ -842,7 +844,7 @@ struct ecore_vlan_mac_obj {\n \t */\n \tint (*complete)(struct bnx2x_softc *sc, struct ecore_vlan_mac_obj *o,\n \t\t\tunion event_ring_elem *cqe,\n-\t\t\tunsigned long *ramrod_flags);\n+\t\t\tuint32_t *ramrod_flags);\n \n \t/**\n \t * Wait for completion of all commands. Don't schedule new ones,\n@@ -883,13 +885,13 @@ enum {\n \n struct ecore_rx_mode_ramrod_params {\n \tstruct ecore_rx_mode_obj *rx_mode_obj;\n-\tunsigned long *pstate;\n+\tuint32_t *pstate;\n \tint state;\n \tuint8_t cl_id;\n \tuint32_t cid;\n \tuint8_t func_id;\n-\tunsigned long ramrod_flags;\n-\tunsigned long rx_mode_flags;\n+\tuint32_t ramrod_flags;\n+\tuint32_t rx_mode_flags;\n \n \t/* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to\n \t * a tstorm_eth_mac_filter_config (e1x).\n@@ -898,10 +900,10 @@ struct ecore_rx_mode_ramrod_params {\n \tecore_dma_addr_t rdata_mapping;\n \n \t/* Rx mode settings */\n-\tunsigned long rx_accept_flags;\n+\tuint32_t rx_accept_flags;\n \n \t/* internal switching settings */\n-\tunsigned long tx_accept_flags;\n+\tuint32_t tx_accept_flags;\n };\n \n struct ecore_rx_mode_obj {\n@@ -928,7 +930,7 @@ struct ecore_mcast_ramrod_params {\n \tstruct ecore_mcast_obj *mcast_obj;\n \n \t/* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */\n-\tunsigned long ramrod_flags;\n+\tuint32_t ramrod_flags;\n \n \tecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */\n \t/** TODO:\n@@ -1144,22 +1146,22 @@ struct ecore_config_rss_params {\n \tstruct ecore_rss_config_obj *rss_obj;\n \n \t/* may have RAMROD_COMP_WAIT set only */\n-\tunsigned long\tramrod_flags;\n+\tuint32_t ramrod_flags;\n \n \t/* ECORE_RSS_X bits */\n-\tunsigned long\trss_flags;\n+\tuint32_t rss_flags;\n \n \t/* Number hash bits to take into an account */\n-\tuint8_t\t\trss_result_mask;\n+\tuint8_t\t rss_result_mask;\n \n \t/* Indirection table */\n-\tuint8_t\t\tind_table[T_ETH_INDIRECTION_TABLE_SIZE];\n+\tuint8_t\t ind_table[T_ETH_INDIRECTION_TABLE_SIZE];\n \n \t/* RSS hash values */\n-\tuint32_t\t\trss_key[10];\n+\tuint32_t rss_key[10];\n \n \t/* valid only if ECORE_RSS_UPDATE_TOE is set */\n-\tuint16_t\t\ttoe_rss_bitmap;\n+\tuint16_t toe_rss_bitmap;\n };\n \n struct ecore_rss_config_obj {\n@@ -1290,17 +1292,17 @@ enum ecore_q_type {\n \n struct ecore_queue_init_params {\n \tstruct {\n-\t\tunsigned long\tflags;\n-\t\tuint16_t\t\thc_rate;\n-\t\tuint8_t\t\tfw_sb_id;\n-\t\tuint8_t\t\tsb_cq_index;\n+\t\tuint32_t flags;\n+\t\tuint16_t hc_rate;\n+\t\tuint8_t\t fw_sb_id;\n+\t\tuint8_t\t sb_cq_index;\n \t} tx;\n \n \tstruct {\n-\t\tunsigned long\tflags;\n-\t\tuint16_t\t\thc_rate;\n-\t\tuint8_t\t\tfw_sb_id;\n-\t\tuint8_t\t\tsb_cq_index;\n+\t\tuint32_t flags;\n+\t\tuint16_t hc_rate;\n+\t\tuint8_t\t fw_sb_id;\n+\t\tuint8_t\t sb_cq_index;\n \t} rx;\n \n \t/* CID context in the host memory */\n@@ -1321,10 +1323,10 @@ struct ecore_queue_cfc_del_params {\n };\n \n struct ecore_queue_update_params {\n-\tunsigned long\tupdate_flags; /* ECORE_Q_UPDATE_XX bits */\n-\tuint16_t\t\tdef_vlan;\n-\tuint16_t\t\tsilent_removal_value;\n-\tuint16_t\t\tsilent_removal_mask;\n+\tuint32_t\tupdate_flags; /* ECORE_Q_UPDATE_XX bits */\n+\tuint16_t\tdef_vlan;\n+\tuint16_t\tsilent_removal_value;\n+\tuint16_t\tsilent_removal_mask;\n /* index within the tx_only cids of this queue object */\n \tuint8_t\t\tcid_index;\n };\n@@ -1422,13 +1424,13 @@ struct ecore_queue_setup_params {\n \tstruct ecore_txq_setup_params txq_params;\n \tstruct ecore_rxq_setup_params rxq_params;\n \tstruct rxq_pause_params pause_params;\n-\tunsigned long flags;\n+\tuint32_t flags;\n };\n \n struct ecore_queue_setup_tx_only_params {\n \tstruct ecore_general_setup_params\tgen_params;\n \tstruct ecore_txq_setup_params\t\ttxq_params;\n-\tunsigned long\t\t\t\tflags;\n+\tuint32_t\t\t\t\tflags;\n \t/* index within the tx_only cids of this queue object */\n \tuint8_t\t\t\t\t\tcid_index;\n };\n@@ -1440,7 +1442,7 @@ struct ecore_queue_state_params {\n \tenum ecore_queue_cmd cmd;\n \n \t/* may have RAMROD_COMP_WAIT set only */\n-\tunsigned long ramrod_flags;\n+\tuint32_t ramrod_flags;\n \n \t/* Params according to the current command */\n \tunion {\n@@ -1478,14 +1480,14 @@ struct ecore_queue_sp_obj {\n \tenum ecore_q_state state, next_state;\n \n \t/* bits from enum ecore_q_type */\n-\tunsigned long\ttype;\n+\tuint32_t\ttype;\n \n \t/* ECORE_Q_CMD_XX bits. This object implements \"one\n \t * pending\" paradigm but for debug and tracing purposes it's\n \t * more convenient to have different bits for different\n \t * commands.\n \t */\n-\tunsigned long\tpending;\n+\tuint32_t\tpending;\n \n \t/* Buffer to use as a ramrod data and its mapping */\n \tvoid\t\t*rdata;\n@@ -1653,7 +1655,7 @@ struct ecore_func_start_params {\n };\n \n struct ecore_func_switch_update_params {\n-\tunsigned long changes; /* ECORE_F_UPDATE_XX bits */\n+\tuint32_t changes; /* ECORE_F_UPDATE_XX bits */\n \tuint16_t vlan;\n \tuint16_t vlan_eth_type;\n \tuint8_t vlan_force_prio;\n@@ -1704,7 +1706,7 @@ struct ecore_func_state_params {\n \tenum ecore_func_cmd cmd;\n \n \t/* may have RAMROD_COMP_WAIT set only */\n-\tunsigned long\tramrod_flags;\n+\tuint32_t ramrod_flags;\n \n \t/* Params according to the current command */\n \tunion {\n@@ -1753,7 +1755,7 @@ struct ecore_func_sp_obj {\n \t * more convenient to have different bits for different\n \t * commands.\n \t */\n-\tunsigned long\t\tpending;\n+\tuint32_t\t\tpending;\n \n \t/* Buffer to use as a ramrod data and its mapping */\n \tvoid\t\t\t*rdata;\n@@ -1821,7 +1823,7 @@ enum ecore_func_state ecore_func_get_state(struct bnx2x_softc *sc,\n void ecore_init_queue_obj(struct bnx2x_softc *sc,\n \t\t\t  struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids,\n \t\t\t  uint8_t cid_cnt, uint8_t func_id, void *rdata,\n-\t\t\t  ecore_dma_addr_t rdata_mapping, unsigned long type);\n+\t\t\t  ecore_dma_addr_t rdata_mapping, uint32_t type);\n \n int ecore_queue_state_change(struct bnx2x_softc *sc,\n \t\t\t     struct ecore_queue_state_params *params);\n@@ -1834,7 +1836,7 @@ void ecore_init_mac_obj(struct bnx2x_softc *sc,\n \t\t\tstruct ecore_vlan_mac_obj *mac_obj,\n \t\t\tuint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata,\n \t\t\tecore_dma_addr_t rdata_mapping, int state,\n-\t\t\tunsigned long *pstate, ecore_obj_type type,\n+\t\t\tuint32_t *pstate, ecore_obj_type type,\n \t\t\tstruct ecore_credit_pool_obj *macs_pool);\n \n void ecore_init_vlan_obj(struct bnx2x_softc *sc,\n@@ -1842,7 +1844,7 @@ void ecore_init_vlan_obj(struct bnx2x_softc *sc,\n \t\t\t uint8_t cl_id, uint32_t cid, uint8_t func_id,\n \t\t\t void *rdata,\n \t\t\t ecore_dma_addr_t rdata_mapping, int state,\n-\t\t\t unsigned long *pstate, ecore_obj_type type,\n+\t\t\t uint32_t *pstate, ecore_obj_type type,\n \t\t\t struct ecore_credit_pool_obj *vlans_pool);\n \n void ecore_init_vlan_mac_obj(struct bnx2x_softc *sc,\n@@ -1850,7 +1852,7 @@ void ecore_init_vlan_mac_obj(struct bnx2x_softc *sc,\n \t\t\t     uint8_t cl_id, uint32_t cid, uint8_t func_id,\n \t\t\t     void *rdata,\n \t\t\t     ecore_dma_addr_t rdata_mapping, int state,\n-\t\t\t     unsigned long *pstate, ecore_obj_type type,\n+\t\t\t     uint32_t *pstate, ecore_obj_type type,\n \t\t\t     struct ecore_credit_pool_obj *macs_pool,\n \t\t\t     struct ecore_credit_pool_obj *vlans_pool);\n \n@@ -1859,7 +1861,7 @@ void ecore_init_vxlan_fltr_obj(struct bnx2x_softc *sc,\n \t\t\t       uint8_t cl_id, uint32_t cid, uint8_t func_id,\n \t\t\t       void *rdata,\n \t\t\t       ecore_dma_addr_t rdata_mapping, int state,\n-\t\t\t       unsigned long *pstate, ecore_obj_type type,\n+\t\t\t       uint32_t *pstate, ecore_obj_type type,\n \t\t\t       struct ecore_credit_pool_obj *macs_pool,\n \t\t\t       struct ecore_credit_pool_obj *vlans_pool);\n \n@@ -1901,7 +1903,7 @@ void ecore_init_mcast_obj(struct bnx2x_softc *sc,\n \t\t\t  struct ecore_mcast_obj *mcast_obj,\n \t\t\t  uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id,\n \t\t\t  uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping,\n-\t\t\t  int state, unsigned long *pstate,\n+\t\t\t  int state, uint32_t *pstate,\n \t\t\t  ecore_obj_type type);\n \n /**\n@@ -1943,7 +1945,7 @@ void ecore_init_rss_config_obj(struct bnx2x_softc *sc,\n \t\t\t       struct ecore_rss_config_obj *rss_obj,\n \t\t\t       uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id,\n \t\t\t       void *rdata, ecore_dma_addr_t rdata_mapping,\n-\t\t\t       int state, unsigned long *pstate,\n+\t\t\t       int state, uint32_t *pstate,\n \t\t\t       ecore_obj_type type);\n \n /**\n",
    "prefixes": [
        "v9",
        "4/6"
    ]
}