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GET /api/patches/71329/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 71329,
    "url": "http://patchwork.dpdk.org/api/patches/71329/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200612032410.20864-6-guinanx.sun@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200612032410.20864-6-guinanx.sun@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200612032410.20864-6-guinanx.sun@intel.com",
    "date": "2020-06-12T03:23:54",
    "name": "[05/21] net/ixgbe/base: added API for NVM update",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "633606e0cc0c8c8f711b65c5ab202fc8eb9492f4",
    "submitter": {
        "id": 1476,
        "url": "http://patchwork.dpdk.org/api/people/1476/?format=api",
        "name": "Guinan Sun",
        "email": "guinanx.sun@intel.com"
    },
    "delegate": {
        "id": 1540,
        "url": "http://patchwork.dpdk.org/api/users/1540/?format=api",
        "username": "qzhan15",
        "first_name": "Qi",
        "last_name": "Zhang",
        "email": "qi.z.zhang@intel.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200612032410.20864-6-guinanx.sun@intel.com/mbox/",
    "series": [
        {
            "id": 10428,
            "url": "http://patchwork.dpdk.org/api/series/10428/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=10428",
            "date": "2020-06-12T03:23:49",
            "name": "update ixgbe base code",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/10428/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/71329/comments/",
    "check": "success",
    "checks": "http://patchwork.dpdk.org/api/patches/71329/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3D570A00BE;\n\tFri, 12 Jun 2020 05:46:49 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 593D41BE88;\n\tFri, 12 Jun 2020 05:46:17 +0200 (CEST)",
            "from mga03.intel.com (mga03.intel.com [134.134.136.65])\n by dpdk.org (Postfix) with ESMTP id A859614581\n for <dev@dpdk.org>; Fri, 12 Jun 2020 05:46:12 +0200 (CEST)",
            "from orsmga002.jf.intel.com ([10.7.209.21])\n by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 11 Jun 2020 20:46:12 -0700",
            "from intel.sh.intel.com ([10.239.255.18])\n by orsmga002.jf.intel.com with ESMTP; 11 Jun 2020 20:46:10 -0700"
        ],
        "IronPort-SDR": [
            "\n PPp8XidL0JeZ2QXPNKCCoHASqbLUjDI8bB6kZDv4DtxlVH34kvroHbra8slNB5rHJ3sB99fEUH\n GFlPJe79gwww==",
            "\n 59lgZdZC4f1r7I1LsNtXPeN3HBELl2eiAXcnBMZRioQOg4U7jkR7Ig5t/XWXS3/hCR64QYqddC\n VlQQ2nJLw4fw=="
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "X-IronPort-AV": "E=Sophos;i=\"5.73,501,1583222400\"; d=\"scan'208\";a=\"289759488\"",
        "From": "Guinan Sun <guinanx.sun@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "Guinan Sun <guinanx.sun@intel.com>,\n Piotr Skajewski <piotrx.skajewski@intel.com>",
        "Date": "Fri, 12 Jun 2020 03:23:54 +0000",
        "Message-Id": "<20200612032410.20864-6-guinanx.sun@intel.com>",
        "X-Mailer": "git-send-email 2.17.1",
        "In-Reply-To": "<20200612032410.20864-1-guinanx.sun@intel.com>",
        "References": "<20200612032410.20864-1-guinanx.sun@intel.com>",
        "Subject": "[dpdk-dev] [PATCH 05/21] net/ixgbe/base: added API for NVM update",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "When Secure Boot is enabled access to the /dev/mem is forbidden\nfor user-space applications and clients are reporting inability\nto use tools in Secure Boot Mode. The way to perform NVM update\nis to use ixgbe driver. Currently 10G Linux Base Driver has API\nwhich allows only EEPROM access. There is a need to extend IOCTL\nAPI to allow NVM and registers access.\n\nSigned-off-by: Piotr Skajewski <piotrx.skajewski@intel.com>\nSigned-off-by: Guinan Sun <guinanx.sun@intel.com>\n---\n drivers/net/ixgbe/base/ixgbe_api.c  | 13 ++++++++++\n drivers/net/ixgbe/base/ixgbe_type.h | 40 +++++++++++++++++++++++++++++\n 2 files changed, 53 insertions(+)",
    "diff": "diff --git a/drivers/net/ixgbe/base/ixgbe_api.c b/drivers/net/ixgbe/base/ixgbe_api.c\nindex 9e4763a64..4d61513ec 100644\n--- a/drivers/net/ixgbe/base/ixgbe_api.c\n+++ b/drivers/net/ixgbe/base/ixgbe_api.c\n@@ -95,6 +95,19 @@ s32 ixgbe_init_shared_code(struct ixgbe_hw *hw)\n \t}\n \thw->mac.max_link_up_time = IXGBE_LINK_UP_TIME;\n \n+#ifdef IXGBE_NVMUPD_SUPPORT\n+\t/* NVM Update features structure initialization */\n+\thw->nvmupd_features.major = IXGBE_NVMUPD_FEATURES_API_VER_MAJOR;\n+\thw->nvmupd_features.minor = IXGBE_NVMUPD_FEATURES_API_VER_MINOR;\n+\thw->nvmupd_features.size = sizeof(hw->nvmupd_features);\n+\tmemset(hw->nvmupd_features.features, 0x0,\n+\t       IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN *\n+\t       sizeof(*hw->nvmupd_features.features));\n+\n+\thw->nvmupd_features.features[0] =\n+\t\tIXGBE_NVMUPD_FEATURE_REGISTER_ACCESS_SUPPORT;\n+#endif /* IXGBE_NVMUPD_SUPPORT */\n+\n \treturn status;\n }\n \ndiff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h\nindex 33ca659cd..c1ee4c680 100644\n--- a/drivers/net/ixgbe/base/ixgbe_type.h\n+++ b/drivers/net/ixgbe/base/ixgbe_type.h\n@@ -169,6 +169,10 @@\n #define IXGBE_FLA_X550EM_x\tIXGBE_FLA\n #define IXGBE_FLA_X550EM_a\t0x15F68\n #define IXGBE_FLA_BY_MAC(_hw)\tIXGBE_BY_MAC((_hw), FLA)\n+#define IXGBE_FLA_FL_SIZE_SHIFT_X540\t17\n+#define IXGBE_FLA_FL_SIZE_SHIFT_X550\t12\n+#define IXGBE_FLA_FL_SIZE_MASK_X540\t(0x7 << IXGBE_FLA_FL_SIZE_SHIFT_X540)\n+#define IXGBE_FLA_FL_SIZE_MASK_X550\t(0x7 << IXGBE_FLA_FL_SIZE_SHIFT_X550)\n \n #define IXGBE_EEMNGCTL\t0x10110\n #define IXGBE_EEMNGDATA\t0x10114\n@@ -1402,6 +1406,7 @@ struct ixgbe_dmac_config {\n #define IXGBE_BARCTRL_FLSIZE\t\t0x0700\n #define IXGBE_BARCTRL_FLSIZE_SHIFT\t8\n #define IXGBE_BARCTRL_CSRSIZE\t\t0x2000\n+#define IXGBE_BARCTRL_CSRSIZE_SHIFT\t13\n \n /* RSCCTL Bit Masks */\n #define IXGBE_RSCCTL_RSCEN\t0x01\n@@ -3905,6 +3910,37 @@ struct ixgbe_hw_stats {\n \tu64 o2bspc;\n };\n \n+#ifdef IXGBE_NVMUPD_SUPPORT\n+/* NVM Update commands */\n+#define IXGBE_NVMUPD_CMD_REG_READ\t0x0000000B\n+#define IXGBE_NVMUPD_CMD_REG_WRITE\t0x0000000C\n+\n+/* NVM Update features API */\n+#define IXGBE_NVMUPD_FEATURES_API_VER_MAJOR\t\t0\n+#define IXGBE_NVMUPD_FEATURES_API_VER_MINOR\t\t0\n+#define IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN\t12\n+#define IXGBE_NVMUPD_EXEC_FEATURES\t\t\t0xe\n+#define IXGBE_NVMUPD_FEATURE_FLAT_NVM_SUPPORT\t\tBIT(0)\n+#define IXGBE_NVMUPD_FEATURE_REGISTER_ACCESS_SUPPORT\tBIT(1)\n+\n+#define IXGBE_NVMUPD_MOD_PNT_MASK\t\t\t0xFF\n+\n+struct ixgbe_nvm_access {\n+\tu32 command;\n+\tu32 config;\n+\tu32 offset;\t/* in bytes */\n+\tu32 data_size;\t/* in bytes */\n+\tu8 data[1];\n+};\n+\n+struct ixgbe_nvm_features {\n+\tu8 major;\n+\tu8 minor;\n+\tu16 size;\n+\tu8 features[IXGBE_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];\n+};\n+\n+#endif\n /* forward declaration */\n struct ixgbe_hw;\n \n@@ -4200,6 +4236,10 @@ struct ixgbe_hw {\n \tbool allow_unsupported_sfp;\n \tbool wol_enabled;\n \tbool need_crosstalk_fix;\n+#ifdef IXGBE_NVMUPD_SUPPORT\n+\t/* NVM Update features */\n+\tstruct ixgbe_nvm_features nvmupd_features;\n+#endif\n };\n \n #define ixgbe_call_func(hw, func, params, error) \\\n",
    "prefixes": [
        "05/21"
    ]
}