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GET /api/patches/73670/?format=api
{ "id": 73670, "url": "http://patchwork.dpdk.org/api/patches/73670/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200710021412.3403562-7-junfeng.guo@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20200710021412.3403562-7-junfeng.guo@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20200710021412.3403562-7-junfeng.guo@intel.com", "date": "2020-07-10T02:14:10", "name": "[v3,6/8] net/ice/base: split capability parse into separate functions", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "33b5777cc8fc6d849fe7307174beba709aff5b64", "submitter": { "id": 1785, "url": "http://patchwork.dpdk.org/api/people/1785/?format=api", "name": "Junfeng Guo", "email": "junfeng.guo@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200710021412.3403562-7-junfeng.guo@intel.com/mbox/", "series": [ { "id": 10935, "url": "http://patchwork.dpdk.org/api/series/10935/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=10935", "date": "2020-07-10T02:14:04", "name": "update base code batch 3", "version": 3, "mbox": "http://patchwork.dpdk.org/series/10935/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/73670/comments/", "check": "fail", "checks": "http://patchwork.dpdk.org/api/patches/73670/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 6C4EEA0526;\n\tFri, 10 Jul 2020 04:18:09 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id DDCFD1DCDF;\n\tFri, 10 Jul 2020 04:17:33 +0200 (CEST)", "from mga07.intel.com (mga07.intel.com [134.134.136.100])\n by dpdk.org (Postfix) with ESMTP id 7DD3C1DC6E;\n Fri, 10 Jul 2020 04:17:22 +0200 (CEST)", "from orsmga006.jf.intel.com ([10.7.209.51])\n by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Jul 2020 19:17:22 -0700", "from dpdk-junfengguo-v3.sh.intel.com ([10.67.119.146])\n by orsmga006.jf.intel.com with ESMTP; 09 Jul 2020 19:17:19 -0700" ], "IronPort-SDR": [ "\n do/d8t9RSmHsVkXk9dxd+B/aYsh9HHNIReqLeByqfL85rTHl5SFqiIfQFbR2r9KTY3rw86TKZ0\n tZpRu1xfU0tA==", "\n oXp8bYaWhDg7+o7kjB778Pc/F0u7NcSsK5zWv64jtUQ8QI+7VGXe20MrIT1TYdvwiNkdr4s2P0\n L2eN2GIRBbiA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9677\"; a=\"213028688\"", "E=Sophos;i=\"5.75,334,1589266800\"; d=\"scan'208\";a=\"213028688\"", "E=Sophos;i=\"5.75,334,1589266800\"; d=\"scan'208\";a=\"284360208\"" ], "X-Amp-Result": "SKIPPED(no attachment in message)", "X-Amp-File-Uploaded": "False", "X-ExtLoop1": "1", "From": "Junfeng Guo <junfeng.guo@intel.com>", "To": "qi.z.zhang@intel.com,\n\tqiming.yang@intel.com", "Cc": "dev@dpdk.org, stable@dpdk.org, ferruh.yigit@intel.com,\n junfeng.guo@intel.com, Jacob Keller <jacob.e.keller@intel.com>,\n Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>", "Date": "Fri, 10 Jul 2020 10:14:10 +0800", "Message-Id": "<20200710021412.3403562-7-junfeng.guo@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20200710021412.3403562-1-junfeng.guo@intel.com>", "References": "<20200701054951.2393-1-qi.z.zhang@intel.com>\n <20200710021412.3403562-1-junfeng.guo@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v3 6/8] net/ice/base: split capability parse into\n\tseparate functions", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Qi Zhang <qi.z.zhang@intel.com>\n\nThe ice_parse_caps function is used to convert the capability block data\ncoming from firmware into a structured format used by other parts of the\ncode.\n\nThe current implementation directly updates the hw->func_caps and\nhw->dev_caps structures. It is directly called from within\nice_aq_discover_caps. This causes the discover_caps function to have the\nside effect of modifying the hw capability structures, which is not\nintuitive.\n\nSplit this function into ice_parse_dev_caps and ice_parse_func_caps.\nThese functions will take a pointer to the dev_caps and func_caps\nrespectively. Also create an ice_parse_common_caps for sharing the\ncapability logic that is common to device and function.\n\nDoing so enables a future refactor to allow reading and parsing\ncapabilities into a local caps structure instead of modifying the\nmembers of the hw structure directly.\n\nSigned-off-by: Jacob Keller <jacob.e.keller@intel.com>\nSigned-off-by: Paul M Stillwell Jr <paul.m.stillwell.jr@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\nAcked-by: Qiming Yang <qiming.yang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 491 ++++++++++++++++++---------\n drivers/net/ice/base/ice_lan_tx_rx.h | 1 -\n 2 files changed, 332 insertions(+), 160 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex 33e29bc0e..6168fb4f0 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -1821,189 +1821,362 @@ static u32 ice_get_num_per_func(struct ice_hw *hw, u32 max)\n }\n \n /**\n- * ice_parse_caps - parse function/device capabilities\n+ * ice_parse_common_caps - parse common device/function capabilities\n * @hw: pointer to the HW struct\n- * @buf: pointer to a buffer containing function/device capability records\n- * @cap_count: number of capability records in the list\n- * @opc: type of capabilities list to parse\n+ * @caps: pointer to common capabilities structure\n+ * @elem: the capability element to parse\n+ * @prefix: message prefix for tracing capabilities\n *\n- * Helper function to parse function(0x000a)/device(0x000b) capabilities list.\n+ * Given a capability element, extract relevant details into the common\n+ * capability structure.\n+ *\n+ * Returns: true if the capability matches one of the common capability ids,\n+ * false otherwise.\n+ */\n+static bool\n+ice_parse_common_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps,\n+\t\t struct ice_aqc_list_caps_elem *elem, const char *prefix)\n+{\n+\tu32 logical_id = LE32_TO_CPU(elem->logical_id);\n+\tu32 phys_id = LE32_TO_CPU(elem->phys_id);\n+\tu32 number = LE32_TO_CPU(elem->number);\n+\tu16 cap = LE16_TO_CPU(elem->cap);\n+\tbool found = true;\n+\n+\tswitch (cap) {\n+\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n+\t\tcaps->valid_functions = number;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: valid_functions (bitmap) = %d\\n\", prefix,\n+\t\t\t caps->valid_functions);\n+\t\tbreak;\n+\tcase ICE_AQC_CAPS_DCB:\n+\t\tcaps->dcb = (number == 1);\n+\t\tcaps->active_tc_bitmap = logical_id;\n+\t\tcaps->maxtc = phys_id;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: dcb = %d\\n\", prefix, caps->dcb);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: active_tc_bitmap = %d\\n\", prefix,\n+\t\t\t caps->active_tc_bitmap);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: maxtc = %d\\n\", prefix, caps->maxtc);\n+\t\tbreak;\n+\tcase ICE_AQC_CAPS_RSS:\n+\t\tcaps->rss_table_size = number;\n+\t\tcaps->rss_table_entry_width = logical_id;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: rss_table_size = %d\\n\", prefix,\n+\t\t\t caps->rss_table_size);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: rss_table_entry_width = %d\\n\", prefix,\n+\t\t\t caps->rss_table_entry_width);\n+\t\tbreak;\n+\tcase ICE_AQC_CAPS_RXQS:\n+\t\tcaps->num_rxq = number;\n+\t\tcaps->rxq_first_id = phys_id;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: num_rxq = %d\\n\", prefix,\n+\t\t\t caps->num_rxq);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: rxq_first_id = %d\\n\", prefix,\n+\t\t\t caps->rxq_first_id);\n+\t\tbreak;\n+\tcase ICE_AQC_CAPS_TXQS:\n+\t\tcaps->num_txq = number;\n+\t\tcaps->txq_first_id = phys_id;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: num_txq = %d\\n\", prefix,\n+\t\t\t caps->num_txq);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: txq_first_id = %d\\n\", prefix,\n+\t\t\t caps->txq_first_id);\n+\t\tbreak;\n+\tcase ICE_AQC_CAPS_MSIX:\n+\t\tcaps->num_msix_vectors = number;\n+\t\tcaps->msix_vector_first_id = phys_id;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: num_msix_vectors = %d\\n\", prefix,\n+\t\t\t caps->num_msix_vectors);\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"%s: msix_vector_first_id = %d\\n\", prefix,\n+\t\t\t caps->msix_vector_first_id);\n+\t\tbreak;\n+\tcase ICE_AQC_CAPS_MAX_MTU:\n+\t\tcaps->max_mtu = number;\n+\t\tice_debug(hw, ICE_DBG_INIT, \"%s: max_mtu = %d\\n\",\n+\t\t\t prefix, caps->max_mtu);\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Not one of the recognized common capabilities */\n+\t\tfound = false;\n+\t}\n+\n+\treturn found;\n+}\n+\n+/**\n+ * ice_recalc_port_limited_caps - Recalculate port limited capabilities\n+ * @hw: pointer to the HW structure\n+ * @caps: pointer to capabilities structure to fix\n+ *\n+ * Re-calculate the capabilities that are dependent on the number of physical\n+ * ports; i.e. some features are not supported or function differently on\n+ * devices with more than 4 ports.\n */\n static void\n-ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n-\t enum ice_adminq_opc opc)\n+ice_recalc_port_limited_caps(struct ice_hw *hw, struct ice_hw_common_caps *caps)\n {\n-\tstruct ice_aqc_list_caps_elem *cap_resp;\n-\tstruct ice_hw_func_caps *func_p = NULL;\n-\tstruct ice_hw_dev_caps *dev_p = NULL;\n-\tstruct ice_hw_common_caps *caps;\n-\tchar const *prefix;\n-\tu32 i;\n+\t/* This assumes device capabilities are always scanned before function\n+\t * capabilities during the initialization flow.\n+\t */\n+\tif (hw->dev_caps.num_funcs > 4) {\n+\t\t/* Max 4 TCs per port */\n+\t\tcaps->maxtc = 4;\n+\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t \"reducing maxtc to %d (based on #ports)\\n\",\n+\t\t\t caps->maxtc);\n+\t}\n+}\n \n-\tif (!buf)\n-\t\treturn;\n+/**\n+ * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @cap: pointer to the capability element to parse\n+ *\n+ * Extract function capabilities for ICE_AQC_CAPS_VSI.\n+ */\n+static void\n+ice_parse_vsi_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,\n+\t\t\tstruct ice_aqc_list_caps_elem *cap)\n+{\n+\tfunc_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI);\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: guar_num_vsi (fw) = %d\\n\",\n+\t\t LE32_TO_CPU(cap->number));\n+\tice_debug(hw, ICE_DBG_INIT, \"func caps: guar_num_vsi = %d\\n\",\n+\t\t func_p->guar_num_vsi);\n+}\n \n-\tcap_resp = (struct ice_aqc_list_caps_elem *)buf;\n+/**\n+ * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @cap: pointer to the capability element to parse\n+ *\n+ * Extract function capabilities for ICE_AQC_CAPS_FD.\n+ */\n+static void\n+ice_parse_fdir_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,\n+\t\t\t struct ice_aqc_list_caps_elem *cap)\n+{\n+\tu32 reg_val, val;\n \n-\tif (opc == ice_aqc_opc_list_dev_caps) {\n-\t\tdev_p = &hw->dev_caps;\n-\t\tcaps = &dev_p->common_cap;\n+\tif (hw->dcf_enabled)\n+\t\treturn;\n+\treg_val = rd32(hw, GLQF_FD_SIZE);\n+\tval = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>\n+\t\tGLQF_FD_SIZE_FD_GSIZE_S;\n+\tfunc_p->fd_fltr_guar =\n+\t\tice_get_num_per_func(hw, val);\n+\tval = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>\n+\t\tGLQF_FD_SIZE_FD_BSIZE_S;\n+\tfunc_p->fd_fltr_best_effort = val;\n+\n+\tice_debug(hw, ICE_DBG_INIT,\n+\t\t \"func caps: fd_fltr_guar = %d\\n\",\n+\t\t func_p->fd_fltr_guar);\n+\tice_debug(hw, ICE_DBG_INIT,\n+\t\t \"func caps: fd_fltr_best_effort = %d\\n\",\n+\t\t func_p->fd_fltr_best_effort);\n+}\n \n-\t\tice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);\n+/**\n+ * ice_parse_func_caps - Parse function capabilities\n+ * @hw: pointer to the HW struct\n+ * @func_p: pointer to function capabilities structure\n+ * @buf: buffer containing the function capability records\n+ * @cap_count: the number of capabilities\n+ *\n+ * Helper function to parse function (0x000A) capabilities list. For\n+ * capabilities shared between device and function, this relies on\n+ * ice_parse_common_caps.\n+ *\n+ * Loop through the list of provided capabilities and extract the relevant\n+ * data into the function capabilities structured.\n+ */\n+static void\n+ice_parse_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,\n+\t\t void *buf, u32 cap_count)\n+{\n+\tstruct ice_aqc_list_caps_elem *cap_resp;\n+\tu32 i;\n \n-\t\tprefix = \"dev cap\";\n-\t} else if (opc == ice_aqc_opc_list_func_caps) {\n-\t\tfunc_p = &hw->func_caps;\n-\t\tcaps = &func_p->common_cap;\n+\tcap_resp = (struct ice_aqc_list_caps_elem *)buf;\n \n-\t\tice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);\n+\tice_memset(func_p, 0, sizeof(*func_p), ICE_NONDMA_MEM);\n \n-\t\tprefix = \"func cap\";\n-\t} else {\n-\t\tice_debug(hw, ICE_DBG_INIT, \"wrong opcode\\n\");\n-\t\treturn;\n-\t}\n+\tfor (i = 0; i < cap_count; i++) {\n+\t\tu16 cap = LE16_TO_CPU(cap_resp[i].cap);\n+\t\tbool found;\n \n-\tfor (i = 0; caps && i < cap_count; i++, cap_resp++) {\n-\t\tu32 logical_id = LE32_TO_CPU(cap_resp->logical_id);\n-\t\tu32 phys_id = LE32_TO_CPU(cap_resp->phys_id);\n-\t\tu32 number = LE32_TO_CPU(cap_resp->number);\n-\t\tu16 cap = LE16_TO_CPU(cap_resp->cap);\n+\t\tfound = ice_parse_common_caps(hw, &func_p->common_cap,\n+\t\t\t\t\t &cap_resp[i], \"func caps\");\n \n \t\tswitch (cap) {\n-\t\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n-\t\t\tcaps->valid_functions = number;\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: valid_functions (bitmap) = %d\\n\", prefix,\n-\t\t\t\t caps->valid_functions);\n-\n-\t\t\t/* store func count for resource management purposes */\n-\t\t\tif (dev_p)\n-\t\t\t\tdev_p->num_funcs = ice_hweight32(number);\n-\t\t\tbreak;\n \t\tcase ICE_AQC_CAPS_VSI:\n-\t\t\tif (dev_p) {\n-\t\t\t\tdev_p->num_vsi_allocd_to_host = number;\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num_vsi_allocd_to_host = %d\\n\",\n-\t\t\t\t\t prefix,\n-\t\t\t\t\t dev_p->num_vsi_allocd_to_host);\n-\t\t\t} else if (func_p) {\n-\t\t\t\tfunc_p->guar_num_vsi =\n-\t\t\t\t\tice_get_num_per_func(hw, ICE_MAX_VSI);\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: guar_num_vsi (fw) = %d\\n\",\n-\t\t\t\t\t prefix, number);\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: guar_num_vsi = %d\\n\",\n-\t\t\t\t\t prefix, func_p->guar_num_vsi);\n-\t\t\t}\n-\t\t\tbreak;\n-\t\tcase ICE_AQC_CAPS_DCB:\n-\t\t\tcaps->dcb = (number == 1);\n-\t\t\tcaps->active_tc_bitmap = logical_id;\n-\t\t\tcaps->maxtc = phys_id;\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: dcb = %d\\n\", prefix, caps->dcb);\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: active_tc_bitmap = %d\\n\", prefix,\n-\t\t\t\t caps->active_tc_bitmap);\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: maxtc = %d\\n\", prefix, caps->maxtc);\n-\t\t\tbreak;\n-\t\tcase ICE_AQC_CAPS_RSS:\n-\t\t\tcaps->rss_table_size = number;\n-\t\t\tcaps->rss_table_entry_width = logical_id;\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: rss_table_size = %d\\n\", prefix,\n-\t\t\t\t caps->rss_table_size);\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: rss_table_entry_width = %d\\n\", prefix,\n-\t\t\t\t caps->rss_table_entry_width);\n+\t\t\tice_parse_vsi_func_caps(hw, func_p, &cap_resp[i]);\n \t\t\tbreak;\n-\t\tcase ICE_AQC_CAPS_RXQS:\n-\t\t\tcaps->num_rxq = number;\n-\t\t\tcaps->rxq_first_id = phys_id;\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: num_rxq = %d\\n\", prefix,\n-\t\t\t\t caps->num_rxq);\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: rxq_first_id = %d\\n\", prefix,\n-\t\t\t\t caps->rxq_first_id);\n+\t\tcase ICE_AQC_CAPS_FD:\n+\t\t\tice_parse_fdir_func_caps(hw, func_p, &cap_resp[i]);\n \t\t\tbreak;\n-\t\tcase ICE_AQC_CAPS_TXQS:\n-\t\t\tcaps->num_txq = number;\n-\t\t\tcaps->txq_first_id = phys_id;\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: num_txq = %d\\n\", prefix,\n-\t\t\t\t caps->num_txq);\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: txq_first_id = %d\\n\", prefix,\n-\t\t\t\t caps->txq_first_id);\n+\t\tdefault:\n+\t\t\t/* Don't list common capabilities as unknown */\n+\t\t\tif (!found)\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t \"func caps: unknown capability[%d]: 0x%x\\n\",\n+\t\t\t\t\t i, cap);\n \t\t\tbreak;\n-\t\tcase ICE_AQC_CAPS_MSIX:\n-\t\t\tcaps->num_msix_vectors = number;\n-\t\t\tcaps->msix_vector_first_id = phys_id;\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: num_msix_vectors = %d\\n\", prefix,\n-\t\t\t\t caps->num_msix_vectors);\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: msix_vector_first_id = %d\\n\", prefix,\n-\t\t\t\t caps->msix_vector_first_id);\n+\t\t}\n+\t}\n+\n+\tice_recalc_port_limited_caps(hw, &func_p->common_cap);\n+}\n+\n+/**\n+ * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse ICE_AQC_CAPS_VALID_FUNCTIONS for device capabilities.\n+ */\n+static void\n+ice_parse_valid_functions_cap(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n+\t\t\t struct ice_aqc_list_caps_elem *cap)\n+{\n+\tu32 number = LE32_TO_CPU(cap->number);\n+\n+\tdev_p->num_funcs = ice_hweight32(number);\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: num_funcs = %d\\n\",\n+\t\t dev_p->num_funcs);\n+}\n+\n+/**\n+ * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse ICE_AQC_CAPS_VSI for device capabilities.\n+ */\n+static void\n+ice_parse_vsi_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n+\t\t struct ice_aqc_list_caps_elem *cap)\n+{\n+\tu32 number = LE32_TO_CPU(cap->number);\n+\n+\tdev_p->num_vsi_allocd_to_host = number;\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: num_vsi_allocd_to_host = %d\\n\",\n+\t\t dev_p->num_vsi_allocd_to_host);\n+}\n+\n+/**\n+ * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @cap: capability element to parse\n+ *\n+ * Parse ICE_AQC_CAPS_FD for device capabilities.\n+ */\n+static void\n+ice_parse_fdir_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n+\t\t\tstruct ice_aqc_list_caps_elem *cap)\n+{\n+\tu32 number = LE32_TO_CPU(cap->number);\n+\n+\tdev_p->num_flow_director_fltr = number;\n+\tice_debug(hw, ICE_DBG_INIT, \"dev caps: num_flow_director_fltr = %d\\n\",\n+\t\t dev_p->num_flow_director_fltr);\n+}\n+\n+/**\n+ * ice_parse_dev_caps - Parse device capabilities\n+ * @hw: pointer to the HW struct\n+ * @dev_p: pointer to device capabilities structure\n+ * @buf: buffer containing the device capability records\n+ * @cap_count: the number of capabilities\n+ *\n+ * Helper device to parse device (0x000B) capabilities list. For\n+ * capabilities shared between device and device, this relies on\n+ * ice_parse_common_caps.\n+ *\n+ * Loop through the list of provided capabilities and extract the relevant\n+ * data into the device capabilities structured.\n+ */\n+static void\n+ice_parse_dev_caps(struct ice_hw *hw, struct ice_hw_dev_caps *dev_p,\n+\t\t void *buf, u32 cap_count)\n+{\n+\tstruct ice_aqc_list_caps_elem *cap_resp;\n+\tu32 i;\n+\n+\tcap_resp = (struct ice_aqc_list_caps_elem *)buf;\n+\n+\tice_memset(dev_p, 0, sizeof(*dev_p), ICE_NONDMA_MEM);\n+\n+\tfor (i = 0; i < cap_count; i++) {\n+\t\tu16 cap = LE16_TO_CPU(cap_resp[i].cap);\n+\t\tbool found;\n+\n+\t\tfound = ice_parse_common_caps(hw, &dev_p->common_cap,\n+\t\t\t\t\t &cap_resp[i], \"dev caps\");\n+\n+\t\tswitch (cap) {\n+\t\tcase ICE_AQC_CAPS_VALID_FUNCTIONS:\n+\t\t\tice_parse_valid_functions_cap(hw, dev_p, &cap_resp[i]);\n \t\t\tbreak;\n-\t\tcase ICE_AQC_CAPS_FD:\n-\t\t\tif (dev_p) {\n-\t\t\t\tdev_p->num_flow_director_fltr = number;\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: num_flow_director_fltr = %d\\n\",\n-\t\t\t\t\t prefix,\n-\t\t\t\t\t dev_p->num_flow_director_fltr);\n-\t\t\t}\n-\t\t\tif (func_p) {\n-\t\t\t\tu32 reg_val, val;\n-\n-\t\t\t\tif (hw->dcf_enabled)\n-\t\t\t\t\tbreak;\n-\t\t\t\treg_val = rd32(hw, GLQF_FD_SIZE);\n-\t\t\t\tval = (reg_val & GLQF_FD_SIZE_FD_GSIZE_M) >>\n-\t\t\t\t GLQF_FD_SIZE_FD_GSIZE_S;\n-\t\t\t\tfunc_p->fd_fltr_guar =\n-\t\t\t\t\tice_get_num_per_func(hw, val);\n-\t\t\t\tval = (reg_val & GLQF_FD_SIZE_FD_BSIZE_M) >>\n-\t\t\t\t GLQF_FD_SIZE_FD_BSIZE_S;\n-\t\t\t\tfunc_p->fd_fltr_best_effort = val;\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: fd_fltr_guar = %d\\n\",\n-\t\t\t\t\t prefix, func_p->fd_fltr_guar);\n-\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t\t \"%s: fd_fltr_best_effort = %d\\n\",\n-\t\t\t\t\t prefix, func_p->fd_fltr_best_effort);\n-\t\t\t}\n+\t\tcase ICE_AQC_CAPS_VSI:\n+\t\t\tice_parse_vsi_dev_caps(hw, dev_p, &cap_resp[i]);\n \t\t\tbreak;\n-\t\tcase ICE_AQC_CAPS_MAX_MTU:\n-\t\t\tcaps->max_mtu = number;\n-\t\t\tice_debug(hw, ICE_DBG_INIT, \"%s: max_mtu = %d\\n\",\n-\t\t\t\t prefix, caps->max_mtu);\n+\t\tcase ICE_AQC_CAPS_FD:\n+\t\t\tice_parse_fdir_dev_caps(hw, dev_p, &cap_resp[i]);\n \t\t\tbreak;\n \t\tdefault:\n-\t\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t\t \"%s: unknown capability[%d]: 0x%x\\n\", prefix,\n-\t\t\t\t i, cap);\n+\t\t\t/* Don't list common capabilities as unknown */\n+\t\t\tif (!found)\n+\t\t\t\tice_debug(hw, ICE_DBG_INIT,\n+\t\t\t\t\t \"dev caps: unknown capability[%d]: 0x%x\\n\",\n+\t\t\t\t\t i, cap);\n \t\t\tbreak;\n \t\t}\n \t}\n \n-\t/* Re-calculate capabilities that are dependent on the number of\n-\t * physical ports; i.e. some features are not supported or function\n-\t * differently on devices with more than 4 ports.\n-\t */\n-\tif (hw->dev_caps.num_funcs > 4) {\n-\t\t/* Max 4 TCs per port */\n-\t\tcaps->maxtc = 4;\n-\t\tice_debug(hw, ICE_DBG_INIT,\n-\t\t\t \"%s: maxtc = %d (based on #ports)\\n\", prefix,\n-\t\t\t caps->maxtc);\n-\t}\n+\tice_recalc_port_limited_caps(hw, &dev_p->common_cap);\n+}\n+\n+/**\n+ * ice_parse_caps - parse function/device capabilities\n+ * @hw: pointer to the HW struct\n+ * @buf: pointer to a buffer containing function/device capability records\n+ * @cap_count: number of capability records in the list\n+ * @opc: type of capabilities list to parse\n+ *\n+ * Helper function to parse function(0x000a)/device(0x000b) capabilities list.\n+ */\n+static void\n+ice_parse_caps(struct ice_hw *hw, void *buf, u32 cap_count,\n+\t enum ice_adminq_opc opc)\n+{\n+\tif (!buf)\n+\t\treturn;\n+\n+\tif (opc == ice_aqc_opc_list_dev_caps)\n+\t\tice_parse_dev_caps(hw, &hw->dev_caps, buf, cap_count);\n+\telse if (opc == ice_aqc_opc_list_func_caps)\n+\t\tice_parse_func_caps(hw, &hw->func_caps, buf, cap_count);\n+\telse\n+\t\tice_debug(hw, ICE_DBG_INIT, \"wrong opcode\\n\");\n }\n \n /**\n@@ -2850,9 +3023,9 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,\n \t\t * bits and OR request bits.\n \t\t */\n \t\tcfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN |\n-\t\t\t\t ICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;\n+\t\t\tICE_AQC_PHY_FEC_25G_KR_CLAUSE74_EN;\n \t\tcfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ |\n-\t\t\t\t ICE_AQC_PHY_FEC_25G_KR_REQ;\n+\t\t\tICE_AQC_PHY_FEC_25G_KR_REQ;\n \t\tbreak;\n \tcase ICE_FEC_RS:\n \t\t/* Clear BASE-R bits, and AND RS ability\n@@ -2860,7 +3033,7 @@ ice_cfg_phy_fec(struct ice_port_info *pi, struct ice_aqc_set_phy_cfg_data *cfg,\n \t\t */\n \t\tcfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN;\n \t\tcfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ |\n-\t\t\t\t ICE_AQC_PHY_FEC_25G_RS_544_REQ;\n+\t\t\tICE_AQC_PHY_FEC_25G_RS_544_REQ;\n \t\tbreak;\n \tcase ICE_FEC_NONE:\n \t\t/* Clear all FEC option bits. */\ndiff --git a/drivers/net/ice/base/ice_lan_tx_rx.h b/drivers/net/ice/base/ice_lan_tx_rx.h\nindex 012d129df..c47114d16 100644\n--- a/drivers/net/ice/base/ice_lan_tx_rx.h\n+++ b/drivers/net/ice/base/ice_lan_tx_rx.h\n@@ -1148,7 +1148,6 @@ struct ice_tx_cmpltnq {\n };\n #pragma pack()\n \n-\n /* LAN Tx Completion Queue Context */\n #pragma pack(1)\n struct ice_tx_cmpltnq_ctx {\n", "prefixes": [ "v3", "6/8" ] }