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{
    "id": 73971,
    "url": "http://patchwork.dpdk.org/api/patches/73971/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20200713165755.61814-3-roy.fan.zhang@intel.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20200713165755.61814-3-roy.fan.zhang@intel.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20200713165755.61814-3-roy.fan.zhang@intel.com",
    "date": "2020-07-13T16:57:53",
    "name": "[v5,2/4] crypto/qat: add support to direct data-path APIs",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "8f6ac1c3540bd8148a0d9f7be9b5f659b2659133",
    "submitter": {
        "id": 304,
        "url": "http://patchwork.dpdk.org/api/people/304/?format=api",
        "name": "Fan Zhang",
        "email": "roy.fan.zhang@intel.com"
    },
    "delegate": {
        "id": 6690,
        "url": "http://patchwork.dpdk.org/api/users/6690/?format=api",
        "username": "akhil",
        "first_name": "akhil",
        "last_name": "goyal",
        "email": "gakhil@marvell.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20200713165755.61814-3-roy.fan.zhang@intel.com/mbox/",
    "series": [
        {
            "id": 11006,
            "url": "http://patchwork.dpdk.org/api/series/11006/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=11006",
            "date": "2020-07-13T16:57:51",
            "name": "cryptodev: add symmetric crypto data-path APIs",
            "version": 5,
            "mbox": "http://patchwork.dpdk.org/series/11006/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/73971/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/73971/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C567DA0540;\n\tMon, 13 Jul 2020 18:58:20 +0200 (CEST)",
            "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id 6AF101D6C1;\n\tMon, 13 Jul 2020 18:58:08 +0200 (CEST)",
            "from mga06.intel.com (mga06.intel.com [134.134.136.31])\n by dpdk.org (Postfix) with ESMTP id ECE001D6AA\n for <dev@dpdk.org>; Mon, 13 Jul 2020 18:58:02 +0200 (CEST)",
            "from orsmga003.jf.intel.com ([10.7.209.27])\n by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 13 Jul 2020 09:58:02 -0700",
            "from silpixa00398673.ir.intel.com (HELO\n silpixa00398673.ger.corp.intel.com) ([10.237.223.136])\n by orsmga003.jf.intel.com with ESMTP; 13 Jul 2020 09:58:00 -0700"
        ],
        "IronPort-SDR": [
            "\n Lycq4P91OsL/RgooZlwmRJQ+rqi0jKjsgec9c/elGVcHP13RGGBHXyaOATXO+fhrnoB1okvPxH\n jPS2G3ZycJjw==",
            "\n nUcLLqSDmWlYZRri+rMc0AiDv2WN3mFpXVyU8qLUEpThYqFKORuWkDb8p/RuZFxq74k28WM8Zo\n Nssgg4EkHFpQ=="
        ],
        "X-IronPort-AV": [
            "E=McAfee;i=\"6000,8403,9681\"; a=\"210203456\"",
            "E=Sophos;i=\"5.75,348,1589266800\"; d=\"scan'208\";a=\"210203456\"",
            "E=Sophos;i=\"5.75,348,1589266800\"; d=\"scan'208\";a=\"281465660\""
        ],
        "X-Amp-Result": "SKIPPED(no attachment in message)",
        "X-Amp-File-Uploaded": "False",
        "X-ExtLoop1": "1",
        "From": "Fan Zhang <roy.fan.zhang@intel.com>",
        "To": "dev@dpdk.org",
        "Cc": "fiona.trahe@intel.com, akhil.goyal@nxp.com,\n Fan Zhang <roy.fan.zhang@intel.com>",
        "Date": "Mon, 13 Jul 2020 17:57:53 +0100",
        "Message-Id": "<20200713165755.61814-3-roy.fan.zhang@intel.com>",
        "X-Mailer": "git-send-email 2.20.1",
        "In-Reply-To": "<20200713165755.61814-1-roy.fan.zhang@intel.com>",
        "References": "<20200703124942.29171-1-roy.fan.zhang@intel.com>\n <20200713165755.61814-1-roy.fan.zhang@intel.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [dpdk-dev v5 2/4] crypto/qat: add support to direct\n\tdata-path APIs",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.15",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
        "List-Post": "<mailto:dev@dpdk.org>",
        "List-Help": "<mailto:dev-request@dpdk.org?subject=help>",
        "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>",
        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "This patch add symmetric crypto data-path APIs support to QAT-SYM PMD.\n\nSigned-off-by: Fan Zhang <roy.fan.zhang@intel.com>\n---\n drivers/common/qat/Makefile        |   1 +\n drivers/common/qat/qat_qp.h        |   1 +\n drivers/crypto/qat/meson.build     |   1 +\n drivers/crypto/qat/qat_sym.h       |   3 +\n drivers/crypto/qat/qat_sym_hw_dp.c | 850 +++++++++++++++++++++++++++++\n drivers/crypto/qat/qat_sym_pmd.c   |   7 +-\n 6 files changed, 861 insertions(+), 2 deletions(-)\n create mode 100644 drivers/crypto/qat/qat_sym_hw_dp.c",
    "diff": "diff --git a/drivers/common/qat/Makefile b/drivers/common/qat/Makefile\nindex 85d420709..1b71bbbab 100644\n--- a/drivers/common/qat/Makefile\n+++ b/drivers/common/qat/Makefile\n@@ -42,6 +42,7 @@ endif\n \tSRCS-y += qat_sym.c\n \tSRCS-y += qat_sym_session.c\n \tSRCS-y += qat_sym_pmd.c\n+\tSRCS-y += qat_sym_hw_dp.c\n \tbuild_qat = yes\n endif\n endif\ndiff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h\nindex 575d69059..ea40f2050 100644\n--- a/drivers/common/qat/qat_qp.h\n+++ b/drivers/common/qat/qat_qp.h\n@@ -79,6 +79,7 @@ struct qat_qp {\n \t/**< qat device this qp is on */\n \tuint32_t enqueued;\n \tuint32_t dequeued __rte_aligned(4);\n+\tuint16_t cached;\n \tuint16_t max_inflights;\n \tuint16_t min_enq_burst_threshold;\n } __rte_cache_aligned;\ndiff --git a/drivers/crypto/qat/meson.build b/drivers/crypto/qat/meson.build\nindex a225f374a..bc90ec44c 100644\n--- a/drivers/crypto/qat/meson.build\n+++ b/drivers/crypto/qat/meson.build\n@@ -15,6 +15,7 @@ if dep.found()\n \tqat_sources += files('qat_sym_pmd.c',\n \t\t\t     'qat_sym.c',\n \t\t\t     'qat_sym_session.c',\n+\t\t\t     'qat_sym_hw_dp.c',\n \t\t\t     'qat_asym_pmd.c',\n \t\t\t     'qat_asym.c')\n \tqat_ext_deps += dep\ndiff --git a/drivers/crypto/qat/qat_sym.h b/drivers/crypto/qat/qat_sym.h\nindex dbca74efb..383e3c3f7 100644\n--- a/drivers/crypto/qat/qat_sym.h\n+++ b/drivers/crypto/qat/qat_sym.h\n@@ -212,11 +212,14 @@ qat_sym_process_response(void **op, uint8_t *resp)\n \t}\n \t*op = (void *)rx_op;\n }\n+\n+extern struct rte_crytodev_sym_hw_dp_ops qat_hw_dp_ops;\n #else\n \n static inline void\n qat_sym_process_response(void **op __rte_unused, uint8_t *resp __rte_unused)\n {\n }\n+\n #endif\n #endif /* _QAT_SYM_H_ */\ndiff --git a/drivers/crypto/qat/qat_sym_hw_dp.c b/drivers/crypto/qat/qat_sym_hw_dp.c\nnew file mode 100644\nindex 000000000..8a946c563\n--- /dev/null\n+++ b/drivers/crypto/qat/qat_sym_hw_dp.c\n@@ -0,0 +1,850 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include <rte_cryptodev_pmd.h>\n+\n+#include \"adf_transport_access_macros.h\"\n+#include \"icp_qat_fw.h\"\n+#include \"icp_qat_fw_la.h\"\n+\n+#include \"qat_sym.h\"\n+#include \"qat_sym_pmd.h\"\n+#include \"qat_sym_session.h\"\n+#include \"qat_qp.h\"\n+\n+static __rte_always_inline int32_t\n+qat_sym_dp_fill_sgl(struct qat_qp *qp, struct icp_qat_fw_la_bulk_req *req,\n+\t\tstruct rte_crypto_sgl *sgl)\n+{\n+\tstruct qat_queue *tx_queue = &qp->tx_q;\n+\tstruct qat_sym_op_cookie *cookie;\n+\tstruct qat_sgl *list;\n+\tuint32_t i;\n+\tuint32_t total_len = 0;\n+\n+\tif (!sgl)\n+\t\treturn -EINVAL;\n+\tif (sgl->num < 2 || sgl->num > QAT_SYM_SGL_MAX_NUMBER || !sgl->vec)\n+\t\treturn -EINVAL;\n+\n+\tICP_QAT_FW_COMN_PTR_TYPE_SET(req->comn_hdr.comn_req_flags,\n+\t\t\tQAT_COMN_PTR_TYPE_SGL);\n+\tcookie = qp->op_cookies[tx_queue->tail >> tx_queue->trailz];\n+\tlist = (struct qat_sgl *)&cookie->qat_sgl_src;\n+\n+\tfor (i = 0; i < sgl->num; i++) {\n+\t\tlist->buffers[i].len = sgl->vec[i].len;\n+\t\tlist->buffers[i].resrvd = 0;\n+\t\tlist->buffers[i].addr = sgl->vec[i].iova;\n+\t\tif (total_len + sgl->vec[i].len > UINT32_MAX) {\n+\t\t\tQAT_DP_LOG(ERR, \"Message too long\");\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t\ttotal_len += sgl->vec[i].len;\n+\t}\n+\n+\tlist->num_bufs = i;\n+\treq->comn_mid.src_data_addr = req->comn_mid.dest_data_addr =\n+\t\t\tcookie->qat_sgl_src_phys_addr;\n+\treq->comn_mid.src_length = req->comn_mid.dst_length = 0;\n+\treturn total_len;\n+}\n+\n+static __rte_always_inline void\n+set_cipher_iv(struct icp_qat_fw_la_cipher_req_params *cipher_param,\n+\t\tstruct rte_crypto_vec *iv, uint32_t iv_len,\n+\t\tstruct icp_qat_fw_la_bulk_req *qat_req)\n+{\n+\t/* copy IV into request if it fits */\n+\tif (iv_len <= sizeof(cipher_param->u.cipher_IV_array))\n+\t\trte_memcpy(cipher_param->u.cipher_IV_array, iv->base, iv_len);\n+\telse {\n+\t\tICP_QAT_FW_LA_CIPH_IV_FLD_FLAG_SET(\n+\t\t\t\tqat_req->comn_hdr.serv_specif_flags,\n+\t\t\t\tICP_QAT_FW_CIPH_IV_64BIT_PTR);\n+\t\tcipher_param->u.s.cipher_IV_ptr = iv->iova;\n+\t}\n+}\n+\n+#define QAT_SYM_DP_IS_RESP_SUCCESS(resp) \\\n+\t(ICP_QAT_FW_COMN_STATUS_FLAG_OK == \\\n+\tICP_QAT_FW_COMN_RESP_CRYPTO_STAT_GET(resp->comn_hdr.comn_status))\n+\n+#define QAT_SYM_DP_IS_VEC_VALID(qp, flag, n) \\\n+\t(((qp)->service_type == QAT_SERVICE_SYMMETRIC) && \\\n+\t(flags & RTE_CRYPTO_HW_DP_FF_SESSIONLESS) == 0 && \\\n+\t(flags & RTE_CRYPTO_HW_DP_FF_SECURITY_SESSION) == 0 && \\\n+\t((qp)->enqueued + (qp)->cached + (n) < qp->nb_descriptors - 1))\n+\n+static __rte_always_inline void\n+qat_sym_dp_update_tx_queue(struct qat_qp *qp, struct qat_queue *tx_queue,\n+\t\tuint32_t tail, uint32_t n, uint32_t flags)\n+{\n+\tif (unlikely((flags & RTE_CRYPTO_HW_DP_FF_KICK_QUEUE) ||\n+\t\t\tqp->cached + n > QAT_CSR_HEAD_WRITE_THRESH)) {\n+\t\tqp->enqueued += n;\n+\t\tqp->stats.enqueued_count += n;\n+\n+\t\ttx_queue->tail = tail;\n+\n+\t\tWRITE_CSR_RING_TAIL(qp->mmap_bar_addr,\n+\t\t\t\ttx_queue->hw_bundle_number,\n+\t\t\t\ttx_queue->hw_queue_number, tx_queue->tail);\n+\t\ttx_queue->csr_tail = tx_queue->tail;\n+\t\tqp->cached = 0;\n+\n+\t\treturn;\n+\t}\n+\n+\tqp->cached += n;\n+}\n+\n+static __rte_always_inline void\n+qat_sym_dp_fill_vec_status(int32_t *sta, int status, uint32_t n)\n+{\n+\tuint32_t i;\n+\n+\tfor (i = 0; i < n; i++)\n+\t\tsta[i] = status;\n+}\n+\n+static __rte_always_inline uint32_t\n+qat_sym_dp_enqueue_aead(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tunion rte_cryptodev_hw_session_ctx session,\n+\tunion rte_crypto_sym_ofs ofs, struct rte_crypto_sym_vec *vec,\n+\tvoid **opaque, uint32_t flags)\n+{\n+\tstruct qat_qp *qp = dev->data->queue_pairs[qp_id];\n+\tstruct rte_cryptodev_sym_session *sess;\n+\tstruct qat_queue *tx_queue;\n+\tstruct qat_sym_session *ctx;\n+\tuint32_t i;\n+\tregister uint32_t tail;\n+\n+\tif (unlikely(QAT_SYM_DP_IS_VEC_VALID(qp, flags, vec->num) == 0)) {\n+\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\tqat_sym_dp_fill_vec_status(vec->status, -1, vec->num);\n+\t\treturn 0;\n+\t}\n+\n+\tsess = session.crypto_sess;\n+\tctx = (struct qat_sym_session *)get_sym_session_private_data(sess,\n+\t\t\tdev->driver_id);\n+\ttx_queue = &qp->tx_q;\n+\ttail = (tx_queue->tail + qp->cached * tx_queue->msg_size) &\n+\t\t\ttx_queue->modulo_mask;\n+\n+\tfor (i = 0; i < vec->num; i++) {\n+\t\tstruct icp_qat_fw_la_bulk_req *req;\n+\t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n+\t\tstruct icp_qat_fw_la_auth_req_params *auth_param;\n+\t\tstruct rte_crypto_sgl *sgl = &vec->sgl[i];\n+\t\tstruct rte_crypto_vec *iv_vec = &vec->iv_vec[i];\n+\t\tstruct rte_crypto_vec *aad_vec = &vec->aad_vec[i];\n+\t\tstruct rte_crypto_vec *digest_vec = &vec->digest_vec[i];\n+\t\tuint8_t *aad_data;\n+\t\tuint8_t aad_ccm_real_len;\n+\t\tuint8_t aad_len_field_sz;\n+\t\tuint32_t aead_len, msg_len_be;\n+\t\trte_iova_t aad_iova = 0;\n+\t\tuint8_t q;\n+\n+\t\treq  = (struct icp_qat_fw_la_bulk_req *)(\n+\t\t\t(uint8_t *)tx_queue->base_addr + tail);\n+\t\trte_mov128((uint8_t *)req,\n+\t\t\t(const uint8_t *)&(ctx->fw_req));\n+\n+\t\tif (i == 0 || (flags & RTE_CRYPTO_HW_DP_FF_SET_OPAQUE_ARRAY))\n+\t\t\treq->comn_mid.opaque_data = (uint64_t)opaque[i];\n+\n+\t\tcipher_param = (void *)&req->serv_specif_rqpars;\n+\t\tauth_param = (void *)((uint8_t *)cipher_param +\n+\t\t\t\tICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);\n+\t\treq->comn_mid.src_data_addr = req->comn_mid.dest_data_addr =\n+\t\t\tsgl->vec[0].iova;\n+\t\treq->comn_mid.src_length = req->comn_mid.dst_length =\n+\t\t\tsgl->vec[0].len;\n+\n+\t\taead_len = sgl->vec[0].len - ofs.ofs.cipher.head -\n+\t\t\t\tofs.ofs.cipher.tail;\n+\n+\t\tswitch (ctx->qat_hash_alg) {\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n+\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(\n+\t\t\t\treq->comn_hdr.serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n+\t\t\trte_memcpy_generic(cipher_param->u.cipher_IV_array,\n+\t\t\t\t\tiv_vec->base, ctx->cipher_iv.length);\n+\t\t\taad_iova = aad_vec->iova;\n+\t\t\tbreak;\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_AES_CBC_MAC:\n+\t\t\taad_data = aad_vec->base;\n+\t\t\taad_iova = aad_vec->iova;\n+\t\t\taad_ccm_real_len = 0;\n+\t\t\taad_len_field_sz = 0;\n+\t\t\tmsg_len_be = rte_bswap32(aead_len);\n+\n+\t\t\tif (ctx->aad_len > ICP_QAT_HW_CCM_AAD_DATA_OFFSET) {\n+\t\t\t\taad_len_field_sz = ICP_QAT_HW_CCM_AAD_LEN_INFO;\n+\t\t\t\taad_ccm_real_len = ctx->aad_len -\n+\t\t\t\t\tICP_QAT_HW_CCM_AAD_B0_LEN -\n+\t\t\t\t\tICP_QAT_HW_CCM_AAD_LEN_INFO;\n+\t\t\t} else {\n+\t\t\t\taad_data = iv_vec->base;\n+\t\t\t\taad_iova = iv_vec->iova;\n+\t\t\t}\n+\n+\t\t\tq = ICP_QAT_HW_CCM_NQ_CONST - ctx->cipher_iv.length;\n+\t\t\taad_data[0] = ICP_QAT_HW_CCM_BUILD_B0_FLAGS(\n+\t\t\t\taad_len_field_sz, ctx->digest_length, q);\n+\t\t\tif (q > ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE) {\n+\t\t\t\tmemcpy(aad_data\t+ ctx->cipher_iv.length +\n+\t\t\t\t\tICP_QAT_HW_CCM_NONCE_OFFSET + (q -\n+\t\t\t\t\tICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE),\n+\t\t\t\t\t(uint8_t *)&msg_len_be,\n+\t\t\t\t\tICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE);\n+\t\t\t} else {\n+\t\t\t\tmemcpy(aad_data\t+ ctx->cipher_iv.length +\n+\t\t\t\t\tICP_QAT_HW_CCM_NONCE_OFFSET,\n+\t\t\t\t\t(uint8_t *)&msg_len_be +\n+\t\t\t\t\t(ICP_QAT_HW_CCM_MSG_LEN_MAX_FIELD_SIZE\n+\t\t\t\t\t- q), q);\n+\t\t\t}\n+\n+\t\t\tif (aad_len_field_sz > 0) {\n+\t\t\t\t*(uint16_t *)\n+\t\t\t\t\t&aad_data[ICP_QAT_HW_CCM_AAD_B0_LEN] =\n+\t\t\t\t\t\trte_bswap16(aad_ccm_real_len);\n+\n+\t\t\t\tif ((aad_ccm_real_len + aad_len_field_sz)\n+\t\t\t\t\t% ICP_QAT_HW_CCM_AAD_B0_LEN) {\n+\t\t\t\t\tuint8_t pad_len = 0;\n+\t\t\t\t\tuint8_t pad_idx = 0;\n+\n+\t\t\t\t\tpad_len = ICP_QAT_HW_CCM_AAD_B0_LEN -\n+\t\t\t\t\t\t((aad_ccm_real_len +\n+\t\t\t\t\t\taad_len_field_sz) %\n+\t\t\t\t\t\tICP_QAT_HW_CCM_AAD_B0_LEN);\n+\t\t\t\t\tpad_idx = ICP_QAT_HW_CCM_AAD_B0_LEN +\n+\t\t\t\t\t\taad_ccm_real_len +\n+\t\t\t\t\t\taad_len_field_sz;\n+\t\t\t\t\tmemset(&aad_data[pad_idx], 0, pad_len);\n+\t\t\t\t}\n+\n+\t\t\t\trte_memcpy(((uint8_t *)cipher_param->\n+\t\t\t\t\tu.cipher_IV_array) +\n+\t\t\t\t\tICP_QAT_HW_CCM_NONCE_OFFSET,\n+\t\t\t\t\t(uint8_t *)iv_vec->base +\n+\t\t\t\t\tICP_QAT_HW_CCM_NONCE_OFFSET,\n+\t\t\t\t\tctx->cipher_iv.length);\n+\t\t\t\t*(uint8_t *)&cipher_param->\n+\t\t\t\t\tu.cipher_IV_array[0] =\n+\t\t\t\t\tq - ICP_QAT_HW_CCM_NONCE_OFFSET;\n+\n+\t\t\t\trte_memcpy((uint8_t *)aad_vec->base +\n+\t\t\t\t\tICP_QAT_HW_CCM_NONCE_OFFSET,\n+\t\t\t\t\t(uint8_t *)iv_vec->base +\n+\t\t\t\t\tICP_QAT_HW_CCM_NONCE_OFFSET,\n+\t\t\t\t\tctx->cipher_iv.length);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tif (flags & RTE_CRYPTO_HW_DP_FF_ENQUEUE_EXHAUST)\n+\t\t\t\tbreak;\n+\t\t\t/* Give up enqueue if exhaust enqueue is not set */\n+\t\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\t\tqat_sym_dp_fill_vec_status(vec->status, -1, vec->num);\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n+\t\tcipher_param->cipher_length = aead_len;\n+\t\tauth_param->auth_off = ofs.ofs.cipher.head;\n+\t\tauth_param->auth_len = aead_len;\n+\t\tauth_param->auth_res_addr = digest_vec->iova;\n+\t\tauth_param->u1.aad_adr = aad_iova;\n+\n+\t\t/* SGL processing */\n+\t\tif (unlikely(sgl->num > 1)) {\n+\t\t\tint total_len = qat_sym_dp_fill_sgl(qp, req, sgl);\n+\n+\t\t\tif (total_len < 0) {\n+\t\t\t\tif (flags & RTE_CRYPTO_HW_DP_FF_ENQUEUE_EXHAUST)\n+\t\t\t\t\tbreak;\n+\t\t\t\t/* Give up enqueue if exhaust is not set */\n+\t\t\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\t\t\tqat_sym_dp_fill_vec_status(vec->status, -1,\n+\t\t\t\t\t\tvec->num);\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\n+\t\t\tcipher_param->cipher_length = auth_param->auth_len =\n+\t\t\t\ttotal_len - ofs.ofs.cipher.head -\n+\t\t\t\tofs.ofs.cipher.tail;\n+\t\t}\n+\n+\t\tif (ctx->is_single_pass) {\n+\t\t\tcipher_param->spc_aad_addr = aad_iova;\n+\t\t\tcipher_param->spc_auth_res_addr = digest_vec->iova;\n+\t\t}\n+\n+\t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\n+\n+\n+\t}\n+\n+\tif (unlikely(i < vec->num))\n+\t\tqat_sym_dp_fill_vec_status(vec->status + i, -1, vec->num - i);\n+\n+\tqat_sym_dp_update_tx_queue(qp, tx_queue, tail, i, flags);\n+\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+qat_sym_dp_enqueue_cipher(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tunion rte_cryptodev_hw_session_ctx session,\n+\tunion rte_crypto_sym_ofs ofs, struct rte_crypto_sym_vec *vec,\n+\tvoid **opaque, uint32_t flags)\n+{\n+\tstruct qat_qp *qp = dev->data->queue_pairs[qp_id];\n+\tstruct rte_cryptodev_sym_session *sess;\n+\tstruct qat_queue *tx_queue;\n+\tstruct qat_sym_session *ctx;\n+\tuint32_t i;\n+\tregister uint32_t tail;\n+\n+\tif (unlikely(QAT_SYM_DP_IS_VEC_VALID(qp, flags, vec->num) == 0)) {\n+\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\tqat_sym_dp_fill_vec_status(vec->status, -1, vec->num);\n+\t\treturn 0;\n+\t}\n+\n+\tsess = session.crypto_sess;\n+\n+\tctx = (struct qat_sym_session *)get_sym_session_private_data(sess,\n+\t\t\tdev->driver_id);\n+\n+\ttx_queue = &qp->tx_q;\n+\ttail = (tx_queue->tail + qp->cached * tx_queue->msg_size) &\n+\t\t\ttx_queue->modulo_mask;\n+\n+\tfor (i = 0; i < vec->num; i++) {\n+\t\tstruct icp_qat_fw_la_bulk_req *req;\n+\t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n+\t\tstruct rte_crypto_sgl *sgl = &vec->sgl[i];\n+\t\tstruct rte_crypto_vec *iv_vec = &vec->iv_vec[i];\n+\n+\t\treq  = (struct icp_qat_fw_la_bulk_req *)(\n+\t\t\t(uint8_t *)tx_queue->base_addr + tail);\n+\t\trte_mov128((uint8_t *)req,\n+\t\t\t(const uint8_t *)&(ctx->fw_req));\n+\n+\t\tif (i == 0 || (flags & RTE_CRYPTO_HW_DP_FF_SET_OPAQUE_ARRAY))\n+\t\t\treq->comn_mid.opaque_data = (uint64_t)opaque[i];\n+\n+\t\tcipher_param = (void *)&req->serv_specif_rqpars;\n+\n+\t\treq->comn_mid.src_data_addr = req->comn_mid.dest_data_addr =\n+\t\t\tsgl->vec[0].iova;\n+\t\treq->comn_mid.src_length = req->comn_mid.dst_length =\n+\t\t\tsgl->vec[0].len;\n+\n+\t\t/* cipher IV */\n+\t\tset_cipher_iv(cipher_param, iv_vec, ctx->cipher_iv.length, req);\n+\t\tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n+\t\tcipher_param->cipher_length = sgl->vec[0].len -\n+\t\t\t\tofs.ofs.cipher.head - ofs.ofs.cipher.tail;\n+\n+\t\t/* SGL processing */\n+\t\tif (unlikely(sgl->num > 1)) {\n+\t\t\tint total_len = qat_sym_dp_fill_sgl(qp, req, sgl);\n+\n+\t\t\tif (total_len < 0) {\n+\t\t\t\tif (flags & RTE_CRYPTO_HW_DP_FF_ENQUEUE_EXHAUST)\n+\t\t\t\t\tbreak;\n+\t\t\t\t/* Give up enqueue if exhaust is not set */\n+\t\t\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\t\t\tqat_sym_dp_fill_vec_status(vec->status, -1,\n+\t\t\t\t\t\tvec->num);\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\n+\t\t\tcipher_param->cipher_length = total_len -\n+\t\t\t\tofs.ofs.cipher.head - ofs.ofs.cipher.tail;\n+\t\t}\n+\n+\t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\n+\n+\t}\n+\n+\tqat_sym_dp_update_tx_queue(qp, tx_queue, tail, i, flags);\n+\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+qat_sym_dp_enqueue_auth(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tunion rte_cryptodev_hw_session_ctx session,\n+\tunion rte_crypto_sym_ofs ofs, struct rte_crypto_sym_vec *vec,\n+\tvoid **opaque, uint32_t flags)\n+{\n+\tstruct qat_qp *qp = dev->data->queue_pairs[qp_id];\n+\tstruct rte_cryptodev_sym_session *sess;\n+\tstruct qat_queue *tx_queue;\n+\tstruct qat_sym_session *ctx;\n+\tuint32_t i;\n+\tregister uint32_t tail;\n+\n+\tif (unlikely(QAT_SYM_DP_IS_VEC_VALID(qp, flags, vec->num) == 0)) {\n+\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\tqat_sym_dp_fill_vec_status(vec->status, -1, vec->num);\n+\t\treturn 0;\n+\t}\n+\n+\tsess = session.crypto_sess;\n+\n+\tctx = (struct qat_sym_session *)get_sym_session_private_data(sess,\n+\t\t\tdev->driver_id);\n+\n+\ttx_queue = &qp->tx_q;\n+\ttail = (tx_queue->tail + qp->cached * tx_queue->msg_size) &\n+\t\t\ttx_queue->modulo_mask;\n+\n+\tfor (i = 0; i < vec->num; i++) {\n+\t\tstruct icp_qat_fw_la_bulk_req *req;\n+\t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n+\t\tstruct icp_qat_fw_la_auth_req_params *auth_param;\n+\t\tstruct rte_crypto_sgl *sgl = &vec->sgl[i];\n+\t\tstruct rte_crypto_vec *iv_vec = &vec->iv_vec[i];\n+\t\tstruct rte_crypto_vec *digest_vec = &vec->digest_vec[i];\n+\t\tint total_len;\n+\n+\t\treq  = (struct icp_qat_fw_la_bulk_req *)(\n+\t\t\t(uint8_t *)tx_queue->base_addr + tail);\n+\t\trte_mov128((uint8_t *)req,\n+\t\t\t(const uint8_t *)&(ctx->fw_req));\n+\n+\t\tif (i == 0 || (flags & RTE_CRYPTO_HW_DP_FF_SET_OPAQUE_ARRAY))\n+\t\t\treq->comn_mid.opaque_data = (uint64_t)opaque[i];\n+\n+\t\tcipher_param = (void *)&req->serv_specif_rqpars;\n+\t\tauth_param = (void *)((uint8_t *)cipher_param +\n+\t\t\t\tICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);\n+\t\treq->comn_mid.src_data_addr = req->comn_mid.dest_data_addr =\n+\t\t\tsgl->vec[0].iova;\n+\t\treq->comn_mid.src_length = req->comn_mid.dst_length =\n+\t\t\tsgl->vec[0].len;\n+\n+\t\tauth_param->auth_off = ofs.ofs.auth.head;\n+\t\tauth_param->auth_len = sgl->vec[0].len - ofs.ofs.auth.head -\n+\t\t\t\tofs.ofs.auth.tail;\n+\t\tauth_param->auth_res_addr = digest_vec->iova;\n+\n+\t\tswitch (ctx->qat_hash_alg) {\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:\n+\t\t\tauth_param->u1.aad_adr = iv_vec->iova;\n+\t\t\tbreak;\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n+\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_FLAG_SET(\n+\t\t\t\treq->comn_hdr.serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_GCM_IV_LEN_12_OCTETS);\n+\t\t\trte_memcpy_generic(cipher_param->u.cipher_IV_array,\n+\t\t\t\t\tiv_vec->base, ctx->cipher_iv.length);\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\t/* SGL processing */\n+\t\tif (unlikely(sgl->num > 1)) {\n+\t\t\ttotal_len = qat_sym_dp_fill_sgl(qp, req, sgl);\n+\n+\t\t\tif (total_len < 0) {\n+\t\t\t\tif (flags & RTE_CRYPTO_HW_DP_FF_ENQUEUE_EXHAUST)\n+\t\t\t\t\tbreak;\n+\t\t\t\t/* Give up enqueue if exhaust is not set */\n+\t\t\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\t\t\tqat_sym_dp_fill_vec_status(vec->status, -1,\n+\t\t\t\t\t\tvec->num);\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\n+\t\t\tcipher_param->cipher_length = auth_param->auth_len =\n+\t\t\t\ttotal_len - ofs.ofs.cipher.head -\n+\t\t\t\tofs.ofs.cipher.tail;\n+\t\t}\n+\n+\t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\n+\t}\n+\n+\tif (unlikely(i < vec->num))\n+\t\tqat_sym_dp_fill_vec_status(vec->status + i, -1, vec->num - i);\n+\n+\tqat_sym_dp_update_tx_queue(qp, tx_queue, tail, i, flags);\n+\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+qat_sym_dp_enqueue_chain(struct rte_cryptodev *dev, uint16_t qp_id,\n+\tunion rte_cryptodev_hw_session_ctx session,\n+\tunion rte_crypto_sym_ofs ofs, struct rte_crypto_sym_vec *vec,\n+\tvoid **opaque, uint32_t flags)\n+{\n+\tstruct qat_qp *qp = dev->data->queue_pairs[qp_id];\n+\tstruct rte_cryptodev_sym_session *sess;\n+\tstruct qat_queue *tx_queue;\n+\tstruct qat_sym_session *ctx;\n+\tuint32_t i;\n+\tregister uint32_t tail;\n+\n+\tif (unlikely(QAT_SYM_DP_IS_VEC_VALID(qp, flags, vec->num) == 0)) {\n+\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\tqat_sym_dp_fill_vec_status(vec->status, -1, vec->num);\n+\t\treturn 0;\n+\t}\n+\n+\tsess = session.crypto_sess;\n+\n+\tctx = (struct qat_sym_session *)get_sym_session_private_data(sess,\n+\t\t\tdev->driver_id);\n+\n+\ttx_queue = &qp->tx_q;\n+\ttail = (tx_queue->tail + qp->cached * tx_queue->msg_size) &\n+\t\t\ttx_queue->modulo_mask;\n+\n+\tfor (i = 0; i < vec->num; i++) {\n+\t\tstruct icp_qat_fw_la_bulk_req *req;\n+\t\tstruct icp_qat_fw_la_cipher_req_params *cipher_param;\n+\t\tstruct icp_qat_fw_la_auth_req_params *auth_param;\n+\t\tstruct rte_crypto_sgl *sgl = &vec->sgl[i];\n+\t\tstruct rte_crypto_vec *iv_vec = &vec->iv_vec[i];\n+\t\tstruct rte_crypto_vec *digest_vec = &vec->digest_vec[i];\n+\t\trte_iova_t auth_iova_end;\n+\t\tint total_len;\n+\n+\t\treq  = (struct icp_qat_fw_la_bulk_req *)(\n+\t\t\t(uint8_t *)tx_queue->base_addr + tail);\n+\t\trte_mov128((uint8_t *)req,\n+\t\t\t(const uint8_t *)&(ctx->fw_req));\n+\n+\t\tif (i == 0 || (flags & RTE_CRYPTO_HW_DP_FF_SET_OPAQUE_ARRAY))\n+\t\t\treq->comn_mid.opaque_data = (uint64_t)opaque[i];\n+\n+\t\tcipher_param = (void *)&req->serv_specif_rqpars;\n+\t\tauth_param = (void *)((uint8_t *)cipher_param +\n+\t\t\t\tICP_QAT_FW_HASH_REQUEST_PARAMETERS_OFFSET);\n+\t\treq->comn_mid.src_data_addr = req->comn_mid.dest_data_addr =\n+\t\t\tsgl->vec[0].iova;\n+\t\treq->comn_mid.src_length = req->comn_mid.dst_length =\n+\t\t\tsgl->vec[0].len;\n+\n+\t\tcipher_param->cipher_offset = ofs.ofs.cipher.head;\n+\t\tcipher_param->cipher_length = sgl->vec[0].len -\n+\t\t\t\tofs.ofs.cipher.head - ofs.ofs.cipher.tail;\n+\t\tset_cipher_iv(cipher_param, iv_vec, ctx->cipher_iv.length, req);\n+\n+\t\tauth_param->auth_off = ofs.ofs.cipher.head;\n+\t\tauth_param->auth_len = sgl->vec[0].len -\n+\t\t\t\tofs.ofs.auth.head - ofs.ofs.auth.tail;\n+\t\tauth_param->auth_res_addr = digest_vec->iova;\n+\n+\t\t/* SGL processing */\n+\t\tif (unlikely(sgl->num > 1)) {\n+\t\t\ttotal_len = qat_sym_dp_fill_sgl(qp, req, sgl);\n+\n+\t\t\tif (total_len < 0) {\n+\t\t\t\tif (flags & RTE_CRYPTO_HW_DP_FF_ENQUEUE_EXHAUST)\n+\t\t\t\t\tbreak;\n+\t\t\t\t/* Give up enqueue if exhaust is not set */\n+\t\t\t\tQAT_DP_LOG(ERR, \"Operation not supported\");\n+\t\t\t\tqat_sym_dp_fill_vec_status(vec->status, -1,\n+\t\t\t\t\t\tvec->num);\n+\t\t\t\treturn 0;\n+\t\t\t}\n+\n+\t\t\tcipher_param->cipher_length = auth_param->auth_len =\n+\t\t\t\ttotal_len - ofs.ofs.cipher.head -\n+\t\t\t\tofs.ofs.cipher.tail;\n+\t\t}\n+\n+\t\tswitch (ctx->qat_hash_alg) {\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_SNOW_3G_UIA2:\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_KASUMI_F9:\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_ZUC_3G_128_EIA3:\n+\t\t\tauth_param->u1.aad_adr = iv_vec->iova;\n+\n+\t\t\tif (unlikely(sgl->num > 1)) {\n+\t\t\t\tint auth_end_get = 0, i = sgl->num - 1;\n+\t\t\t\tstruct rte_crypto_vec *cvec = &sgl->vec[i];\n+\t\t\t\tuint32_t len;\n+\n+\t\t\t\tif (total_len - ofs.ofs.auth.tail < 0) {\n+\t\t\t\t\tif (flags &\n+\t\t\t\t\tRTE_CRYPTO_HW_DP_FF_ENQUEUE_EXHAUST)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t/* Give up enqueue if exhaust not set */\n+\t\t\t\t\tQAT_DP_LOG(ERR, \"Incorrect length\");\n+\t\t\t\t\tqat_sym_dp_fill_vec_status(vec->status,\n+\t\t\t\t\t\t-1, vec->num);\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\n+\t\t\t\tlen = total_len - ofs.ofs.auth.tail;\n+\n+\t\t\t\twhile (i >= 0 && len > 0) {\n+\t\t\t\t\tif (cvec->len >= len) {\n+\t\t\t\t\t\tauth_iova_end = cvec->iova +\n+\t\t\t\t\t\t\t(cvec->len - len);\n+\t\t\t\t\t\tlen = 0;\n+\t\t\t\t\t\tauth_end_get = 1;\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t}\n+\t\t\t\t\tlen -= cvec->len;\n+\t\t\t\t\ti--;\n+\t\t\t\t\tvec--;\n+\t\t\t\t}\n+\n+\t\t\t\tif (!auth_end_get) {\n+\t\t\t\t\tQAT_DP_LOG(ERR, \"Failed to get end\");\n+\t\t\t\t\tif (flags &\n+\t\t\t\t\tRTE_CRYPTO_HW_DP_FF_ENQUEUE_EXHAUST)\n+\t\t\t\t\t\tbreak;\n+\t\t\t\t\t/* Give up enqueue if exhaust not set */\n+\t\t\t\t\tQAT_DP_LOG(ERR, \"Incorrect length\");\n+\t\t\t\t\tqat_sym_dp_fill_vec_status(vec->status,\n+\t\t\t\t\t\t-1, vec->num);\n+\t\t\t\t\treturn 0;\n+\t\t\t\t}\n+\t\t\t} else\n+\t\t\t\tauth_iova_end = digest_vec->iova +\n+\t\t\t\t\tdigest_vec->len;\n+\n+\t\t\t/* Then check if digest-encrypted conditions are met */\n+\t\t\tif ((auth_param->auth_off + auth_param->auth_len <\n+\t\t\t\t\tcipher_param->cipher_offset +\n+\t\t\t\t\tcipher_param->cipher_length) &&\n+\t\t\t\t\t(digest_vec->iova == auth_iova_end)) {\n+\t\t\t\t/* Handle partial digest encryption */\n+\t\t\t\tif (cipher_param->cipher_offset +\n+\t\t\t\t\t\tcipher_param->cipher_length <\n+\t\t\t\t\t\tauth_param->auth_off +\n+\t\t\t\t\t\tauth_param->auth_len +\n+\t\t\t\t\t\tctx->digest_length)\n+\t\t\t\t\treq->comn_mid.dst_length =\n+\t\t\t\t\t\treq->comn_mid.src_length =\n+\t\t\t\t\t\tauth_param->auth_off +\n+\t\t\t\t\t\tauth_param->auth_len +\n+\t\t\t\t\t\tctx->digest_length;\n+\t\t\t\tstruct icp_qat_fw_comn_req_hdr *header =\n+\t\t\t\t\t&req->comn_hdr;\n+\t\t\t\tICP_QAT_FW_LA_DIGEST_IN_BUFFER_SET(\n+\t\t\t\t\theader->serv_specif_flags,\n+\t\t\t\t\tICP_QAT_FW_LA_DIGEST_IN_BUFFER);\n+\t\t\t}\n+\t\t\tbreak;\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_128:\n+\t\tcase ICP_QAT_HW_AUTH_ALGO_GALOIS_64:\n+\t\t\tQAT_DP_LOG(ERR, \"GMAC as auth algo not supported\");\n+\t\t\treturn -1;\n+\t\tdefault:\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\ttail = (tail + tx_queue->msg_size) & tx_queue->modulo_mask;\n+\t}\n+\n+\tif (unlikely(i < vec->num))\n+\t\tqat_sym_dp_fill_vec_status(vec->status + i, -1, vec->num - i);\n+\n+\tqat_sym_dp_update_tx_queue(qp, tx_queue, tail, i, flags);\n+\n+\treturn i;\n+}\n+\n+static __rte_always_inline uint32_t\n+qat_sym_dp_dequeue(struct rte_cryptodev *dev, uint16_t qp_id,\n+\trte_cryptodev_get_dequeue_count_t get_dequeue_count,\n+\trte_cryptodev_post_dequeue_t post_dequeue,\n+\tvoid **out_opaque,\n+\tuint32_t *n_success_jobs, uint32_t flags)\n+{\n+\tstruct qat_qp *qp = dev->data->queue_pairs[qp_id];\n+\tregister struct qat_queue *rx_queue;\n+\tstruct icp_qat_fw_comn_resp *resp, *last_resp = 0;\n+\tvoid *resp_opaque;\n+\tuint32_t i, n;\n+\tuint32_t head;\n+\tuint8_t status;\n+\n+\t*n_success_jobs = 0;\n+\trx_queue = &qp->rx_q;\n+\thead = rx_queue->head;\n+\n+\tresp = (struct icp_qat_fw_comn_resp *)((uint8_t *)rx_queue->base_addr +\n+\t\t\thead);\n+\t/* no operation ready */\n+\tif (unlikely(*(uint32_t *)resp == ADF_RING_EMPTY_SIG))\n+\t\treturn 0;\n+\n+\tresp_opaque = (void *)(uintptr_t)resp->opaque_data;\n+\t/* get the dequeue count */\n+\tn = get_dequeue_count(resp_opaque);\n+\tassert(n > 0);\n+\n+\tout_opaque[0] = resp_opaque;\n+\thead = (head + rx_queue->msg_size) & rx_queue->modulo_mask;\n+\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(resp);\n+\tpost_dequeue(resp_opaque, 0, status);\n+\t*n_success_jobs += status;\n+\n+\t/* we already finished dequeue when n == 1 */\n+\tif (unlikely(n == 1)) {\n+\t\ti = 1;\n+\t\tgoto update_rx_queue;\n+\t}\n+\n+\tlast_resp = (struct icp_qat_fw_comn_resp *)(\n+\t\t(uint8_t *)rx_queue->base_addr + ((head + rx_queue->msg_size *\n+\t\t\t(n - 2)) & rx_queue->modulo_mask));\n+\n+\t/* if EXAUST is not set, check if we can dequeue that many jobs */\n+\tif (flags & RTE_CRYPTO_HW_DP_FF_DEQUEUE_EXHAUST) {\n+\t\tif (flags & RTE_CRYPTO_HW_DP_FF_GET_OPAQUE_ARRAY) {\n+\t\t\tfor (i = 1; i < n - 1; i++) {\n+\t\t\t\tresp = (struct icp_qat_fw_comn_resp *)(\n+\t\t\t\t\t(uint8_t *)rx_queue->base_addr + head);\n+\t\t\t\tif (unlikely(*(uint32_t *)resp ==\n+\t\t\t\t\t\tADF_RING_EMPTY_SIG))\n+\t\t\t\t\tgoto update_rx_queue;\n+\t\t\t\tout_opaque[i] = (void *)(uintptr_t)\n+\t\t\t\t\t\tresp->opaque_data;\n+\t\t\t\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(resp);\n+\t\t\t\t*n_success_jobs += status;\n+\t\t\t\tpost_dequeue(out_opaque[i], i, status);\n+\t\t\t\thead = (head + rx_queue->msg_size) &\n+\t\t\t\t\t\trx_queue->modulo_mask;\n+\t\t\t}\n+\n+\t\t\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(last_resp);\n+\t\t\tout_opaque[i] = (void *)(uintptr_t)\n+\t\t\t\t\tlast_resp->opaque_data;\n+\t\t\tpost_dequeue(out_opaque[i], i, status);\n+\t\t\t*n_success_jobs += status;\n+\t\t\ti++;\n+\t\t\thead = (head + rx_queue->msg_size) &\n+\t\t\t\t\trx_queue->modulo_mask;\n+\t\t\tgoto update_rx_queue;\n+\t\t}\n+\n+\t\t/* (flags & RTE_CRYPTO_HW_DP_FF_GET_OPAQUE_ARRAY) == 0 */\n+\t\tfor (i = 1; i < n - 1; i++) {\n+\t\t\tresp = (struct icp_qat_fw_comn_resp *)(\n+\t\t\t\t(uint8_t *)rx_queue->base_addr + head);\n+\t\t\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(resp);\n+\t\t\tif (unlikely(*(uint32_t *)resp == ADF_RING_EMPTY_SIG))\n+\t\t\t\tgoto update_rx_queue;\n+\t\t\thead = (head + rx_queue->msg_size) &\n+\t\t\t\t\trx_queue->modulo_mask;\n+\t\t\tpost_dequeue(resp_opaque, i, status);\n+\t\t\t*n_success_jobs += status;\n+\t\t}\n+\t\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(last_resp);\n+\t\tpost_dequeue(resp_opaque, i, status);\n+\t\t*n_success_jobs += status;\n+\t\ti++;\n+\t\thead = (head + rx_queue->msg_size) & rx_queue->modulo_mask;\n+\t\tgoto update_rx_queue;\n+\t}\n+\n+\t/* not all operation ready */\n+\tif (unlikely(*(uint32_t *)last_resp == ADF_RING_EMPTY_SIG))\n+\t\treturn 0;\n+\n+\tif (flags & RTE_CRYPTO_HW_DP_FF_GET_OPAQUE_ARRAY) {\n+\t\tfor (i = 1; i < n - 1; i++) {\n+\t\t\tuint8_t status;\n+\n+\t\t\tresp = (struct icp_qat_fw_comn_resp *)(\n+\t\t\t\t(uint8_t *)rx_queue->base_addr + head);\n+\t\t\tout_opaque[i] = (void *)(uintptr_t)resp->opaque_data;\n+\t\t\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(resp);\n+\t\t\t*n_success_jobs += status;\n+\t\t\tpost_dequeue(out_opaque[i], i, status);\n+\t\t\thead = (head + rx_queue->msg_size) &\n+\t\t\t\t\trx_queue->modulo_mask;\n+\t\t}\n+\t\tout_opaque[i] = (void *)(uintptr_t)last_resp->opaque_data;\n+\t\tpost_dequeue(out_opaque[i], i,\n+\t\t\t\tQAT_SYM_DP_IS_RESP_SUCCESS(last_resp));\n+\t\ti++;\n+\t\thead = (head + rx_queue->msg_size) & rx_queue->modulo_mask;\n+\t\tgoto update_rx_queue;\n+\t}\n+\n+\t/* (flags & RTE_CRYPTO_HW_DP_FF_GET_OPAQUE_ARRAY) == 0 */\n+\tfor (i = 1; i < n - 1; i++) {\n+\t\tresp = (struct icp_qat_fw_comn_resp *)(\n+\t\t\t(uint8_t *)rx_queue->base_addr + head);\n+\t\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(resp);\n+\t\t*n_success_jobs += status;\n+\t\tpost_dequeue(resp_opaque, i, status);\n+\t\thead = (head + rx_queue->msg_size) & rx_queue->modulo_mask;\n+\t}\n+\n+\tstatus = QAT_SYM_DP_IS_RESP_SUCCESS(resp);\n+\thead = (head + rx_queue->msg_size) & rx_queue->modulo_mask;\n+\ti++;\n+\t*n_success_jobs += status;\n+\tpost_dequeue(resp_opaque, i, status);\n+\n+update_rx_queue:\n+\trx_queue->head = head;\n+\trx_queue->nb_processed_responses += i;\n+\tqp->dequeued += i;\n+\tqp->stats.dequeued_count += i;\n+\tif (rx_queue->nb_processed_responses > QAT_CSR_HEAD_WRITE_THRESH) {\n+\t\tuint32_t old_head, new_head;\n+\t\tuint32_t max_head;\n+\n+\t\told_head = rx_queue->csr_head;\n+\t\tnew_head = rx_queue->head;\n+\t\tmax_head = qp->nb_descriptors * rx_queue->msg_size;\n+\n+\t\t/* write out free descriptors */\n+\t\tvoid *cur_desc = (uint8_t *)rx_queue->base_addr + old_head;\n+\n+\t\tif (new_head < old_head) {\n+\t\t\tmemset(cur_desc, ADF_RING_EMPTY_SIG_BYTE,\n+\t\t\t\t\tmax_head - old_head);\n+\t\t\tmemset(rx_queue->base_addr, ADF_RING_EMPTY_SIG_BYTE,\n+\t\t\t\t\tnew_head);\n+\t\t} else {\n+\t\t\tmemset(cur_desc, ADF_RING_EMPTY_SIG_BYTE, new_head -\n+\t\t\t\t\told_head);\n+\t\t}\n+\t\trx_queue->nb_processed_responses = 0;\n+\t\trx_queue->csr_head = new_head;\n+\n+\t\t/* write current head to CSR */\n+\t\tWRITE_CSR_RING_HEAD(qp->mmap_bar_addr,\n+\t\t\trx_queue->hw_bundle_number, rx_queue->hw_queue_number,\n+\t\t\tnew_head);\n+\t}\n+\n+\treturn i;\n+}\n+\n+struct rte_crytodev_sym_hw_dp_ops qat_hw_dp_ops = {\n+\t.enqueue_aead = qat_sym_dp_enqueue_aead,\n+\t.enqueue_cipher = qat_sym_dp_enqueue_cipher,\n+\t.enqueue_auth = qat_sym_dp_enqueue_auth,\n+\t.enqueue_chain = qat_sym_dp_enqueue_chain,\n+\t.dequeue = qat_sym_dp_dequeue\n+};\ndiff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c\nindex c7e323cce..ba6c2130f 100644\n--- a/drivers/crypto/qat/qat_sym_pmd.c\n+++ b/drivers/crypto/qat/qat_sym_pmd.c\n@@ -259,7 +259,9 @@ static struct rte_cryptodev_ops crypto_qat_ops = {\n \t\t/* Crypto related operations */\n \t\t.sym_session_get_size\t= qat_sym_session_get_private_size,\n \t\t.sym_session_configure\t= qat_sym_session_configure,\n-\t\t.sym_session_clear\t= qat_sym_session_clear\n+\t\t.sym_session_clear\t= qat_sym_session_clear,\n+\n+\t\t.sym_hw_enq_deq = &qat_hw_dp_ops\n };\n \n #ifdef RTE_LIBRTE_SECURITY\n@@ -382,7 +384,8 @@ qat_sym_dev_create(struct qat_pci_device *qat_pci_dev,\n \t\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_SGL_OUT |\n \t\t\tRTE_CRYPTODEV_FF_OOP_LB_IN_LB_OUT |\n \t\t\tRTE_CRYPTODEV_FF_DIGEST_ENCRYPTED |\n-\t\t\tRTE_CRYPTODEV_FF_SECURITY;\n+\t\t\tRTE_CRYPTODEV_FF_SECURITY |\n+\t\t\tRTE_CRYPTODEV_FF_SYM_HW_DIRECT_API;\n \n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY)\n \t\treturn 0;\n",
    "prefixes": [
        "v5",
        "2/4"
    ]
}