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GET /api/patches/77119/?format=api
{ "id": 77119, "url": "http://patchwork.dpdk.org/api/patches/77119/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1599722434-432403-1-git-send-email-matan@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1599722434-432403-1-git-send-email-matan@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1599722434-432403-1-git-send-email-matan@nvidia.com", "date": "2020-09-10T07:20:34", "name": "vdpa/mlx5: fix completion queue polling", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "a6edc02d4b16af512fdbb8c9739c690f8d9386e5", "submitter": { "id": 1911, "url": "http://patchwork.dpdk.org/api/people/1911/?format=api", "name": "Matan Azrad", "email": "matan@nvidia.com" }, "delegate": { "id": 2642, "url": "http://patchwork.dpdk.org/api/users/2642/?format=api", "username": "mcoquelin", "first_name": "Maxime", "last_name": "Coquelin", "email": "maxime.coquelin@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1599722434-432403-1-git-send-email-matan@nvidia.com/mbox/", "series": [ { "id": 12089, "url": "http://patchwork.dpdk.org/api/series/12089/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=12089", "date": "2020-09-10T07:20:34", "name": "vdpa/mlx5: fix completion queue polling", "version": 1, "mbox": "http://patchwork.dpdk.org/series/12089/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/77119/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/77119/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from dpdk.org (dpdk.org [92.243.14.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 146B2A04B5;\n\tThu, 10 Sep 2020 09:20:45 +0200 (CEST)", "from [92.243.14.124] (localhost [127.0.0.1])\n\tby dpdk.org (Postfix) with ESMTP id B3DE91BFB4;\n\tThu, 10 Sep 2020 09:20:43 +0200 (CEST)", "from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129])\n by dpdk.org (Postfix) with ESMTP id 157A1DE0\n for <dev@dpdk.org>; Thu, 10 Sep 2020 09:20:41 +0200 (CEST)", "from Internal Mail-Server by MTLPINE1 (envelope-from\n matan@nvidia.com) with SMTP; 10 Sep 2020 10:20:37 +0300", "from nvidia.com (pegasus25.mtr.labs.mlnx [10.210.16.10])\n by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 08A7KbNr012939;\n Thu, 10 Sep 2020 10:20:37 +0300" ], "From": "Matan Azrad <matan@nvidia.com>", "To": "Maxime Coquelin <maxime.coquelin@redhat.com>", "Cc": "dev@dpdk.org, stable@dpdk.org", "Date": "Thu, 10 Sep 2020 07:20:34 +0000", "Message-Id": "<1599722434-432403-1-git-send-email-matan@nvidia.com>", "X-Mailer": "git-send-email 1.8.3.1", "Subject": "[dpdk-dev] [PATCH] vdpa/mlx5: fix completion queue polling", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.15", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The CQ polling is done in order to notify the guest about new traffic\nbursts and to release FW resources for the next bursts management.\n\nWhen HW is faster than SW, it may be that all the FW resources are busy\nin SW due to late polling.\nIn this case, due to wrong WQE counter masking, the fullness\ncalculation of the completions number is 0 while the queue is full.\n\nChange the WQE counter masking to 16-bit wideness instead of the CQ\nsize mask as defined by the CQE format.\n\nFixes: c5f714e50b0e (\"vdpa/mlx5: optimize completion queue poll\")\nCc: stable@dpdk.org\n\nSigned-off-by: Matan Azrad <matan@nvidia.com>\nAcked-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/vdpa/mlx5/mlx5_vdpa_event.c | 7 +++----\n 1 file changed, 3 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/vdpa/mlx5/mlx5_vdpa_event.c b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\nindex 5a2d4fb..2672935 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa_event.c\n@@ -172,7 +172,7 @@\n \tcq->callfd = callfd;\n \t/* Init CQ to ones to be in HW owner in the start. */\n \tcq->cqes[0].op_own = MLX5_CQE_OWNER_MASK;\n-\tcq->cqes[0].wqe_counter = rte_cpu_to_be_16(cq_size - 1);\n+\tcq->cqes[0].wqe_counter = rte_cpu_to_be_16(UINT16_MAX);\n \t/* First arming. */\n \tmlx5_vdpa_cq_arm(priv, cq);\n \treturn 0;\n@@ -187,7 +187,6 @@\n \tstruct mlx5_vdpa_event_qp *eqp =\n \t\t\t\tcontainer_of(cq, struct mlx5_vdpa_event_qp, cq);\n \tconst unsigned int cq_size = 1 << cq->log_desc_n;\n-\tconst unsigned int cq_mask = cq_size - 1;\n \tunion {\n \t\tstruct {\n \t\t\tuint16_t wqe_counter;\n@@ -196,13 +195,13 @@\n \t\t};\n \t\tuint32_t word;\n \t} last_word;\n-\tuint16_t next_wqe_counter = cq->cq_ci & cq_mask;\n+\tuint16_t next_wqe_counter = cq->cq_ci;\n \tuint16_t cur_wqe_counter;\n \tuint16_t comp;\n \n \tlast_word.word = rte_read32(&cq->cqes[0].wqe_counter);\n \tcur_wqe_counter = rte_be_to_cpu_16(last_word.wqe_counter);\n-\tcomp = (cur_wqe_counter + 1u - next_wqe_counter) & cq_mask;\n+\tcomp = cur_wqe_counter + (uint16_t)1 - next_wqe_counter;\n \tif (comp) {\n \t\tcq->cq_ci += comp;\n \t\tMLX5_ASSERT(!!(cq->cq_ci & cq_size) ==\n", "prefixes": [] }