Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/86419/?format=api
{ "id": 86419, "url": "http://patchwork.dpdk.org/api/patches/86419/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/9a07d5777a2e7d0b9d33be9c3b2aeff97d4ef066.1610473000.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<9a07d5777a2e7d0b9d33be9c3b2aeff97d4ef066.1610473000.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/9a07d5777a2e7d0b9d33be9c3b2aeff97d4ef066.1610473000.git.anatoly.burakov@intel.com", "date": "2021-01-12T17:37:09", "name": "[v16,01/11] eal: uninline power intrinsics", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "d6d3cac1659f887e3b3c505abc30d9bee759b31e", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Anatoly Burakov", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/9a07d5777a2e7d0b9d33be9c3b2aeff97d4ef066.1610473000.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 14673, "url": "http://patchwork.dpdk.org/api/series/14673/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14673", "date": "2021-01-12T17:37:08", "name": "Add PMD power management", "version": 16, "mbox": "http://patchwork.dpdk.org/series/14673/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/86419/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/86419/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 61084A04B5;\n\tTue, 12 Jan 2021 18:37:33 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id E09F6140EA3;\n\tTue, 12 Jan 2021 18:37:27 +0100 (CET)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id DD0D9140E76\n for <dev@dpdk.org>; Tue, 12 Jan 2021 18:37:25 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Jan 2021 09:37:25 -0800", "from silpixa00399498.ir.intel.com (HELO\n silpixa00399498.ger.corp.intel.com) ([10.237.222.179])\n by fmsmga001.fm.intel.com with ESMTP; 12 Jan 2021 09:37:22 -0800" ], "IronPort-SDR": [ "\n knWhA1W84BsP5aIrNCLshMdLpAqPKmJmJBzIHfJ9XutGWYnc9HK5nEu2EaDBhm69S80sG5z/XA\n ku2sFAqVjZSQ==", "\n MB4QcVpltrnp3xuulIp4xRj9HRye/kkJQegwA7udTkDHwjxoAdNROeHspWpB8iF6v7SwnehWx3\n L0EzJCFR3O2A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9862\"; a=\"175497958\"", "E=Sophos;i=\"5.79,342,1602572400\"; d=\"scan'208\";a=\"175497958\"", "E=Sophos;i=\"5.79,342,1602572400\"; d=\"scan'208\";a=\"464604136\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Jan Viktorin <viktorin@rehivetech.com>,\n Ruifeng Wang <ruifeng.wang@arm.com>, Jerin Jacob <jerinj@marvell.com>,\n David Christensen <drc@linux.vnet.ibm.com>, Ray Kinsella <mdr@ashroe.eu>,\n Neil Horman <nhorman@tuxdriver.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, thomas@monjalon.net,\n timothy.mcdaniel@intel.com, david.hunt@intel.com, chris.macnamara@intel.com", "Date": "Tue, 12 Jan 2021 17:37:09 +0000", "Message-Id": "\n <9a07d5777a2e7d0b9d33be9c3b2aeff97d4ef066.1610473000.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1610473000.git.anatoly.burakov@intel.com>", "References": "<cover.1610377084.git.anatoly.burakov@intel.com>\n <cover.1610473000.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v16 01/11] eal: uninline power intrinsics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Currently, power intrinsics are inline functions. Make them part of the\nABI so that we can have various internal data associated with them\nwithout exposing said data to the outside world.\n\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n\nNotes:\n v14:\n - Fix compile issues on ARM and PPC64 by moving implementations to .c files\n\n .../arm/include/rte_power_intrinsics.h | 40 ------\n lib/librte_eal/arm/meson.build | 1 +\n lib/librte_eal/arm/rte_power_intrinsics.c | 45 +++++++\n .../include/generic/rte_power_intrinsics.h | 6 +-\n .../ppc/include/rte_power_intrinsics.h | 40 ------\n lib/librte_eal/ppc/meson.build | 1 +\n lib/librte_eal/ppc/rte_power_intrinsics.c | 45 +++++++\n lib/librte_eal/version.map | 3 +\n .../x86/include/rte_power_intrinsics.h | 115 -----------------\n lib/librte_eal/x86/meson.build | 1 +\n lib/librte_eal/x86/rte_power_intrinsics.c | 120 ++++++++++++++++++\n 11 files changed, 219 insertions(+), 198 deletions(-)\n create mode 100644 lib/librte_eal/arm/rte_power_intrinsics.c\n create mode 100644 lib/librte_eal/ppc/rte_power_intrinsics.c\n create mode 100644 lib/librte_eal/x86/rte_power_intrinsics.c", "diff": "diff --git a/lib/librte_eal/arm/include/rte_power_intrinsics.h b/lib/librte_eal/arm/include/rte_power_intrinsics.h\nindex a4a1bc1159..9e498e9ebf 100644\n--- a/lib/librte_eal/arm/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/arm/include/rte_power_intrinsics.h\n@@ -13,46 +13,6 @@ extern \"C\" {\n \n #include \"generic/rte_power_intrinsics.h\"\n \n-/**\n- * This function is not supported on ARM.\n- */\n-static inline void\n-rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz)\n-{\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n-\tRTE_SET_USED(tsc_timestamp);\n-\tRTE_SET_USED(data_sz);\n-}\n-\n-/**\n- * This function is not supported on ARM.\n- */\n-static inline void\n-rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n-{\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n-\tRTE_SET_USED(tsc_timestamp);\n-\tRTE_SET_USED(lck);\n-\tRTE_SET_USED(data_sz);\n-}\n-\n-/**\n- * This function is not supported on ARM.\n- */\n-static inline void\n-rte_power_pause(const uint64_t tsc_timestamp)\n-{\n-\tRTE_SET_USED(tsc_timestamp);\n-}\n-\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/arm/meson.build b/lib/librte_eal/arm/meson.build\nindex d62875ebae..6ec53ea03a 100644\n--- a/lib/librte_eal/arm/meson.build\n+++ b/lib/librte_eal/arm/meson.build\n@@ -7,4 +7,5 @@ sources += files(\n \t'rte_cpuflags.c',\n \t'rte_cycles.c',\n \t'rte_hypervisor.c',\n+\t'rte_power_intrinsics.c',\n )\ndiff --git a/lib/librte_eal/arm/rte_power_intrinsics.c b/lib/librte_eal/arm/rte_power_intrinsics.c\nnew file mode 100644\nindex 0000000000..ab1f44f611\n--- /dev/null\n+++ b/lib/librte_eal/arm/rte_power_intrinsics.c\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#include \"rte_power_intrinsics.h\"\n+\n+/**\n+ * This function is not supported on ARM.\n+ */\n+void\n+rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n+\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n+\t\tconst uint8_t data_sz)\n+{\n+\tRTE_SET_USED(p);\n+\tRTE_SET_USED(expected_value);\n+\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(tsc_timestamp);\n+\tRTE_SET_USED(data_sz);\n+}\n+\n+/**\n+ * This function is not supported on ARM.\n+ */\n+void\n+rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n+\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n+\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n+{\n+\tRTE_SET_USED(p);\n+\tRTE_SET_USED(expected_value);\n+\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(tsc_timestamp);\n+\tRTE_SET_USED(lck);\n+\tRTE_SET_USED(data_sz);\n+}\n+\n+/**\n+ * This function is not supported on ARM.\n+ */\n+void\n+rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(tsc_timestamp);\n+}\ndiff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h\nindex dd520d90fa..67977bd511 100644\n--- a/lib/librte_eal/include/generic/rte_power_intrinsics.h\n+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h\n@@ -52,7 +52,7 @@\n * to undefined result.\n */\n __rte_experimental\n-static inline void rte_power_monitor(const volatile void *p,\n+void rte_power_monitor(const volatile void *p,\n \t\tconst uint64_t expected_value, const uint64_t value_mask,\n \t\tconst uint64_t tsc_timestamp, const uint8_t data_sz);\n \n@@ -97,7 +97,7 @@ static inline void rte_power_monitor(const volatile void *p,\n * wakes up.\n */\n __rte_experimental\n-static inline void rte_power_monitor_sync(const volatile void *p,\n+void rte_power_monitor_sync(const volatile void *p,\n \t\tconst uint64_t expected_value, const uint64_t value_mask,\n \t\tconst uint64_t tsc_timestamp, const uint8_t data_sz,\n \t\trte_spinlock_t *lck);\n@@ -118,6 +118,6 @@ static inline void rte_power_monitor_sync(const volatile void *p,\n * architecture-dependent.\n */\n __rte_experimental\n-static inline void rte_power_pause(const uint64_t tsc_timestamp);\n+void rte_power_pause(const uint64_t tsc_timestamp);\n \n #endif /* _RTE_POWER_INTRINSIC_H_ */\ndiff --git a/lib/librte_eal/ppc/include/rte_power_intrinsics.h b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\nindex 4ed03d521f..c0e9ac279f 100644\n--- a/lib/librte_eal/ppc/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/ppc/include/rte_power_intrinsics.h\n@@ -13,46 +13,6 @@ extern \"C\" {\n \n #include \"generic/rte_power_intrinsics.h\"\n \n-/**\n- * This function is not supported on PPC64.\n- */\n-static inline void\n-rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz)\n-{\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n-\tRTE_SET_USED(tsc_timestamp);\n-\tRTE_SET_USED(data_sz);\n-}\n-\n-/**\n- * This function is not supported on PPC64.\n- */\n-static inline void\n-rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n-{\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n-\tRTE_SET_USED(tsc_timestamp);\n-\tRTE_SET_USED(lck);\n-\tRTE_SET_USED(data_sz);\n-}\n-\n-/**\n- * This function is not supported on PPC64.\n- */\n-static inline void\n-rte_power_pause(const uint64_t tsc_timestamp)\n-{\n-\tRTE_SET_USED(tsc_timestamp);\n-}\n-\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/ppc/meson.build b/lib/librte_eal/ppc/meson.build\nindex f4b6d95c42..43c46542fb 100644\n--- a/lib/librte_eal/ppc/meson.build\n+++ b/lib/librte_eal/ppc/meson.build\n@@ -7,4 +7,5 @@ sources += files(\n \t'rte_cpuflags.c',\n \t'rte_cycles.c',\n \t'rte_hypervisor.c',\n+\t'rte_power_intrinsics.c',\n )\ndiff --git a/lib/librte_eal/ppc/rte_power_intrinsics.c b/lib/librte_eal/ppc/rte_power_intrinsics.c\nnew file mode 100644\nindex 0000000000..84340ca2a4\n--- /dev/null\n+++ b/lib/librte_eal/ppc/rte_power_intrinsics.c\n@@ -0,0 +1,45 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2021 Intel Corporation\n+ */\n+\n+#include \"rte_power_intrinsics.h\"\n+\n+/**\n+ * This function is not supported on PPC64.\n+ */\n+void\n+rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n+\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n+\t\tconst uint8_t data_sz)\n+{\n+\tRTE_SET_USED(p);\n+\tRTE_SET_USED(expected_value);\n+\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(tsc_timestamp);\n+\tRTE_SET_USED(data_sz);\n+}\n+\n+/**\n+ * This function is not supported on PPC64.\n+ */\n+void\n+rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n+\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n+\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n+{\n+\tRTE_SET_USED(p);\n+\tRTE_SET_USED(expected_value);\n+\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(tsc_timestamp);\n+\tRTE_SET_USED(lck);\n+\tRTE_SET_USED(data_sz);\n+}\n+\n+/**\n+ * This function is not supported on PPC64.\n+ */\n+void\n+rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tRTE_SET_USED(tsc_timestamp);\n+}\ndiff --git a/lib/librte_eal/version.map b/lib/librte_eal/version.map\nindex b1db7ec795..32eceb8869 100644\n--- a/lib/librte_eal/version.map\n+++ b/lib/librte_eal/version.map\n@@ -405,6 +405,9 @@ EXPERIMENTAL {\n \trte_vect_set_max_simd_bitwidth;\n \n \t# added in 21.02\n+\trte_power_monitor;\n+\trte_power_monitor_sync;\n+\trte_power_pause;\n \trte_thread_tls_key_create;\n \trte_thread_tls_key_delete;\n \trte_thread_tls_value_get;\ndiff --git a/lib/librte_eal/x86/include/rte_power_intrinsics.h b/lib/librte_eal/x86/include/rte_power_intrinsics.h\nindex c7d790c854..e4c2b87f73 100644\n--- a/lib/librte_eal/x86/include/rte_power_intrinsics.h\n+++ b/lib/librte_eal/x86/include/rte_power_intrinsics.h\n@@ -13,121 +13,6 @@ extern \"C\" {\n \n #include \"generic/rte_power_intrinsics.h\"\n \n-static inline uint64_t\n-__rte_power_get_umwait_val(const volatile void *p, const uint8_t sz)\n-{\n-\tswitch (sz) {\n-\tcase sizeof(uint8_t):\n-\t\treturn *(const volatile uint8_t *)p;\n-\tcase sizeof(uint16_t):\n-\t\treturn *(const volatile uint16_t *)p;\n-\tcase sizeof(uint32_t):\n-\t\treturn *(const volatile uint32_t *)p;\n-\tcase sizeof(uint64_t):\n-\t\treturn *(const volatile uint64_t *)p;\n-\tdefault:\n-\t\t/* this is an intrinsic, so we can't have any error handling */\n-\t\tRTE_ASSERT(0);\n-\t\treturn 0;\n-\t}\n-}\n-\n-/**\n- * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n- * For more information about usage of these instructions, please refer to\n- * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n- */\n-static inline void\n-rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz)\n-{\n-\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n-\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n-\t/*\n-\t * we're using raw byte codes for now as only the newest compiler\n-\t * versions support this instruction natively.\n-\t */\n-\n-\t/* set address for UMONITOR */\n-\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n-\t\t\t:\n-\t\t\t: \"D\"(p));\n-\n-\tif (value_mask) {\n-\t\tconst uint64_t cur_value = __rte_power_get_umwait_val(p, data_sz);\n-\t\tconst uint64_t masked = cur_value & value_mask;\n-\n-\t\t/* if the masked value is already matching, abort */\n-\t\tif (masked == expected_value)\n-\t\t\treturn;\n-\t}\n-\t/* execute UMWAIT */\n-\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n-\t\t\t: /* ignore rflags */\n-\t\t\t: \"D\"(0), /* enter C0.2 */\n-\t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n-}\n-\n-/**\n- * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n- * For more information about usage of these instructions, please refer to\n- * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n- */\n-static inline void\n-rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n-{\n-\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n-\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n-\t/*\n-\t * we're using raw byte codes for now as only the newest compiler\n-\t * versions support this instruction natively.\n-\t */\n-\n-\t/* set address for UMONITOR */\n-\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n-\t\t\t:\n-\t\t\t: \"D\"(p));\n-\n-\tif (value_mask) {\n-\t\tconst uint64_t cur_value = __rte_power_get_umwait_val(p, data_sz);\n-\t\tconst uint64_t masked = cur_value & value_mask;\n-\n-\t\t/* if the masked value is already matching, abort */\n-\t\tif (masked == expected_value)\n-\t\t\treturn;\n-\t}\n-\trte_spinlock_unlock(lck);\n-\n-\t/* execute UMWAIT */\n-\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n-\t\t\t: /* ignore rflags */\n-\t\t\t: \"D\"(0), /* enter C0.2 */\n-\t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n-\n-\trte_spinlock_lock(lck);\n-}\n-\n-/**\n- * This function uses TPAUSE instruction and will enter C0.2 state. For more\n- * information about usage of this instruction, please refer to Intel(R) 64 and\n- * IA-32 Architectures Software Developer's Manual.\n- */\n-static inline void\n-rte_power_pause(const uint64_t tsc_timestamp)\n-{\n-\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n-\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n-\n-\t/* execute TPAUSE */\n-\tasm volatile(\".byte 0x66, 0x0f, 0xae, 0xf7;\"\n-\t\t: /* ignore rflags */\n-\t\t: \"D\"(0), /* enter C0.2 */\n-\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n-}\n-\n #ifdef __cplusplus\n }\n #endif\ndiff --git a/lib/librte_eal/x86/meson.build b/lib/librte_eal/x86/meson.build\nindex e78f29002e..dfd42dee0c 100644\n--- a/lib/librte_eal/x86/meson.build\n+++ b/lib/librte_eal/x86/meson.build\n@@ -8,4 +8,5 @@ sources += files(\n \t'rte_cycles.c',\n \t'rte_hypervisor.c',\n \t'rte_spinlock.c',\n+\t'rte_power_intrinsics.c',\n )\ndiff --git a/lib/librte_eal/x86/rte_power_intrinsics.c b/lib/librte_eal/x86/rte_power_intrinsics.c\nnew file mode 100644\nindex 0000000000..34c5fd9c3e\n--- /dev/null\n+++ b/lib/librte_eal/x86/rte_power_intrinsics.c\n@@ -0,0 +1,120 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2020 Intel Corporation\n+ */\n+\n+#include \"rte_power_intrinsics.h\"\n+\n+static inline uint64_t\n+__get_umwait_val(const volatile void *p, const uint8_t sz)\n+{\n+\tswitch (sz) {\n+\tcase sizeof(uint8_t):\n+\t\treturn *(const volatile uint8_t *)p;\n+\tcase sizeof(uint16_t):\n+\t\treturn *(const volatile uint16_t *)p;\n+\tcase sizeof(uint32_t):\n+\t\treturn *(const volatile uint32_t *)p;\n+\tcase sizeof(uint64_t):\n+\t\treturn *(const volatile uint64_t *)p;\n+\tdefault:\n+\t\t/* this is an intrinsic, so we can't have any error handling */\n+\t\tRTE_ASSERT(0);\n+\t\treturn 0;\n+\t}\n+}\n+\n+/**\n+ * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n+ * For more information about usage of these instructions, please refer to\n+ * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n+ */\n+void\n+rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n+\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n+\t\tconst uint8_t data_sz)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n+\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\t/*\n+\t * we're using raw byte codes for now as only the newest compiler\n+\t * versions support this instruction natively.\n+\t */\n+\n+\t/* set address for UMONITOR */\n+\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n+\t\t\t:\n+\t\t\t: \"D\"(p));\n+\n+\tif (value_mask) {\n+\t\tconst uint64_t cur_value = __get_umwait_val(p, data_sz);\n+\t\tconst uint64_t masked = cur_value & value_mask;\n+\n+\t\t/* if the masked value is already matching, abort */\n+\t\tif (masked == expected_value)\n+\t\t\treturn;\n+\t}\n+\t/* execute UMWAIT */\n+\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n+\t\t\t: /* ignore rflags */\n+\t\t\t: \"D\"(0), /* enter C0.2 */\n+\t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n+}\n+\n+/**\n+ * This function uses UMONITOR/UMWAIT instructions and will enter C0.2 state.\n+ * For more information about usage of these instructions, please refer to\n+ * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n+ */\n+void\n+rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n+\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n+\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n+\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\t/*\n+\t * we're using raw byte codes for now as only the newest compiler\n+\t * versions support this instruction natively.\n+\t */\n+\n+\t/* set address for UMONITOR */\n+\tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n+\t\t\t:\n+\t\t\t: \"D\"(p));\n+\n+\tif (value_mask) {\n+\t\tconst uint64_t cur_value = __get_umwait_val(p, data_sz);\n+\t\tconst uint64_t masked = cur_value & value_mask;\n+\n+\t\t/* if the masked value is already matching, abort */\n+\t\tif (masked == expected_value)\n+\t\t\treturn;\n+\t}\n+\trte_spinlock_unlock(lck);\n+\n+\t/* execute UMWAIT */\n+\tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n+\t\t\t: /* ignore rflags */\n+\t\t\t: \"D\"(0), /* enter C0.2 */\n+\t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n+\n+\trte_spinlock_lock(lck);\n+}\n+\n+/**\n+ * This function uses TPAUSE instruction and will enter C0.2 state. For more\n+ * information about usage of this instruction, please refer to Intel(R) 64 and\n+ * IA-32 Architectures Software Developer's Manual.\n+ */\n+void\n+rte_power_pause(const uint64_t tsc_timestamp)\n+{\n+\tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n+\tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\n+\t/* execute TPAUSE */\n+\tasm volatile(\".byte 0x66, 0x0f, 0xae, 0xf7;\"\n+\t\t\t: /* ignore rflags */\n+\t\t\t: \"D\"(0), /* enter C0.2 */\n+\t\t\t\"a\"(tsc_l), \"d\"(tsc_h));\n+}\n", "prefixes": [ "v16", "01/11" ] }