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GET /api/patches/86421/?format=api
{ "id": 86421, "url": "http://patchwork.dpdk.org/api/patches/86421/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/f32d9217045ba88e93a708c9d07858dfda8c8447.1610473000.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<f32d9217045ba88e93a708c9d07858dfda8c8447.1610473000.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/f32d9217045ba88e93a708c9d07858dfda8c8447.1610473000.git.anatoly.burakov@intel.com", "date": "2021-01-12T17:37:11", "name": "[v16,03/11] eal: change API of power intrinsics", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "9251b9e28203d60f7397d54f5dab289c7de1930c", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Anatoly Burakov", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/f32d9217045ba88e93a708c9d07858dfda8c8447.1610473000.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 14673, "url": "http://patchwork.dpdk.org/api/series/14673/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14673", "date": "2021-01-12T17:37:08", "name": "Add PMD power management", "version": 16, "mbox": "http://patchwork.dpdk.org/series/14673/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/86421/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/86421/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 15D7DA04B5;\n\tTue, 12 Jan 2021 18:37:52 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id AD41B140EB9;\n\tTue, 12 Jan 2021 18:37:33 +0100 (CET)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id A1C04140EB8\n for <dev@dpdk.org>; Tue, 12 Jan 2021 18:37:31 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Jan 2021 09:37:31 -0800", "from silpixa00399498.ir.intel.com (HELO\n silpixa00399498.ger.corp.intel.com) ([10.237.222.179])\n by fmsmga001.fm.intel.com with ESMTP; 12 Jan 2021 09:37:28 -0800" ], "IronPort-SDR": [ "\n 5wCpuL0IXcQpL4i++iJoYzQkcwNSeHiuuVDeqUuOrGrTa/+Z+HFxZkoZF9MIVx4KLnUrXSWdp+\n 5xE4FRDjsQDA==", "\n 5H7HuywDXd6Y32xN7lnS18Obl1wp09ZjLI4jeYTCF1x6EeG45lGNKd8W9D9FWLZcU/AtITG0q9\n wfDQn6243MEA==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9862\"; a=\"175498003\"", "E=Sophos;i=\"5.79,342,1602572400\"; d=\"scan'208\";a=\"175498003\"", "E=Sophos;i=\"5.79,342,1602572400\"; d=\"scan'208\";a=\"464604181\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Timothy McDaniel <timothy.mcdaniel@intel.com>,\n Jerin Jacob <jerinj@marvell.com>, Ruifeng Wang <ruifeng.wang@arm.com>,\n Jan Viktorin <viktorin@rehivetech.com>,\n David Christensen <drc@linux.vnet.ibm.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, thomas@monjalon.net,\n david.hunt@intel.com, chris.macnamara@intel.com", "Date": "Tue, 12 Jan 2021 17:37:11 +0000", "Message-Id": "\n <f32d9217045ba88e93a708c9d07858dfda8c8447.1610473000.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1610473000.git.anatoly.burakov@intel.com>", "References": "<cover.1610377084.git.anatoly.burakov@intel.com>\n <cover.1610473000.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v16 03/11] eal: change API of power intrinsics", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Instead of passing around pointers and integers, collect everything\ninto struct. This makes API design around these intrinsics much easier.\n\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\nAcked-by: Konstantin Ananyev <konstantin.ananyev@intel.com>\n---\n\nNotes:\n v16:\n - Add error handling\n\n drivers/event/dlb/dlb.c | 10 ++--\n drivers/event/dlb2/dlb2.c | 10 ++--\n lib/librte_eal/arm/rte_power_intrinsics.c | 20 +++-----\n .../include/generic/rte_power_intrinsics.h | 50 ++++++++-----------\n lib/librte_eal/ppc/rte_power_intrinsics.c | 20 +++-----\n lib/librte_eal/x86/rte_power_intrinsics.c | 42 +++++++++-------\n 6 files changed, 70 insertions(+), 82 deletions(-)", "diff": "diff --git a/drivers/event/dlb/dlb.c b/drivers/event/dlb/dlb.c\nindex 0c95c4793d..d2f2026291 100644\n--- a/drivers/event/dlb/dlb.c\n+++ b/drivers/event/dlb/dlb.c\n@@ -3161,6 +3161,7 @@ dlb_dequeue_wait(struct dlb_eventdev *dlb,\n \t\t/* Interrupts not supported by PF PMD */\n \t\treturn 1;\n \t} else if (dlb->umwait_allowed) {\n+\t\tstruct rte_power_monitor_cond pmc;\n \t\tvolatile struct dlb_dequeue_qe *cq_base;\n \t\tunion {\n \t\t\tuint64_t raw_qe[2];\n@@ -3181,9 +3182,12 @@ dlb_dequeue_wait(struct dlb_eventdev *dlb,\n \t\telse\n \t\t\texpected_value = 0;\n \n-\t\trte_power_monitor(monitor_addr, expected_value,\n-\t\t\t\t qe_mask.raw_qe[1], timeout + start_ticks,\n-\t\t\t\t sizeof(uint64_t));\n+\t\tpmc.addr = monitor_addr;\n+\t\tpmc.val = expected_value;\n+\t\tpmc.mask = qe_mask.raw_qe[1];\n+\t\tpmc.data_sz = sizeof(uint64_t);\n+\n+\t\trte_power_monitor(&pmc, timeout + start_ticks);\n \n \t\tDLB_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);\n \t} else {\ndiff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c\nindex 86724863f2..c9a8a02278 100644\n--- a/drivers/event/dlb2/dlb2.c\n+++ b/drivers/event/dlb2/dlb2.c\n@@ -2870,6 +2870,7 @@ dlb2_dequeue_wait(struct dlb2_eventdev *dlb2,\n \tif (elapsed_ticks >= timeout) {\n \t\treturn 1;\n \t} else if (dlb2->umwait_allowed) {\n+\t\tstruct rte_power_monitor_cond pmc;\n \t\tvolatile struct dlb2_dequeue_qe *cq_base;\n \t\tunion {\n \t\t\tuint64_t raw_qe[2];\n@@ -2890,9 +2891,12 @@ dlb2_dequeue_wait(struct dlb2_eventdev *dlb2,\n \t\telse\n \t\t\texpected_value = 0;\n \n-\t\trte_power_monitor(monitor_addr, expected_value,\n-\t\t\t\t qe_mask.raw_qe[1], timeout + start_ticks,\n-\t\t\t\t sizeof(uint64_t));\n+\t\tpmc.addr = monitor_addr;\n+\t\tpmc.val = expected_value;\n+\t\tpmc.mask = qe_mask.raw_qe[1];\n+\t\tpmc.data_sz = sizeof(uint64_t);\n+\n+\t\trte_power_monitor(&pmc, timeout + start_ticks);\n \n \t\tDLB2_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);\n \t} else {\ndiff --git a/lib/librte_eal/arm/rte_power_intrinsics.c b/lib/librte_eal/arm/rte_power_intrinsics.c\nindex 7e7552fa8a..5f1caaf25b 100644\n--- a/lib/librte_eal/arm/rte_power_intrinsics.c\n+++ b/lib/librte_eal/arm/rte_power_intrinsics.c\n@@ -8,15 +8,11 @@\n * This function is not supported on ARM.\n */\n int\n-rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz)\n+rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp)\n {\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(pmc);\n \tRTE_SET_USED(tsc_timestamp);\n-\tRTE_SET_USED(data_sz);\n \n \treturn -ENOTSUP;\n }\n@@ -25,16 +21,12 @@ rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n * This function is not supported on ARM.\n */\n int\n-rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n+rte_power_monitor_sync(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp, rte_spinlock_t *lck)\n {\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(pmc);\n \tRTE_SET_USED(tsc_timestamp);\n \tRTE_SET_USED(lck);\n-\tRTE_SET_USED(data_sz);\n \n \treturn -ENOTSUP;\n }\ndiff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h\nindex 37e4ec0414..3ad53068d5 100644\n--- a/lib/librte_eal/include/generic/rte_power_intrinsics.h\n+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h\n@@ -18,6 +18,18 @@\n * which are architecture-dependent.\n */\n \n+struct rte_power_monitor_cond {\n+\tvolatile void *addr; /**< Address to monitor for changes */\n+\tuint64_t val; /**< Before attempting the monitoring, the address\n+\t * may be read and compared against this value.\n+\t **/\n+\tuint64_t mask; /**< 64-bit mask to extract current value from addr */\n+\tuint8_t data_sz; /**< Data size (in bytes) that will be used to compare\n+\t * expected value with the memory address. Can be 1,\n+\t * 2, 4, or 8. Supplying any other value will lead to\n+\t * undefined result. */\n+};\n+\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change without prior notice\n@@ -35,20 +47,11 @@\n * @warning It is responsibility of the user to check if this function is\n * supported at runtime using `rte_cpu_get_intrinsics_support()` API call.\n *\n- * @param p\n- * Address to monitor for changes.\n- * @param expected_value\n- * Before attempting the monitoring, the `p` address may be read and compared\n- * against this value. If `value_mask` is zero, this step will be skipped.\n- * @param value_mask\n- * The 64-bit mask to use to extract current value from `p`.\n+ * @param pmc\n+ * The monitoring condition structure.\n * @param tsc_timestamp\n * Maximum TSC timestamp to wait for. Note that the wait behavior is\n * architecture-dependent.\n- * @param data_sz\n- * Data size (in bytes) that will be used to compare expected value with the\n- * memory address. Can be 1, 2, 4 or 8. Supplying any other value will lead\n- * to undefined result.\n *\n * @return\n * 0 on success\n@@ -56,10 +59,8 @@\n * -ENOTSUP if unsupported\n */\n __rte_experimental\n-int rte_power_monitor(const volatile void *p,\n-\t\tconst uint64_t expected_value, const uint64_t value_mask,\n-\t\tconst uint64_t tsc_timestamp, const uint8_t data_sz);\n-\n+int rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp);\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change without prior notice\n@@ -80,20 +81,11 @@ int rte_power_monitor(const volatile void *p,\n * @warning It is responsibility of the user to check if this function is\n * supported at runtime using `rte_cpu_get_intrinsics_support()` API call.\n *\n- * @param p\n- * Address to monitor for changes.\n- * @param expected_value\n- * Before attempting the monitoring, the `p` address may be read and compared\n- * against this value. If `value_mask` is zero, this step will be skipped.\n- * @param value_mask\n- * The 64-bit mask to use to extract current value from `p`.\n+ * @param pmc\n+ * The monitoring condition structure.\n * @param tsc_timestamp\n * Maximum TSC timestamp to wait for. Note that the wait behavior is\n * architecture-dependent.\n- * @param data_sz\n- * Data size (in bytes) that will be used to compare expected value with the\n- * memory address. Can be 1, 2, 4 or 8. Supplying any other value will lead\n- * to undefined result.\n * @param lck\n * A spinlock that must be locked before entering the function, will be\n * unlocked while the CPU is sleeping, and will be locked again once the CPU\n@@ -105,10 +97,8 @@ int rte_power_monitor(const volatile void *p,\n * -ENOTSUP if unsupported\n */\n __rte_experimental\n-int rte_power_monitor_sync(const volatile void *p,\n-\t\tconst uint64_t expected_value, const uint64_t value_mask,\n-\t\tconst uint64_t tsc_timestamp, const uint8_t data_sz,\n-\t\trte_spinlock_t *lck);\n+int rte_power_monitor_sync(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp, rte_spinlock_t *lck);\n \n /**\n * @warning\ndiff --git a/lib/librte_eal/ppc/rte_power_intrinsics.c b/lib/librte_eal/ppc/rte_power_intrinsics.c\nindex 929e0611b0..5e5a1fff5a 100644\n--- a/lib/librte_eal/ppc/rte_power_intrinsics.c\n+++ b/lib/librte_eal/ppc/rte_power_intrinsics.c\n@@ -8,15 +8,11 @@\n * This function is not supported on PPC64.\n */\n int\n-rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz)\n+rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp)\n {\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(pmc);\n \tRTE_SET_USED(tsc_timestamp);\n-\tRTE_SET_USED(data_sz);\n \n \treturn -ENOTSUP;\n }\n@@ -25,16 +21,12 @@ rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n * This function is not supported on PPC64.\n */\n int\n-rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n+rte_power_monitor_sync(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp, rte_spinlock_t *lck)\n {\n-\tRTE_SET_USED(p);\n-\tRTE_SET_USED(expected_value);\n-\tRTE_SET_USED(value_mask);\n+\tRTE_SET_USED(pmc);\n \tRTE_SET_USED(tsc_timestamp);\n \tRTE_SET_USED(lck);\n-\tRTE_SET_USED(data_sz);\n \n \treturn -ENOTSUP;\n }\ndiff --git a/lib/librte_eal/x86/rte_power_intrinsics.c b/lib/librte_eal/x86/rte_power_intrinsics.c\nindex 2a38440bec..6be5c8b9f1 100644\n--- a/lib/librte_eal/x86/rte_power_intrinsics.c\n+++ b/lib/librte_eal/x86/rte_power_intrinsics.c\n@@ -46,9 +46,8 @@ __check_val_size(const uint8_t sz)\n * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n */\n int\n-rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz)\n+rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp)\n {\n \tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n \tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n@@ -57,7 +56,10 @@ rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n \tif (!wait_supported)\n \t\treturn -ENOTSUP;\n \n-\tif (__check_val_size(data_sz) < 0)\n+\tif (pmc == NULL)\n+\t\treturn -EINVAL;\n+\n+\tif (__check_val_size(pmc->data_sz) < 0)\n \t\treturn -EINVAL;\n \n \t/*\n@@ -68,14 +70,15 @@ rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n \t/* set address for UMONITOR */\n \tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n \t\t\t:\n-\t\t\t: \"D\"(p));\n+\t\t\t: \"D\"(pmc->addr));\n \n-\tif (value_mask) {\n-\t\tconst uint64_t cur_value = __get_umwait_val(p, data_sz);\n-\t\tconst uint64_t masked = cur_value & value_mask;\n+\tif (pmc->mask) {\n+\t\tconst uint64_t cur_value = __get_umwait_val(\n+\t\t\t\tpmc->addr, pmc->data_sz);\n+\t\tconst uint64_t masked = cur_value & pmc->mask;\n \n \t\t/* if the masked value is already matching, abort */\n-\t\tif (masked == expected_value)\n+\t\tif (masked == pmc->val)\n \t\t\treturn 0;\n \t}\n \t/* execute UMWAIT */\n@@ -93,9 +96,8 @@ rte_power_monitor(const volatile void *p, const uint64_t expected_value,\n * Intel(R) 64 and IA-32 Architectures Software Developer's Manual.\n */\n int\n-rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n-\t\tconst uint64_t value_mask, const uint64_t tsc_timestamp,\n-\t\tconst uint8_t data_sz, rte_spinlock_t *lck)\n+rte_power_monitor_sync(const struct rte_power_monitor_cond *pmc,\n+\t\tconst uint64_t tsc_timestamp, rte_spinlock_t *lck)\n {\n \tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n \tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n@@ -104,7 +106,10 @@ rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n \tif (!wait_supported)\n \t\treturn -ENOTSUP;\n \n-\tif (__check_val_size(data_sz) < 0)\n+\tif (pmc == NULL || lck == NULL)\n+\t\treturn -EINVAL;\n+\n+\tif (__check_val_size(pmc->data_sz) < 0)\n \t\treturn -EINVAL;\n \n \t/*\n@@ -115,14 +120,15 @@ rte_power_monitor_sync(const volatile void *p, const uint64_t expected_value,\n \t/* set address for UMONITOR */\n \tasm volatile(\".byte 0xf3, 0x0f, 0xae, 0xf7;\"\n \t\t\t:\n-\t\t\t: \"D\"(p));\n+\t\t\t: \"D\"(pmc->addr));\n \n-\tif (value_mask) {\n-\t\tconst uint64_t cur_value = __get_umwait_val(p, data_sz);\n-\t\tconst uint64_t masked = cur_value & value_mask;\n+\tif (pmc->mask) {\n+\t\tconst uint64_t cur_value = __get_umwait_val(\n+\t\t\t\tpmc->addr, pmc->data_sz);\n+\t\tconst uint64_t masked = cur_value & pmc->mask;\n \n \t\t/* if the masked value is already matching, abort */\n-\t\tif (masked == expected_value)\n+\t\tif (masked == pmc->val)\n \t\t\treturn 0;\n \t}\n \trte_spinlock_unlock(lck);\n", "prefixes": [ "v16", "03/11" ] }