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GET /api/patches/86423/?format=api
{ "id": 86423, "url": "http://patchwork.dpdk.org/api/patches/86423/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/9e48ffbd9baada13231f961ae46b75a5a664ea1b.1610473000.git.anatoly.burakov@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<9e48ffbd9baada13231f961ae46b75a5a664ea1b.1610473000.git.anatoly.burakov@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/9e48ffbd9baada13231f961ae46b75a5a664ea1b.1610473000.git.anatoly.burakov@intel.com", "date": "2021-01-12T17:37:13", "name": "[v16,05/11] eal: add monitor wakeup function", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "90f395051b5636851b2662e0bc5674a6d935b643", "submitter": { "id": 4, "url": "http://patchwork.dpdk.org/api/people/4/?format=api", "name": "Anatoly Burakov", "email": "anatoly.burakov@intel.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/9e48ffbd9baada13231f961ae46b75a5a664ea1b.1610473000.git.anatoly.burakov@intel.com/mbox/", "series": [ { "id": 14673, "url": "http://patchwork.dpdk.org/api/series/14673/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=14673", "date": "2021-01-12T17:37:08", "name": "Add PMD power management", "version": 16, "mbox": "http://patchwork.dpdk.org/series/14673/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/86423/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/86423/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C1561A04B5;\n\tTue, 12 Jan 2021 18:38:10 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 813A1140ECD;\n\tTue, 12 Jan 2021 18:37:38 +0100 (CET)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 8D658140ECC\n for <dev@dpdk.org>; Tue, 12 Jan 2021 18:37:37 +0100 (CET)", "from fmsmga001.fm.intel.com ([10.253.24.23])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 12 Jan 2021 09:37:37 -0800", "from silpixa00399498.ir.intel.com (HELO\n silpixa00399498.ger.corp.intel.com) ([10.237.222.179])\n by fmsmga001.fm.intel.com with ESMTP; 12 Jan 2021 09:37:34 -0800" ], "IronPort-SDR": [ "\n RuhWt9H3PjNs1qevnZfPcXxPn5uaSR+praHL4mQQQ/XH2wAhPHPQ8KQlNZAw4jiO6NzDze/NGB\n dfG3fWEfiijw==", "\n fubdUxPWh2UiSPm036RbIEFa4EF52PtxpJjPL7rrW7OETb/o6zsX+cWOVPPbIYUfBmU3E59fwq\n n6CLg3mvdNyw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6000,8403,9862\"; a=\"175498035\"", "E=Sophos;i=\"5.79,342,1602572400\"; d=\"scan'208\";a=\"175498035\"", "E=Sophos;i=\"5.79,342,1602572400\"; d=\"scan'208\";a=\"464604205\"" ], "X-ExtLoop1": "1", "From": "Anatoly Burakov <anatoly.burakov@intel.com>", "To": "dev@dpdk.org", "Cc": "Jerin Jacob <jerinj@marvell.com>, Ruifeng Wang <ruifeng.wang@arm.com>,\n Jan Viktorin <viktorin@rehivetech.com>,\n David Christensen <drc@linux.vnet.ibm.com>, Ray Kinsella <mdr@ashroe.eu>,\n Neil Horman <nhorman@tuxdriver.com>,\n Bruce Richardson <bruce.richardson@intel.com>,\n Konstantin Ananyev <konstantin.ananyev@intel.com>, thomas@monjalon.net,\n timothy.mcdaniel@intel.com, david.hunt@intel.com, chris.macnamara@intel.com", "Date": "Tue, 12 Jan 2021 17:37:13 +0000", "Message-Id": "\n <9e48ffbd9baada13231f961ae46b75a5a664ea1b.1610473000.git.anatoly.burakov@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<cover.1610473000.git.anatoly.burakov@intel.com>", "References": "<cover.1610377084.git.anatoly.burakov@intel.com>\n <cover.1610473000.git.anatoly.burakov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v16 05/11] eal: add monitor wakeup function", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Now that we have everything in a C file, we can store the information\nabout our sleep, and have a native mechanism to wake up the sleeping\ncore. This mechanism would however only wake up a core that's sleeping\nwhile monitoring - waking up from `rte_power_pause` won't work.\n\nSigned-off-by: Anatoly Burakov <anatoly.burakov@intel.com>\n---\n\nNotes:\n v16:\n - Improve error handling\n - Take a lock before UMONITOR\n \n v13:\n - Add comments around wakeup code to explain what it does\n - Add lcore_id parameter checking to prevent buffer overrun\n\n lib/librte_eal/arm/rte_power_intrinsics.c | 9 ++\n .../include/generic/rte_power_intrinsics.h | 16 +++\n lib/librte_eal/ppc/rte_power_intrinsics.c | 9 ++\n lib/librte_eal/version.map | 1 +\n lib/librte_eal/x86/rte_power_intrinsics.c | 98 ++++++++++++++++++-\n 5 files changed, 132 insertions(+), 1 deletion(-)", "diff": "diff --git a/lib/librte_eal/arm/rte_power_intrinsics.c b/lib/librte_eal/arm/rte_power_intrinsics.c\nindex 8d271dc0c1..5a24c13913 100644\n--- a/lib/librte_eal/arm/rte_power_intrinsics.c\n+++ b/lib/librte_eal/arm/rte_power_intrinsics.c\n@@ -27,3 +27,12 @@ rte_power_pause(const uint64_t tsc_timestamp)\n \n \treturn -ENOTSUP;\n }\n+\n+/**\n+ * This function is not supported on ARM.\n+ */\n+void\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tRTE_SET_USED(lcore_id);\n+}\ndiff --git a/lib/librte_eal/include/generic/rte_power_intrinsics.h b/lib/librte_eal/include/generic/rte_power_intrinsics.h\nindex 85343bc9eb..6109d28faa 100644\n--- a/lib/librte_eal/include/generic/rte_power_intrinsics.h\n+++ b/lib/librte_eal/include/generic/rte_power_intrinsics.h\n@@ -62,6 +62,22 @@ __rte_experimental\n int rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \t\tconst uint64_t tsc_timestamp);\n \n+/**\n+ * @warning\n+ * @b EXPERIMENTAL: this API may change without prior notice\n+ *\n+ * Wake up a specific lcore that is in a power optimized state and is monitoring\n+ * an address.\n+ *\n+ * @note This function will *not* wake up a core that is in a power optimized\n+ * state due to calling `rte_power_pause`.\n+ *\n+ * @param lcore_id\n+ * Lcore ID of a sleeping thread.\n+ */\n+__rte_experimental\n+int rte_power_monitor_wakeup(const unsigned int lcore_id);\n+\n /**\n * @warning\n * @b EXPERIMENTAL: this API may change without prior notice\ndiff --git a/lib/librte_eal/ppc/rte_power_intrinsics.c b/lib/librte_eal/ppc/rte_power_intrinsics.c\nindex f7862ea324..7e334f7cf0 100644\n--- a/lib/librte_eal/ppc/rte_power_intrinsics.c\n+++ b/lib/librte_eal/ppc/rte_power_intrinsics.c\n@@ -27,3 +27,12 @@ rte_power_pause(const uint64_t tsc_timestamp)\n \n \treturn -ENOTSUP;\n }\n+\n+/**\n+ * This function is not supported on PPC64.\n+ */\n+void\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tRTE_SET_USED(lcore_id);\n+}\ndiff --git a/lib/librte_eal/version.map b/lib/librte_eal/version.map\nindex 1fcd1d3bed..fce90a112f 100644\n--- a/lib/librte_eal/version.map\n+++ b/lib/librte_eal/version.map\n@@ -406,6 +406,7 @@ EXPERIMENTAL {\n \n \t# added in 21.02\n \trte_power_monitor;\n+\trte_power_monitor_wakeup;\n \trte_power_pause;\n \trte_thread_tls_key_create;\n \trte_thread_tls_key_delete;\ndiff --git a/lib/librte_eal/x86/rte_power_intrinsics.c b/lib/librte_eal/x86/rte_power_intrinsics.c\nindex 29247d8638..a9e1689f75 100644\n--- a/lib/librte_eal/x86/rte_power_intrinsics.c\n+++ b/lib/librte_eal/x86/rte_power_intrinsics.c\n@@ -2,8 +2,31 @@\n * Copyright(c) 2020 Intel Corporation\n */\n \n+#include <rte_common.h>\n+#include <rte_lcore.h>\n+#include <rte_spinlock.h>\n+\n #include \"rte_power_intrinsics.h\"\n \n+/*\n+ * Per-lcore structure holding current status of C0.2 sleeps.\n+ */\n+static struct power_wait_status {\n+\trte_spinlock_t lock;\n+\tvolatile void *monitor_addr; /**< NULL if not currently sleeping */\n+} __rte_cache_aligned wait_status[RTE_MAX_LCORE];\n+\n+static inline void\n+__umwait_wakeup(volatile void *addr)\n+{\n+\tuint64_t val;\n+\n+\t/* trigger a write but don't change the value */\n+\tval = __atomic_load_n((volatile uint64_t *)addr, __ATOMIC_RELAXED);\n+\t__atomic_compare_exchange_n((volatile uint64_t *)addr, &val, val, 0,\n+\t\t\t__ATOMIC_RELAXED, __ATOMIC_RELAXED);\n+}\n+\n static bool wait_supported;\n \n static inline uint64_t\n@@ -51,17 +74,29 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n {\n \tconst uint32_t tsc_l = (uint32_t)tsc_timestamp;\n \tconst uint32_t tsc_h = (uint32_t)(tsc_timestamp >> 32);\n+\tconst unsigned int lcore_id = rte_lcore_id();\n+\tstruct power_wait_status *s;\n \n \t/* prevent user from running this instruction if it's not supported */\n \tif (!wait_supported)\n \t\treturn -ENOTSUP;\n \n+\t/* prevent non-EAL thread from using this API */\n+\tif (lcore_id >= RTE_MAX_LCORE)\n+\t\treturn -EINVAL;\n+\n \tif (pmc == NULL)\n \t\treturn -EINVAL;\n \n \tif (__check_val_size(pmc->data_sz) < 0)\n \t\treturn -EINVAL;\n \n+\ts = &wait_status[lcore_id];\n+\n+\t/* update sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = pmc->addr;\n+\n \t/*\n \t * we're using raw byte codes for now as only the newest compiler\n \t * versions support this instruction natively.\n@@ -72,21 +107,37 @@ rte_power_monitor(const struct rte_power_monitor_cond *pmc,\n \t\t\t:\n \t\t\t: \"D\"(pmc->addr));\n \n+\t/* now that we've put this address into monitor, we can unlock */\n+\trte_spinlock_unlock(&s->lock);\n+\n+\t/* if we have a comparison mask, we might not need to sleep at all */\n \tif (pmc->mask) {\n \t\tconst uint64_t cur_value = __get_umwait_val(\n \t\t\t\tpmc->addr, pmc->data_sz);\n \t\tconst uint64_t masked = cur_value & pmc->mask;\n \n \t\t/* if the masked value is already matching, abort */\n-\t\tif (masked == pmc->val)\n+\t\tif (masked == pmc->val) {\n+\t\t\t/* erase sleep address */\n+\t\t\trte_spinlock_lock(&s->lock);\n+\t\t\ts->monitor_addr = NULL;\n+\t\t\trte_spinlock_unlock(&s->lock);\n+\n \t\t\treturn 0;\n+\t\t}\n \t}\n+\n \t/* execute UMWAIT */\n \tasm volatile(\".byte 0xf2, 0x0f, 0xae, 0xf7;\"\n \t\t\t: /* ignore rflags */\n \t\t\t: \"D\"(0), /* enter C0.2 */\n \t\t\t \"a\"(tsc_l), \"d\"(tsc_h));\n \n+\t/* erase sleep address */\n+\trte_spinlock_lock(&s->lock);\n+\ts->monitor_addr = NULL;\n+\trte_spinlock_unlock(&s->lock);\n+\n \treturn 0;\n }\n \n@@ -122,3 +173,48 @@ RTE_INIT(rte_power_intrinsics_init) {\n \tif (i.power_monitor && i.power_pause)\n \t\twait_supported = 1;\n }\n+\n+int\n+rte_power_monitor_wakeup(const unsigned int lcore_id)\n+{\n+\tstruct power_wait_status *s;\n+\n+\t/* prevent user from running this instruction if it's not supported */\n+\tif (!wait_supported)\n+\t\treturn -ENOTSUP;\n+\n+\t/* prevent buffer overrun */\n+\tif (lcore_id >= RTE_MAX_LCORE)\n+\t\treturn -EINVAL;\n+\n+\ts = &wait_status[lcore_id];\n+\n+\t/*\n+\t * There is a race condition between sleep, wakeup and locking, but we\n+\t * don't need to handle it.\n+\t *\n+\t * Possible situations:\n+\t *\n+\t * 1. T1 locks, sets address, unlocks\n+\t * 2. T2 locks, triggers wakeup, unlocks\n+\t * 3. T1 sleeps\n+\t *\n+\t * In this case, because T1 has already set the address for monitoring,\n+\t * we will wake up immediately even if T2 triggers wakeup before T1\n+\t * goes to sleep.\n+\t *\n+\t * 1. T1 locks, sets address, unlocks, goes to sleep, and wakes up\n+\t * 2. T2 locks, triggers wakeup, and unlocks\n+\t * 3. T1 locks, erases address, and unlocks\n+\t *\n+\t * In this case, since we've already woken up, the \"wakeup\" was\n+\t * unneeded, and since T1 is still waiting on T2 releasing the lock, the\n+\t * wakeup address is still valid so it's perfectly safe to write it.\n+\t */\n+\trte_spinlock_lock(&s->lock);\n+\tif (s->monitor_addr != NULL)\n+\t\t__umwait_wakeup(s->monitor_addr);\n+\trte_spinlock_unlock(&s->lock);\n+\n+\treturn 0;\n+}\n", "prefixes": [ "v16", "05/11" ] }