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{
    "id": 88167,
    "url": "http://patchwork.dpdk.org/api/patches/88167/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210224155553.26893-6-kalesh-anakkur.purayil@broadcom.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210224155553.26893-6-kalesh-anakkur.purayil@broadcom.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210224155553.26893-6-kalesh-anakkur.purayil@broadcom.com",
    "date": "2021-02-24T15:55:47",
    "name": "[05/11] net/bnxt: update HWRM structures",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "cc3e242ca6292cebe512773fe3274aab83573a2a",
    "submitter": {
        "id": 1479,
        "url": "http://patchwork.dpdk.org/api/people/1479/?format=api",
        "name": "Kalesh A P",
        "email": "kalesh-anakkur.purayil@broadcom.com"
    },
    "delegate": {
        "id": 1766,
        "url": "http://patchwork.dpdk.org/api/users/1766/?format=api",
        "username": "ajitkhaparde",
        "first_name": "Ajit",
        "last_name": "Khaparde",
        "email": "ajit.khaparde@broadcom.com"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210224155553.26893-6-kalesh-anakkur.purayil@broadcom.com/mbox/",
    "series": [
        {
            "id": 15364,
            "url": "http://patchwork.dpdk.org/api/series/15364/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=15364",
            "date": "2021-02-24T15:55:42",
            "name": "bnxt fixes",
            "version": 1,
            "mbox": "http://patchwork.dpdk.org/series/15364/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/88167/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/88167/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id E2100A054F;\n\tWed, 24 Feb 2021 16:34:14 +0100 (CET)",
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        ],
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        "From": "Kalesh A P <kalesh-anakkur.purayil@broadcom.com>",
        "To": "dev@dpdk.org",
        "Cc": "ferruh.yigit@intel.com,\n\tajit.khaparde@broadcom.com",
        "Date": "Wed, 24 Feb 2021 21:25:47 +0530",
        "Message-Id": "<20210224155553.26893-6-kalesh-anakkur.purayil@broadcom.com>",
        "X-Mailer": "git-send-email 2.10.1",
        "In-Reply-To": "<20210224155553.26893-1-kalesh-anakkur.purayil@broadcom.com>",
        "References": "<20210224155553.26893-1-kalesh-anakkur.purayil@broadcom.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain; charset=y",
        "Content-Transfer-Encoding": "8bit",
        "Subject": "[dpdk-dev] [PATCH 05/11] net/bnxt: update HWRM structures",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "From: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>\n\nBrought in the latest hsi_struct_def_dpdk.h.\nHWRM API is now updated to version 1.10.2.15.\n\nSigned-off-by: Kalesh AP <kalesh-anakkur.purayil@broadcom.com>\nReviewed-by: Ajit Khaparde <ajit.khaparde@broadcom.com>\n---\n drivers/net/bnxt/hsi_struct_def_dpdk.h | 3720 +++++++++++++++++++++++++-------\n 1 file changed, 2968 insertions(+), 752 deletions(-)",
    "diff": "diff --git a/drivers/net/bnxt/hsi_struct_def_dpdk.h b/drivers/net/bnxt/hsi_struct_def_dpdk.h\nindex b3980c1..a039914 100644\n--- a/drivers/net/bnxt/hsi_struct_def_dpdk.h\n+++ b/drivers/net/bnxt/hsi_struct_def_dpdk.h\n@@ -269,6 +269,7 @@ struct cmd_nums {\n \t */\n \tuint16_t\treq_type;\n \t#define HWRM_VER_GET                              UINT32_C(0x0)\n+\t#define HWRM_FUNC_ECHO_RESPONSE                   UINT32_C(0xb)\n \t#define HWRM_ERROR_RECOVERY_QCFG                  UINT32_C(0xc)\n \t#define HWRM_FUNC_DRV_IF_CHANGE                   UINT32_C(0xd)\n \t#define HWRM_FUNC_BUF_UNRGTR                      UINT32_C(0xe)\n@@ -336,6 +337,8 @@ struct cmd_nums {\n \t#define HWRM_VNIC_PLCMODES_CFG                    UINT32_C(0x48)\n \t#define HWRM_VNIC_PLCMODES_QCFG                   UINT32_C(0x49)\n \t#define HWRM_VNIC_QCAPS                           UINT32_C(0x4a)\n+\t/* Updates specific fields in RX VNIC structure */\n+\t#define HWRM_VNIC_UPDATE                          UINT32_C(0x4b)\n \t#define HWRM_RING_ALLOC                           UINT32_C(0x50)\n \t#define HWRM_RING_FREE                            UINT32_C(0x51)\n \t#define HWRM_RING_CMPL_RING_QAGGINT_PARAMS        UINT32_C(0x52)\n@@ -358,6 +361,9 @@ struct cmd_nums {\n \t#define HWRM_QUEUE_MPLS_QCAPS                     UINT32_C(0x80)\n \t#define HWRM_QUEUE_MPLSTC2PRI_QCFG                UINT32_C(0x81)\n \t#define HWRM_QUEUE_MPLSTC2PRI_CFG                 UINT32_C(0x82)\n+\t#define HWRM_QUEUE_VLANPRI_QCAPS                  UINT32_C(0x83)\n+\t#define HWRM_QUEUE_VLANPRI2PRI_QCFG               UINT32_C(0x84)\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG                UINT32_C(0x85)\n \t#define HWRM_CFA_L2_FILTER_ALLOC                  UINT32_C(0x90)\n \t#define HWRM_CFA_L2_FILTER_FREE                   UINT32_C(0x91)\n \t#define HWRM_CFA_L2_FILTER_CFG                    UINT32_C(0x92)\n@@ -397,6 +403,8 @@ struct cmd_nums {\n \t#define HWRM_PORT_TX_FIR_CFG                      UINT32_C(0xbb)\n \t#define HWRM_PORT_TX_FIR_QCFG                     UINT32_C(0xbc)\n \t#define HWRM_PORT_ECN_QSTATS                      UINT32_C(0xbd)\n+\t#define HWRM_FW_LIVEPATCH_QUERY                   UINT32_C(0xbe)\n+\t#define HWRM_FW_LIVEPATCH                         UINT32_C(0xbf)\n \t#define HWRM_FW_RESET                             UINT32_C(0xc0)\n \t#define HWRM_FW_QSTATUS                           UINT32_C(0xc1)\n \t#define HWRM_FW_HEALTH_CHECK                      UINT32_C(0xc2)\n@@ -625,6 +633,10 @@ struct cmd_nums {\n \t#define HWRM_FUNC_QSTATS_EXT                      UINT32_C(0x198)\n \t/* Queries extended statistics context */\n \t#define HWRM_STAT_EXT_CTX_QUERY                   UINT32_C(0x199)\n+\t/* Configure SoC packet DMA settings */\n+\t#define HWRM_FUNC_SPD_CFG                         UINT32_C(0x19a)\n+\t/* Query SoC packet DMA settings */\n+\t#define HWRM_FUNC_SPD_QCFG                        UINT32_C(0x19b)\n \t/* Experimental */\n \t#define HWRM_SELFTEST_QLIST                       UINT32_C(0x200)\n \t/* Experimental */\n@@ -652,6 +664,16 @@ struct cmd_nums {\n \t#define HWRM_MFG_FRU_EEPROM_WRITE                 UINT32_C(0x20a)\n \t/* Tells the fw to read the fru memory */\n \t#define HWRM_MFG_FRU_EEPROM_READ                  UINT32_C(0x20b)\n+\t/* Used to provision SoC software images */\n+\t#define HWRM_MFG_SOC_IMAGE                        UINT32_C(0x20c)\n+\t/* Retrieves the SoC status and image provisioning information */\n+\t#define HWRM_MFG_SOC_QSTATUS                      UINT32_C(0x20d)\n+\t/* Tells the fw to program the seeprom memory */\n+\t#define HWRM_MFG_PARAM_SEEPROM_SYNC               UINT32_C(0x20e)\n+\t/* Tells the fw to read the seeprom memory */\n+\t#define HWRM_MFG_PARAM_SEEPROM_READ               UINT32_C(0x20f)\n+\t/* Tells the fw to get the health of seeprom data */\n+\t#define HWRM_MFG_PARAM_SEEPROM_HEALTH             UINT32_C(0x210)\n \t/* Experimental */\n \t#define HWRM_TF                                   UINT32_C(0x2bc)\n \t/* Experimental */\n@@ -703,6 +725,8 @@ struct cmd_nums {\n \t/* Experimental */\n \t#define HWRM_TF_EM_DELETE                         UINT32_C(0x2eb)\n \t/* Experimental */\n+\t#define HWRM_TF_EM_HASH_INSERT                    UINT32_C(0x2ec)\n+\t/* Experimental */\n \t#define HWRM_TF_TCAM_SET                          UINT32_C(0x2f8)\n \t/* Experimental */\n \t#define HWRM_TF_TCAM_GET                          UINT32_C(0x2f9)\n@@ -960,10 +984,10 @@ struct hwrm_err_output {\n #define HWRM_TARGET_ID_TOOLS 0xFFFD\n #define HWRM_VERSION_MAJOR 1\n #define HWRM_VERSION_MINOR 10\n-#define HWRM_VERSION_UPDATE 1\n+#define HWRM_VERSION_UPDATE 2\n /* non-zero means beta version */\n-#define HWRM_VERSION_RSVD 70\n-#define HWRM_VERSION_STR \"1.10.1.70\"\n+#define HWRM_VERSION_RSVD 15\n+#define HWRM_VERSION_STR \"1.10.2.15\"\n \n /****************\n  * hwrm_ver_get *\n@@ -1350,18 +1374,34 @@ struct hwrm_ver_get_output {\n \t * If set to 1, it will indicate to host drivers that firmware is\n \t * not ready to start full blown HWRM commands. Host drivers should\n \t * re-try HWRM_VER_GET with some timeout period. The timeout period\n-\t * can be selected up to 5 seconds.\n+\t * can be selected up to 5 seconds. Host drivers should also check\n+\t * for dev_not_rdy_backing_store to identify if flag is set due to\n+\t * backing store not been available.\n \t * For Example, PCIe hot-plug:\n \t *     Hot plug timing is system dependent. It generally takes up to\n \t *     600 miliseconds for firmware to clear DEV_NOT_RDY flag.\n \t * If set to 0, device is ready to accept all HWRM commands.\n \t */\n-\t#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY       UINT32_C(0x1)\n+\t#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY \\\n+\t\tUINT32_C(0x1)\n \t/*\n \t * If set to 1, external version present.\n \t * If set to 0, external version not present.\n \t */\n-\t#define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL     UINT32_C(0x2)\n+\t#define HWRM_VER_GET_OUTPUT_FLAGS_EXT_VER_AVAIL \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Firmware sets this flag along with dev_not_rdy flag to indicate\n+\t * host drivers that it has not completed resource initialization\n+\t * required for data path operations. Host drivers should not send\n+\t * any HWRM command that requires data path resources. Firmware will\n+\t * fail those commands with HWRM_ERR_CODE_BUSY. Host drivers can retry\n+\t * those commands once both the flags are cleared.\n+\t * If this flag and dev_not_rdy flag are set to 0, device is ready\n+\t * to accept all HWRM commands.\n+\t */\n+\t#define HWRM_VER_GET_OUTPUT_FLAGS_DEV_NOT_RDY_BACKING_STORE \\\n+\t\tUINT32_C(0x4)\n \tuint8_t\tunused_0[2];\n \t/*\n \t * For backward compatibility this field must be set to 1.\n@@ -1613,7 +1653,7 @@ struct cfa_bds_write_cmd_data_msg {\n \tuint32_t\tdta[32];\n } __rte_packed;\n \n-/* cfa_bds_read_clr_cmd_data_msg (size:192b/24B) */\n+/* cfa_bds_read_clr_cmd_data_msg (size:256b/32B) */\n struct cfa_bds_read_clr_cmd_data_msg {\n \t/* This value selects the format for the mid-path command for the CFA. */\n \tuint8_t\topcode;\n@@ -1640,7 +1680,13 @@ struct cfa_bds_read_clr_cmd_data_msg {\n \tuint8_t\ttable_scope;\n \t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n \t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n-\tuint8_t\tunused0;\n+\t/*\n+\t * This value identifies the number of 32B units will be accessed.\n+\t * Always set the value to 1.\n+\t */\n+\tuint8_t\tdata_size;\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)\n+\t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_DATA_SIZE_SFT 0\n \t/* This is the 32B index into the selected table to access. */\n \tuint32_t\ttable_index;\n \t#define CFA_BDS_READ_CLR_CMD_DATA_MSG_TABLE_INDEX_MASK \\\n@@ -1659,7 +1705,8 @@ struct cfa_bds_read_clr_cmd_data_msg {\n \t * of data read when set to '1'.\n \t */\n \tuint16_t\tclear_mask;\n-\tuint16_t\tunused1[3];\n+\tuint16_t\tunused0[3];\n+\tuint16_t\tunused1[4];\n } __rte_packed;\n \n /* cfa_bds_em_insert_cmd_data_msg (size:1152b/144B) */\n@@ -1714,7 +1761,7 @@ struct cfa_bds_em_insert_cmd_data_msg {\n \tuint32_t\tdta[32];\n } __rte_packed;\n \n-/* cfa_bds_em_delete_cmd_data_msg (size:192b/24B) */\n+/* cfa_bds_em_delete_cmd_data_msg (size:256b/32B) */\n struct cfa_bds_em_delete_cmd_data_msg {\n \t/* This value selects the format for the mid-path command for the CFA. */\n \tuint8_t\topcode;\n@@ -1756,9 +1803,10 @@ struct cfa_bds_em_delete_cmd_data_msg {\n \t * the data_size field. The bd_cnt in the encapsulating BD must also be\n \t */\n \tuint64_t\tdta;\n+\tuint32_t\tunused1[2];\n } __rte_packed;\n \n-/* cfa_bds_invalidate_cmd_data_msg (size:64b/8B) */\n+/* cfa_bds_invalidate_cmd_data_msg (size:128b/16B) */\n struct cfa_bds_invalidate_cmd_data_msg {\n \t/* This value selects the format for the mid-path command for the CFA. */\n \tuint8_t\topcode;\n@@ -1786,12 +1834,16 @@ struct cfa_bds_invalidate_cmd_data_msg {\n \tuint8_t\ttable_scope;\n \t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_MASK UINT32_C(0x1f)\n \t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_SCOPE_SFT 0\n-\tuint8_t\tunused0;\n+\t/* This value specifies the number of cache lines to invalidate. */\n+\tuint8_t\tdata_size;\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_MASK UINT32_C(0x7)\n+\t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_DATA_SIZE_SFT 0\n \t/* This is the 32B index into the selected table to access. */\n \tuint32_t\ttable_index;\n \t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_MASK \\\n \t\tUINT32_C(0x3ffffff)\n \t#define CFA_BDS_INVALIDATE_CMD_DATA_MSG_TABLE_INDEX_SFT 0\n+\tuint32_t\tunused[2];\n } __rte_packed;\n \n /* cfa_bds_event_collect_cmd_data_msg (size:128b/16B) */\n@@ -2638,51 +2690,69 @@ struct tx_bd_long_hi {\n \t */\n \tuint32_t\tcfa_meta;\n \t/* When key=1, This is the VLAN tag VID value. */\n-\t#define TX_BD_LONG_CFA_META_VLAN_VID_MASK     UINT32_C(0xfff)\n-\t#define TX_BD_LONG_CFA_META_VLAN_VID_SFT      0\n+\t#define TX_BD_LONG_CFA_META_VLAN_VID_MASK        UINT32_C(0xfff)\n+\t#define TX_BD_LONG_CFA_META_VLAN_VID_SFT         0\n \t/* When key=1, This is the VLAN tag DE value. */\n-\t#define TX_BD_LONG_CFA_META_VLAN_DE           UINT32_C(0x1000)\n+\t#define TX_BD_LONG_CFA_META_VLAN_DE              UINT32_C(0x1000)\n \t/* When key=1, This is the VLAN tag PRI value. */\n-\t#define TX_BD_LONG_CFA_META_VLAN_PRI_MASK     UINT32_C(0xe000)\n-\t#define TX_BD_LONG_CFA_META_VLAN_PRI_SFT      13\n+\t#define TX_BD_LONG_CFA_META_VLAN_PRI_MASK        UINT32_C(0xe000)\n+\t#define TX_BD_LONG_CFA_META_VLAN_PRI_SFT         13\n \t/* When key=1, This is the VLAN tag TPID select value. */\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_MASK    UINT32_C(0x70000)\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_SFT     16\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_MASK       UINT32_C(0x70000)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_SFT        16\n \t/* 0x88a8 */\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8  (UINT32_C(0x0) << 16)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID88A8 \\\n+\t\t(UINT32_C(0x0) << 16)\n \t/* 0x8100 */\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100  (UINT32_C(0x1) << 16)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID8100 \\\n+\t\t(UINT32_C(0x1) << 16)\n \t/* 0x9100 */\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100  (UINT32_C(0x2) << 16)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9100 \\\n+\t\t(UINT32_C(0x2) << 16)\n \t/* 0x9200 */\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200  (UINT32_C(0x3) << 16)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9200 \\\n+\t\t(UINT32_C(0x3) << 16)\n \t/* 0x9300 */\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300  (UINT32_C(0x4) << 16)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPID9300 \\\n+\t\t(UINT32_C(0x4) << 16)\n \t/* Value programmed in CFA VLANTPID register. */\n-\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG   (UINT32_C(0x5) << 16)\n+\t#define TX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG \\\n+\t\t(UINT32_C(0x5) << 16)\n \t#define TX_BD_LONG_CFA_META_VLAN_TPID_LAST \\\n \t\tTX_BD_LONG_CFA_META_VLAN_TPID_TPIDCFG\n \t/* When key=1, This is the VLAN tag TPID select value. */\n-\t#define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK UINT32_C(0xff80000)\n-\t#define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT 19\n+\t#define TX_BD_LONG_CFA_META_VLAN_RESERVED_MASK   UINT32_C(0xff80000)\n+\t#define TX_BD_LONG_CFA_META_VLAN_RESERVED_SFT    19\n \t/*\n \t * This field identifies the type of edit to be performed\n \t * on the packet.\n \t *\n \t * This value must be valid on the first BD of a packet.\n \t */\n-\t#define TX_BD_LONG_CFA_META_KEY_MASK          UINT32_C(0xf0000000)\n-\t#define TX_BD_LONG_CFA_META_KEY_SFT           28\n+\t#define TX_BD_LONG_CFA_META_KEY_MASK             UINT32_C(0xf0000000)\n+\t#define TX_BD_LONG_CFA_META_KEY_SFT              28\n \t/* No editing */\n-\t#define TX_BD_LONG_CFA_META_KEY_NONE            (UINT32_C(0x0) << 28)\n+\t#define TX_BD_LONG_CFA_META_KEY_NONE \\\n+\t\t(UINT32_C(0x0) << 28)\n \t/*\n \t * - meta[17:16] - TPID select value (0 = 0x8100).\n \t * - meta[15:12] - PRI/DE value.\n \t * - meta[11:0] - VID value.\n \t */\n-\t#define TX_BD_LONG_CFA_META_KEY_VLAN_TAG        (UINT32_C(0x1) << 28)\n+\t#define TX_BD_LONG_CFA_META_KEY_VLAN_TAG \\\n+\t\t(UINT32_C(0x1) << 28)\n+\t/*\n+\t * Provide metadata\n+\t * - Wh+/SR - this option is not supported.\n+\t * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta\n+\t *   is set in the Lookup Table.\n+\t * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if\n+\t *   en_bd_meta is set in the Lookup Table.\n+\t */\n+\t#define TX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER \\\n+\t\t(UINT32_C(0x2) << 28)\n \t#define TX_BD_LONG_CFA_META_KEY_LAST \\\n-\t\tTX_BD_LONG_CFA_META_KEY_VLAN_TAG\n+\t\tTX_BD_LONG_CFA_META_KEY_METADATA_TRANSFER\n } __rte_packed;\n \n /*\n@@ -2912,16 +2982,19 @@ struct tx_bd_long_inline {\n \t */\n \tuint32_t\tcfa_meta;\n \t/* When key = 1, this is the VLAN tag VID value. */\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK     UINT32_C(0xfff)\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT      0\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_MASK        UINT32_C(0xfff)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_VID_SFT         0\n \t/* When key = 1, this is the VLAN tag DE value. */\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_DE           UINT32_C(0x1000)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_DE \\\n+\t\tUINT32_C(0x1000)\n \t/* When key = 1, this is the VLAN tag PRI value. */\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK     UINT32_C(0xe000)\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT      13\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_MASK \\\n+\t\tUINT32_C(0xe000)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_PRI_SFT         13\n \t/* When key = 1, this is the VLAN tag TPID select value. */\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK    UINT32_C(0x70000)\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT     16\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_MASK \\\n+\t\tUINT32_C(0x70000)\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_SFT        16\n \t/* 0x88a8 */\n \t#define TX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPID88A8 \\\n \t\t(UINT32_C(0x0) << 16)\n@@ -2944,7 +3017,7 @@ struct tx_bd_long_inline {\n \t\tTX_BD_LONG_INLINE_CFA_META_VLAN_TPID_TPIDCFG\n \t#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_MASK \\\n \t\tUINT32_C(0xff80000)\n-\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT 19\n+\t#define TX_BD_LONG_INLINE_CFA_META_VLAN_RESERVED_SFT    19\n \t/*\n \t * This field identifies the type of edit to be performed\n \t * on the packet.\n@@ -2953,7 +3026,7 @@ struct tx_bd_long_inline {\n \t */\n \t#define TX_BD_LONG_INLINE_CFA_META_KEY_MASK \\\n \t\tUINT32_C(0xf0000000)\n-\t#define TX_BD_LONG_INLINE_CFA_META_KEY_SFT           28\n+\t#define TX_BD_LONG_INLINE_CFA_META_KEY_SFT              28\n \t/* No editing */\n \t#define TX_BD_LONG_INLINE_CFA_META_KEY_NONE \\\n \t\t(UINT32_C(0x0) << 28)\n@@ -2964,8 +3037,18 @@ struct tx_bd_long_inline {\n \t */\n \t#define TX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG \\\n \t\t(UINT32_C(0x1) << 28)\n+\t/*\n+\t * Provide metadata\n+\t * - Wh+/SR - this option is not supported.\n+\t * - Thor - cfa_meta[15:0] is used for metadata output if en_bd_meta\n+\t *   is set in the Lookup Table.\n+\t * - SR2 - {4’d0, cfa_meta[27:0]} is used for metadata output if\n+\t *   en_bd_meta is set in the Lookup Table.\n+\t */\n+\t#define TX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER \\\n+\t\t(UINT32_C(0x2) << 28)\n \t#define TX_BD_LONG_INLINE_CFA_META_KEY_LAST \\\n-\t\tTX_BD_LONG_INLINE_CFA_META_KEY_VLAN_TAG\n+\t\tTX_BD_LONG_INLINE_CFA_META_KEY_METADATA_TRANSFER\n } __rte_packed;\n \n /* tx_bd_empty (size:128b/16B) */\n@@ -7373,9 +7456,15 @@ struct hwrm_async_event_cmpl {\n \t */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_PFC_WATCHDOG_CFG_CHANGE \\\n \t\tUINT32_C(0x41)\n+\t/*\n+\t * An echo request from the firmware. An echo response is expected by\n+\t * the firmware.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_ECHO_REQUEST \\\n+\t\tUINT32_C(0x42)\n \t/* Maximum Registrable event id. */\n \t#define HWRM_ASYNC_EVENT_CMPL_EVENT_ID_MAX_RGTR_EVENT_ID \\\n-\t\tUINT32_C(0x42)\n+\t\tUINT32_C(0x43)\n \t/*\n \t * A trace log message. This contains firmware trace logs string\n \t * embedded in the asynchronous message. This is an experimental\n@@ -8014,6 +8103,18 @@ struct hwrm_async_event_cmpl_reset_notify {\n \t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_ID_RESET_NOTIFY\n \t/* Event specific data. The data is for internal debug use only. */\n \tuint32_t\tevent_data2;\n+\t/*\n+\t * These bits indicate the status as being reported by the firmware.\n+\t * This value is exactly the same as status code in fw_status register.\n+\t * If the status code is equal to 0x8000, then the reset is initiated\n+\t * by the Host using the FW_RESET command when the FW is in a healthy\n+\t * state. If the status code is not equal to 0x8000, then the reset is\n+\t * initiated by the FW to recover from the error or FATAL state.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_MASK \\\n+\t\tUINT32_C(0xffff)\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA2_FW_STATUS_CODE_SFT \\\n+\t\t0\n \tuint8_t\topaque_v;\n \t/*\n \t * This value is written by the NIC such that it will be different\n@@ -8075,8 +8176,11 @@ struct hwrm_async_event_cmpl_reset_notify {\n \t/* A non-fatal firmware exception has occurred. */\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL \\\n \t\t(UINT32_C(0x3) << 8)\n+\t/* Fast reset */\n+\t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET \\\n+\t\t(UINT32_C(0x4) << 8)\n \t#define HWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_LAST \\\n-\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FW_EXCEPTION_NON_FATAL\n+\t\tHWRM_ASYNC_EVENT_CMPL_RESET_NOTIFY_EVENT_DATA1_REASON_CODE_FAST_RESET\n \t/*\n \t * Minimum time before driver should attempt access - units 100ms ticks.\n \t * Range 0-65535\n@@ -9511,6 +9615,54 @@ struct hwrm_async_event_cmpl_pfc_watchdog_cfg_change {\n \t\t8\n } __rte_packed;\n \n+/* hwrm_async_event_cmpl_echo_request (size:128b/16B) */\n+struct hwrm_async_event_cmpl_echo_request {\n+\tuint16_t\ttype;\n+\t/*\n+\t * This field indicates the exact type of the completion.\n+\t * By convention, the LSB identifies the length of the\n+\t * record in 16B units. Even values indicate 16B\n+\t * records. Odd values indicate 32B\n+\t * records.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_MASK \\\n+\t\tUINT32_C(0x3f)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_SFT             0\n+\t/* HWRM Asynchronous Event Information */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT \\\n+\t\tUINT32_C(0x2e)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_TYPE_HWRM_ASYNC_EVENT\n+\t/* Identifiers of events. */\n+\tuint16_t\tevent_id;\n+\t/*\n+\t * An echo request from the firmware. An echo response is expected by\n+\t * the firmware.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST \\\n+\t\tUINT32_C(0x42)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_LAST \\\n+\t\tHWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_EVENT_ID_ECHO_REQUEST\n+\t/* Event specific data that should be provided in the echo response */\n+\tuint32_t\tevent_data2;\n+\tuint8_t\topaque_v;\n+\t/*\n+\t * This value is written by the NIC such that it will be different\n+\t * for each pass through the completion queue. The even passes\n+\t * will write 1. The odd passes will write 0.\n+\t */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_V          UINT32_C(0x1)\n+\t/* opaque is 7 b */\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_MASK UINT32_C(0xfe)\n+\t#define HWRM_ASYNC_EVENT_CMPL_ECHO_REQUEST_OPAQUE_SFT 1\n+\t/* 8-lsb timestamp from POR (100-msec resolution) */\n+\tuint8_t\ttimestamp_lo;\n+\t/* 16-lsb timestamp from POR (100-msec resolution) */\n+\tuint16_t\ttimestamp_hi;\n+\t/* Event specific data that should be provided in the echo response */\n+\tuint32_t\tevent_data1;\n+} __rte_packed;\n+\n /* hwrm_async_event_cmpl_fw_trace_msg (size:128b/16B) */\n struct hwrm_async_event_cmpl_fw_trace_msg {\n \tuint16_t\ttype;\n@@ -11131,6 +11283,60 @@ struct hwrm_func_qcaps_output {\n \t */\n \t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_PPP_PUSH_MODE_SUPPORTED \\\n \t\tUINT32_C(0x80)\n+\t/*\n+\t * If set to 1, then this function doesn't have the privilege to\n+\t * configure the EVB mode of the port it uses.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_EVB_MODE_CFG_NOT_SUPPORTED \\\n+\t\tUINT32_C(0x100)\n+\t/*\n+\t * If set to 1, then the HW and FW support the SoC packet DMA\n+\t * datapath between SoC and NIC. This function can act as the\n+\t * HWRM communication transport agent on behalf of the SoC SPD\n+\t * software module. This capability is only advertised to the\n+\t * SoC PFs.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_SOC_SPD_SUPPORTED \\\n+\t\tUINT32_C(0x200)\n+\t/*\n+\t * If set to 1, then this function supports FW_LIVEPATCH for\n+\t * firmware livepatch commands.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FW_LIVEPATCH_SUPPORTED \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * When this bit is '1', it indicates that core firmware is\n+\t * capable of fast Reset.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_FAST_RESET_CAPABLE \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * When this bit is '1', it indicates that firmware and hardware\n+\t * are capable of updating tx_metadata via hwrm_ring_cfg command.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_TX_METADATA_CFG_CAPABLE \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * If set to 1, then the device can report the action\n+\t * needed to activate set nvm options.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_NVM_OPTION_ACTION_SUPPORTED \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n+\t * When this bit is '1', it indicates that the BD metadata feature\n+\t * is supported for this function.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_BD_METADATA_SUPPORTED \\\n+\t\tUINT32_C(0x4000)\n+\t/*\n+\t * When this bit is '1', it indicates that the echo request feature\n+\t * is supported for this function. If the driver registers for the\n+\t * echo request asynchronous event, then the firmware can send an\n+\t * unsolicited echo request to the driver and expect an echo\n+\t * response.\n+\t */\n+\t#define HWRM_FUNC_QCAPS_OUTPUT_FLAGS_EXT_ECHO_REQUEST_SUPPORTED \\\n+\t\tUINT32_C(0x8000)\n \t/* The maximum number of SCHQs supported by this device. */\n \tuint8_t\tmax_schqs;\n \tuint8_t\tmpc_chnls_cap;\n@@ -11294,6 +11500,8 @@ struct hwrm_func_qcfg_output {\n \t\tUINT32_C(0x10)\n \t/*\n \t * If set to 1, then multi-host mode is active for this function.\n+\t * The NIC is attached to two or more independent host systems\n+\t * through two or more PCIe endpoints.\n \t * If set to 0, then multi-host mode is inactive for this function\n \t * or not applicable for this device.\n \t */\n@@ -11348,6 +11556,24 @@ struct hwrm_func_qcfg_output {\n \t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_RING_MONITOR_ENABLED \\\n \t\tUINT32_C(0x800)\n \t/*\n+\t * If set to 1, then the firmware and all currently registered driver\n+\t * instances support fast reset. The fast reset support will be\n+\t * updated dynamically based on the driver interface advertisement.\n+\t * If set to 0, then the adapter is not currently able to initiate\n+\t * fast reset.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_FAST_RESET_ALLOWED \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n+\t * If set to 1, then multi-root mode is active for this function.\n+\t * The NIC is attached to a single host with a single operating\n+\t * system, but through two or more PCIe endpoints.\n+\t * If set to 0, then multi-root mode is inactive for this function\n+\t * or not applicable for this device.\n+\t */\n+\t#define HWRM_FUNC_QCFG_OUTPUT_FLAGS_MULTI_ROOT \\\n+\t\tUINT32_C(0x2000)\n+\t/*\n \t * This value is current MAC address configured for this\n \t * function. A value of 00-00-00-00-00-00 indicates no\n \t * MAC address is currently configured.\n@@ -11745,7 +11971,7 @@ struct hwrm_func_cfg_input {\n \t/*\n \t * Function ID of the function that is being\n \t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * If set to 0xFF... (All Fs), then the the configuration is\n \t * for the requesting function.\n \t */\n \tuint16_t\tfid;\n@@ -11962,6 +12188,20 @@ struct hwrm_func_cfg_input {\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_FLAGS_PPP_PUSH_MODE_DISABLE \\\n \t\tUINT32_C(0x10000000)\n+\t/*\n+\t * If this bit is set to 1, the driver is requesting FW to enable\n+\t * the BD_METADATA feature for this function. The FW returns error\n+\t * on this request if the TX_METADATA is enabled for this function.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_ENABLE \\\n+\t\tUINT32_C(0x20000000)\n+\t/*\n+\t * If this bit is set to 1, the driver is requesting FW to disable\n+\t * the BD_METADATA feature for this function. The FW returns error\n+\t * on this request if the TX_METADATA is enabled for this function.\n+\t */\n+\t#define HWRM_FUNC_CFG_INPUT_FLAGS_BD_METADATA_DISABLE \\\n+\t\tUINT32_C(0x40000000)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the mtu field to be\n@@ -12322,16 +12562,27 @@ struct hwrm_func_cfg_input {\n \t */\n \tuint8_t\tallowed_vlan_pris;\n \t/*\n-\t * The HWRM shall allow a PF driver to change EVB mode for the\n-\t * partition it belongs to.\n-\t * The HWRM shall not allow a VF driver to change the EVB mode.\n-\t * The HWRM shall take into account the switching of EVB mode\n-\t * from one to another and reconfigure hardware resources as\n-\t * appropriately.\n-\t * The switching from VEB to VEPA mode requires\n-\t * the disabling of the loopback traffic. Additionally,\n-\t * source knock outs are handled differently in VEB and VEPA\n-\t * modes.\n+\t * The evb_mode is configured on a per port basis. The default evb_mode\n+\t * is configured based on the NVM EVB mode setting upon firmware\n+\t * initialization. The HWRM allows a PF driver to change EVB mode for a\n+\t * port used by the PF only when one of the following conditions is\n+\t * satisfied.\n+\t * 1. The current operating mode is single function mode.\n+\t *    (ie. one PF per port)\n+\t * 2. For SmartNIC, any one of the PAXC PFs is permitted to change the\n+\t *    EVB mode of the port used by the PAXC PF. None of the X86 PFs\n+\t *    should have privileges.\n+\t * The HWRM doesn't permit any PFs to change the underlying EVB mode\n+\t * when running as MHB or NPAR mode in performance NIC configuration.\n+\t * The HWRM doesn't permit a VF driver to change the EVB mode.\n+\t * Once the HWRM determines a function doesn't meet the conditions\n+\t * to configure the EVB mode, it sets the evb_mode_cfg_not_supported\n+\t * flag in HWRM_FUNC_QCAPS command response for the function.\n+\t * The HWRM takes into account the switching of EVB mode from one to\n+\t * another and reconfigure hardware resources as reqiured. The\n+\t * switching from VEB to VEPA mode requires the disabling of the\n+\t * loopback traffic. Additionally, source knockouts are handled\n+\t * differently in VEB and VEPA modes.\n \t */\n \tuint8_t\tevb_mode;\n \t/* No Edge Virtual Bridging (EVB) */\n@@ -12420,7 +12671,7 @@ struct hwrm_func_cfg_input {\n \t/*\n \t * When this bit is '1', the caller requests to disable a MPC\n \t * channel with destination to the TX configurable flow processing\n-\t * block. When this bit is ‘0’, this flag has no effect.\n+\t * block block. When this bit is ‘0’, this flag has no effect.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_TE_CFA_DISABLE \\\n \t\tUINT32_C(0x20)\n@@ -12434,7 +12685,7 @@ struct hwrm_func_cfg_input {\n \t/*\n \t * When this bit is '1', the caller requests to disable a MPC\n \t * channel with destination to the RX configurable flow processing\n-\t * block. When this bit is ‘0’, this flag has no effect.\n+\t * block block. When this bit is ‘0’, this flag has no effect.\n \t */\n \t#define HWRM_FUNC_CFG_INPUT_MPC_CHNLS_RE_CFA_DISABLE \\\n \t\tUINT32_C(0x80)\n@@ -13007,6 +13258,19 @@ struct hwrm_func_drv_rgtr_input {\n \t */\n \t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_MASTER_SUPPORT \\\n \t\tUINT32_C(0x40)\n+\t/*\n+\t * When this bit is 1, the function is indicating the support of the\n+\t * fast reset capability. Fast reset support will be used by\n+\t * firmware only if all the driver instances support fast reset\n+\t * process. By setting this bit, driver is indicating support for\n+\t * corresponding async event completion message. These will be\n+\t * delivered to the driver even if they did not register for it.\n+\t * If supported, after receiving reset notify async event with fast\n+\t * reset flag set in event data1, then all the drivers have to tear\n+\t * down their resources without sending any HWRM commands to FW.\n+\t */\n+\t#define HWRM_FUNC_DRV_RGTR_INPUT_FLAGS_FAST_RESET_SUPPORT \\\n+\t\tUINT32_C(0x80)\n \tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the os_type field to be\n@@ -13810,7 +14074,7 @@ struct hwrm_func_backing_store_qcaps_input {\n \tuint64_t\tresp_addr;\n } __rte_packed;\n \n-/* hwrm_func_backing_store_qcaps_output (size:640b/80B) */\n+/* hwrm_func_backing_store_qcaps_output (size:704b/88B) */\n struct hwrm_func_backing_store_qcaps_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -13924,17 +14188,94 @@ struct hwrm_func_backing_store_qcaps_output {\n \t * before the first time context load.\n \t */\n \tuint8_t\tctx_kind_initializer;\n-\t/* Reserved for future. */\n-\tuint32_t\trsvd;\n-\t/* Reserved for future. */\n-\tuint16_t\trsvd1;\n+\t/*\n+\t * Specifies which context kinds need to be initialized with the\n+\t * ctx_kind_initializer.\n+\t */\n+\tuint16_t\tctx_init_mask;\n+\t/*\n+\t * If this bit is '1' then this context type should be initialized\n+\t * with the ctx_kind_initializer at the specified offset.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_QP \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * If this bit is '1' then this context type should be initialized\n+\t * with the ctx_kind_initializer at the specified offset.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_SRQ \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * If this bit is '1' then this context type should be initialized\n+\t * with the ctx_kind_initializer at the specified offset.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_CQ \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * If this bit is '1' then this context type should be initialized\n+\t * with the ctx_kind_initializer at the specified offset.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_VNIC \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * If this bit is '1' then this context type should be initialized\n+\t * with the ctx_kind_initializer at the specified offset.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_STAT \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * If this bit is '1' then this context type should be initialized\n+\t * with the ctx_kind_initializer at the specified offset.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCAPS_OUTPUT_CTX_INIT_MASK_MRAV \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * Specifies the doubleword offset of ctx_kind_initializer for this\n+\t * context type.\n+\t */\n+\tuint8_t\tqp_init_offset;\n+\t/*\n+\t * Specifies the doubleword offset of ctx_kind_initializer for this\n+\t * context type.\n+\t */\n+\tuint8_t\tsrq_init_offset;\n+\t/*\n+\t * Specifies the doubleword offset of ctx_kind_initializer for this\n+\t * context type.\n+\t */\n+\tuint8_t\tcq_init_offset;\n+\t/*\n+\t * Specifies the doubleword offset of ctx_kind_initializer for this\n+\t * context type.\n+\t */\n+\tuint8_t\tvnic_init_offset;\n \t/*\n \t * Count of TQM fastpath rings to be used for allocating backing store.\n \t * Backing store configuration must be specified for each TQM ring from\n \t * this count in `backing_store_cfg`.\n+\t * Only first 8 TQM FP rings will be advertised with this field.\n \t */\n \tuint8_t\ttqm_fp_rings_count;\n \t/*\n+\t * Specifies the doubleword offset of ctx_kind_initializer for this\n+\t * context type.\n+\t */\n+\tuint8_t\tstat_init_offset;\n+\t/*\n+\t * Specifies the doubleword offset of ctx_kind_initializer for this\n+\t * context type.\n+\t */\n+\tuint8_t\tmrav_init_offset;\n+\t/*\n+\t * Count of TQM extended fastpath rings to be used for allocating\n+\t * backing store beyond 8 rings(rings 9,10,11)\n+\t * Backing store configuration must be specified for each TQM ring from\n+\t * this count in `backing_store_cfg`.\n+\t */\n+\tuint8_t\ttqm_fp_rings_count_ext;\n+\t/* Reserved for future. */\n+\tuint8_t\trsvd[5];\n+\t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n \t * to indicate that the output has been completely written.\n@@ -13944,12 +14285,65 @@ struct hwrm_func_backing_store_qcaps_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/* tqm_fp_ring_cfg (size:128b/16B) */\n+struct tqm_fp_ring_cfg {\n+\t/* TQM ring page size and level. */\n+\tuint8_t\ttqm_ring_pg_size_tqm_ring_lvl;\n+\t/* TQM ring PBL indirect levels. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_SFT       0\n+\t/* PBL pointer is physical start address. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to\n+\t * PTE tables.\n+\t */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LAST \\\n+\t\tTQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_LVL_LVL_2\n+\t/* TQM ring page size. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_SFT   4\n+\t/* 4KB. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define TQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_LAST \\\n+\t\tTQM_FP_RING_CFG_TQM_RING_CFG_TQM_RING_PG_SIZE_PG_1G\n+\tuint8_t\tunused[3];\n+\t/* Number of TQM ring entries. */\n+\tuint32_t\ttqm_ring_num_entries;\n+\t/* TQM ring page directory. */\n+\tuint64_t\ttqm_ring_page_dir;\n+} __rte_packed;\n+\n /*******************************\n  * hwrm_func_backing_store_cfg *\n  *******************************/\n \n \n-/* hwrm_func_backing_store_cfg_input (size:2048b/256B) */\n+/* hwrm_func_backing_store_cfg_input (size:2432b/304B) */\n struct hwrm_func_backing_store_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -14091,6 +14485,24 @@ struct hwrm_func_backing_store_cfg_input {\n \t */\n \t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TIM \\\n \t\tUINT32_C(0x8000)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring8 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING8 \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring9 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING9 \\\n+\t\tUINT32_C(0x20000)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring10 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_ENABLES_TQM_RING10 \\\n+\t\tUINT32_C(0x40000)\n \t/* QPC page size and level. */\n \tuint8_t\tqpc_pg_size_qpc_lvl;\n \t/* QPC PBL indirect levels. */\n@@ -14956,6 +15368,159 @@ struct hwrm_func_backing_store_cfg_input {\n \tuint16_t\tmrav_entry_size;\n \t/* Number of bytes that have been allocated for each context entry. */\n \tuint16_t\ttim_entry_size;\n+\t/* TQM ring page size and level. */\n+\tuint8_t\ttqm_ring8_pg_size_tqm_ring_lvl;\n+\t/* TQM ring PBL indirect levels. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_SFT \\\n+\t\t0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to\n+\t * PTE tables.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_LVL_LVL_2\n+\t/* TQM ring page size. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_SFT \\\n+\t\t4\n+\t/* 4KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_CFG_INPUT_RING8_TQM_RING_PG_SIZE_PG_1G\n+\tuint8_t\tring8_unused[3];\n+\t/* Number of TQM ring entries. */\n+\tuint32_t\ttqm_ring8_num_entries;\n+\t/* TQM ring page directory. */\n+\tuint64_t\ttqm_ring8_page_dir;\n+\t/* TQM ring page size and level. */\n+\tuint8_t\ttqm_ring9_pg_size_tqm_ring_lvl;\n+\t/* TQM ring PBL indirect levels. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_SFT \\\n+\t\t0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to\n+\t * PTE tables.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_LVL_LVL_2\n+\t/* TQM ring page size. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_SFT \\\n+\t\t4\n+\t/* 4KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_CFG_INPUT_RING9_TQM_RING_PG_SIZE_PG_1G\n+\tuint8_t\tring9_unused[3];\n+\t/* Number of TQM ring entries. */\n+\tuint32_t\ttqm_ring9_num_entries;\n+\t/* TQM ring page directory. */\n+\tuint64_t\ttqm_ring9_page_dir;\n+\t/* TQM ring page size and level. */\n+\tuint8_t\ttqm_ring10_pg_size_tqm_ring_lvl;\n+\t/* TQM ring PBL indirect levels. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_SFT \\\n+\t\t0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to\n+\t * PTE tables.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_LVL_LVL_2\n+\t/* TQM ring page size. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_SFT \\\n+\t\t4\n+\t/* 4KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_CFG_INPUT_RING10_TQM_RING_PG_SIZE_PG_1G\n+\tuint8_t\tring10_unused[3];\n+\t/* Number of TQM ring entries. */\n+\tuint32_t\ttqm_ring10_num_entries;\n+\t/* TQM ring page directory. */\n+\tuint64_t\ttqm_ring10_page_dir;\n } __rte_packed;\n \n /* hwrm_func_backing_store_cfg_output (size:128b/16B) */\n@@ -15016,7 +15581,7 @@ struct hwrm_func_backing_store_qcfg_input {\n \tuint64_t\tresp_addr;\n } __rte_packed;\n \n-/* hwrm_func_backing_store_qcfg_output (size:1920b/240B) */\n+/* hwrm_func_backing_store_qcfg_output (size:2304b/288B) */\n struct hwrm_func_backing_store_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -15041,103 +15606,121 @@ struct hwrm_func_backing_store_qcfg_output {\n \t */\n \t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_FLAGS_MRAV_RESERVATION_SPLIT \\\n \t\tUINT32_C(0x2)\n-\tuint8_t\tunused_0[4];\n+\tuint32_t\tenables;\n \t/*\n \t * This bit must be '1' for the qp fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_QP \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_QP \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * This bit must be '1' for the srq fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_SRQ \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_SRQ \\\n \t\tUINT32_C(0x2)\n \t/*\n \t * This bit must be '1' for the cq fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_CQ \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_CQ \\\n \t\tUINT32_C(0x4)\n \t/*\n \t * This bit must be '1' for the vnic fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_VNIC \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_VNIC \\\n \t\tUINT32_C(0x8)\n \t/*\n \t * This bit must be '1' for the stat fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_STAT \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_STAT \\\n \t\tUINT32_C(0x10)\n \t/*\n \t * This bit must be '1' for the tqm_sp fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_SP \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_SP \\\n \t\tUINT32_C(0x20)\n \t/*\n \t * This bit must be '1' for the tqm_ring0 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING0 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING0 \\\n \t\tUINT32_C(0x40)\n \t/*\n \t * This bit must be '1' for the tqm_ring1 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING1 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING1 \\\n \t\tUINT32_C(0x80)\n \t/*\n \t * This bit must be '1' for the tqm_ring2 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING2 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING2 \\\n \t\tUINT32_C(0x100)\n \t/*\n \t * This bit must be '1' for the tqm_ring3 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING3 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING3 \\\n \t\tUINT32_C(0x200)\n \t/*\n \t * This bit must be '1' for the tqm_ring4 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING4 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING4 \\\n \t\tUINT32_C(0x400)\n \t/*\n \t * This bit must be '1' for the tqm_ring5 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING5 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING5 \\\n \t\tUINT32_C(0x800)\n \t/*\n \t * This bit must be '1' for the tqm_ring6 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING6 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING6 \\\n \t\tUINT32_C(0x1000)\n \t/*\n \t * This bit must be '1' for the tqm_ring7 fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TQM_RING7 \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING7 \\\n \t\tUINT32_C(0x2000)\n \t/*\n \t * This bit must be '1' for the mrav fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_MRAV \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_MRAV \\\n \t\tUINT32_C(0x4000)\n \t/*\n \t * This bit must be '1' for the tim fields to be\n \t * configured.\n \t */\n-\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_UNUSED_0_TIM \\\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TIM \\\n \t\tUINT32_C(0x8000)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring8 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING8 \\\n+\t\tUINT32_C(0x10000)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring9 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING9 \\\n+\t\tUINT32_C(0x20000)\n+\t/*\n+\t * This bit must be '1' for the tqm_ring10 fields to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_ENABLES_TQM_RING10 \\\n+\t\tUINT32_C(0x40000)\n \t/* QPC page size and level. */\n \tuint8_t\tqpc_pg_size_qpc_lvl;\n \t/* QPC PBL indirect levels. */\n@@ -15881,6 +16464,159 @@ struct hwrm_func_backing_store_qcfg_output {\n \tuint32_t\tmrav_num_entries;\n \t/* Number of Timer entries. */\n \tuint32_t\ttim_num_entries;\n+\t/* TQM ring page size and level. */\n+\tuint8_t\ttqm_ring8_pg_size_tqm_ring_lvl;\n+\t/* TQM ring PBL indirect levels. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_SFT \\\n+\t\t0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to\n+\t * PTE tables.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_LVL_LVL_2\n+\t/* TQM ring page size. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_SFT \\\n+\t\t4\n+\t/* 4KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING8_TQM_RING_PG_SIZE_PG_1G\n+\tuint8_t\tring8_unused[3];\n+\t/* Number of TQM ring entries. */\n+\tuint32_t\ttqm_ring8_num_entries;\n+\t/* TQM ring page directory. */\n+\tuint64_t\ttqm_ring8_page_dir;\n+\t/* TQM ring page size and level. */\n+\tuint8_t\ttqm_ring9_pg_size_tqm_ring_lvl;\n+\t/* TQM ring PBL indirect levels. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_SFT \\\n+\t\t0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to\n+\t * PTE tables.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_LVL_LVL_2\n+\t/* TQM ring page size. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_SFT \\\n+\t\t4\n+\t/* 4KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING9_TQM_RING_PG_SIZE_PG_1G\n+\tuint8_t\tring9_unused[3];\n+\t/* Number of TQM ring entries. */\n+\tuint32_t\ttqm_ring9_num_entries;\n+\t/* TQM ring page directory. */\n+\tuint64_t\ttqm_ring9_page_dir;\n+\t/* TQM ring page size and level. */\n+\tuint8_t\ttqm_ring10_pg_size_tqm_ring_lvl;\n+\t/* TQM ring PBL indirect levels. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_MASK \\\n+\t\tUINT32_C(0xf)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_SFT \\\n+\t\t0\n+\t/* PBL pointer is physical start address. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_0 \\\n+\t\tUINT32_C(0x0)\n+\t/* PBL pointer points to PTE table. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_1 \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to\n+\t * PTE tables.\n+\t */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2 \\\n+\t\tUINT32_C(0x2)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_LVL_LVL_2\n+\t/* TQM ring page size. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_MASK \\\n+\t\tUINT32_C(0xf0)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_SFT \\\n+\t\t4\n+\t/* 4KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_4K \\\n+\t\t(UINT32_C(0x0) << 4)\n+\t/* 8KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8K \\\n+\t\t(UINT32_C(0x1) << 4)\n+\t/* 64KB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_64K \\\n+\t\t(UINT32_C(0x2) << 4)\n+\t/* 2MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_2M \\\n+\t\t(UINT32_C(0x3) << 4)\n+\t/* 8MB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_8M \\\n+\t\t(UINT32_C(0x4) << 4)\n+\t/* 1GB. */\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G \\\n+\t\t(UINT32_C(0x5) << 4)\n+\t#define HWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_LAST \\\n+\t\tHWRM_FUNC_BACKING_STORE_QCFG_OUTPUT_RING10_TQM_RING_PG_SIZE_PG_1G\n+\tuint8_t\tring10_unused[3];\n+\t/* Number of TQM ring entries. */\n+\tuint32_t\ttqm_ring10_num_entries;\n+\t/* TQM ring page directory. */\n+\tuint64_t\ttqm_ring10_page_dir;\n \tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n@@ -16307,104 +17043,13 @@ struct hwrm_error_recovery_qcfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/***********************\n- * hwrm_func_vlan_qcfg *\n- ***********************/\n-\n-\n-/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n-struct hwrm_func_vlan_qcfg_input {\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/*\n-\t * The completion ring to send the completion event on. This should\n-\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n-\t */\n-\tuint16_t\tcmpl_ring;\n-\t/*\n-\t * The sequence ID is used by the driver for tracking multiple\n-\t * commands. This ID is treated as opaque data by the firmware and\n-\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n-\t */\n-\tuint16_t\tseq_id;\n-\t/*\n-\t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n-\t */\n-\tuint16_t\ttarget_id;\n-\t/*\n-\t * A physical address pointer pointing to a host buffer that the\n-\t * command's response data will be written. This can be either a host\n-\t * physical address (HPA) or a guest physical address (GPA) and must\n-\t * point to a physically contiguous block of memory.\n-\t */\n-\tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n-\t * for the requesting function.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[6];\n-} __rte_packed;\n-\n-/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n-struct hwrm_func_vlan_qcfg_output {\n-\t/* The specific error status for the command. */\n-\tuint16_t\terror_code;\n-\t/* The HWRM command request type. */\n-\tuint16_t\treq_type;\n-\t/* The sequence ID from the original command. */\n-\tuint16_t\tseq_id;\n-\t/* The length of the response data in number of bytes. */\n-\tuint16_t\tresp_len;\n-\tuint64_t\tunused_0;\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n-\t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n-\t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\t/* Future use. */\n-\tuint32_t\trsvd3;\n-\tuint8_t\tunused_3[3];\n-\t/*\n-\t * This field is used in Output records to indicate that the output\n-\t * is completely written to RAM.  This field should be read as '1'\n-\t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n-\t */\n-\tuint8_t\tvalid;\n-} __rte_packed;\n-\n-/**********************\n- * hwrm_func_vlan_cfg *\n- **********************/\n+/***************************\n+ * hwrm_func_echo_response *\n+ ****************************/\n \n \n-/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n-struct hwrm_func_vlan_cfg_input {\n+/* hwrm_func_echo_response_input (size:192b/24B) */\n+struct hwrm_func_echo_response_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -16420,10 +17065,10 @@ struct hwrm_func_vlan_cfg_input {\n \tuint16_t\tseq_id;\n \t/*\n \t * The target ID of the command:\n-\t * * 0x0-0xFFF8 - The function ID\n-\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n-\t * * 0xFFFD - Reserved for user-space HWRM interface\n-\t * * 0xFFFF - HWRM\n+\t * 0x0-0xFFF8 - The function ID\n+\t * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * 0xFFFD - Reserved for user-space HWRM interface\n+\t * 0xFFFF - HWRM\n \t */\n \tuint16_t\ttarget_id;\n \t/*\n@@ -16433,74 +17078,12 @@ struct hwrm_func_vlan_cfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/*\n-\t * Function ID of the function that is being\n-\t * configured.\n-\t * If set to 0xFF... (All Fs), then the configuration is\n-\t * for the requesting function.\n-\t */\n-\tuint16_t\tfid;\n-\tuint8_t\tunused_0[2];\n-\tuint32_t\tenables;\n-\t/*\n-\t * This bit must be '1' for the stag_vid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID      UINT32_C(0x1)\n-\t/*\n-\t * This bit must be '1' for the ctag_vid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID      UINT32_C(0x2)\n-\t/*\n-\t * This bit must be '1' for the stag_pcp field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP      UINT32_C(0x4)\n-\t/*\n-\t * This bit must be '1' for the ctag_pcp field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP      UINT32_C(0x8)\n-\t/*\n-\t * This bit must be '1' for the stag_tpid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID     UINT32_C(0x10)\n-\t/*\n-\t * This bit must be '1' for the ctag_tpid field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID     UINT32_C(0x20)\n-\t/* S-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tstag_vid;\n-\t/* S-TAG PCP value configured for the function. */\n-\tuint8_t\tstag_pcp;\n-\tuint8_t\tunused_1;\n-\t/*\n-\t * S-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tstag_tpid;\n-\t/* C-TAG VLAN identifier configured for the function. */\n-\tuint16_t\tctag_vid;\n-\t/* C-TAG PCP value configured for the function. */\n-\tuint8_t\tctag_pcp;\n-\tuint8_t\tunused_2;\n-\t/*\n-\t * C-TAG TPID value configured for the function. This field is specified in\n-\t * network byte order.\n-\t */\n-\tuint16_t\tctag_tpid;\n-\t/* Future use. */\n-\tuint32_t\trsvd1;\n-\t/* Future use. */\n-\tuint32_t\trsvd2;\n-\tuint8_t\tunused_3[4];\n+\tuint32_t\tevent_data1;\n+\tuint32_t\tevent_data2;\n } __rte_packed;\n \n-/* hwrm_func_vlan_cfg_output (size:128b/16B) */\n-struct hwrm_func_vlan_cfg_output {\n+/* hwrm_func_echo_response_output (size:128b/16B) */\n+struct hwrm_func_echo_response_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -16520,13 +17103,226 @@ struct hwrm_func_vlan_cfg_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n-/*******************************\n- * hwrm_func_vf_vnic_ids_query *\n- *******************************/\n+/***********************\n+ * hwrm_func_vlan_qcfg *\n+ ***********************/\n \n \n-/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */\n-struct hwrm_func_vf_vnic_ids_query_input {\n+/* hwrm_func_vlan_qcfg_input (size:192b/24B) */\n+struct hwrm_func_vlan_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Function ID of the function that is being\n+\t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n+\t */\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[6];\n+} __rte_packed;\n+\n+/* hwrm_func_vlan_qcfg_output (size:320b/40B) */\n+struct hwrm_func_vlan_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint64_t\tunused_0;\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n+\t/*\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\t/* Future use. */\n+\tuint32_t\trsvd3;\n+\tuint8_t\tunused_3[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**********************\n+ * hwrm_func_vlan_cfg *\n+ **********************/\n+\n+\n+/* hwrm_func_vlan_cfg_input (size:384b/48B) */\n+struct hwrm_func_vlan_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Function ID of the function that is being\n+\t * configured.\n+\t * If set to 0xFF... (All Fs), then the configuration is\n+\t * for the requesting function.\n+\t */\n+\tuint16_t\tfid;\n+\tuint8_t\tunused_0[2];\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the stag_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_VID      UINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the ctag_vid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_VID      UINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the stag_pcp field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_PCP      UINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the ctag_pcp field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_PCP      UINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the stag_tpid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_STAG_TPID     UINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the ctag_tpid field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_VLAN_CFG_INPUT_ENABLES_CTAG_TPID     UINT32_C(0x20)\n+\t/* S-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tstag_vid;\n+\t/* S-TAG PCP value configured for the function. */\n+\tuint8_t\tstag_pcp;\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * S-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tstag_tpid;\n+\t/* C-TAG VLAN identifier configured for the function. */\n+\tuint16_t\tctag_vid;\n+\t/* C-TAG PCP value configured for the function. */\n+\tuint8_t\tctag_pcp;\n+\tuint8_t\tunused_2;\n+\t/*\n+\t * C-TAG TPID value configured for the function. This field is specified in\n+\t * network byte order.\n+\t */\n+\tuint16_t\tctag_tpid;\n+\t/* Future use. */\n+\tuint32_t\trsvd1;\n+\t/* Future use. */\n+\tuint32_t\trsvd2;\n+\tuint8_t\tunused_3[4];\n+} __rte_packed;\n+\n+/* hwrm_func_vlan_cfg_output (size:128b/16B) */\n+struct hwrm_func_vlan_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*******************************\n+ * hwrm_func_vf_vnic_ids_query *\n+ *******************************/\n+\n+\n+/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */\n+struct hwrm_func_vf_vnic_ids_query_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n \t/*\n@@ -17153,6 +17949,374 @@ struct hwrm_func_host_pf_ids_query_output {\n } __rte_packed;\n \n /*********************\n+ * hwrm_func_spd_cfg *\n+ *********************/\n+\n+\n+/* hwrm_func_spd_cfg_input (size:384b/48B) */\n+struct hwrm_func_spd_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tflags;\n+\t/* Set this bit is '1' to enable the SPD datapath forwarding. */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_ENABLE       UINT32_C(0x1)\n+\t/* Set this bit is '1' to disable the SPD datapath forwarding. */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_FWD_DISABLE      UINT32_C(0x2)\n+\t/*\n+\t * Set this bit is '1' to enable the SPD datapath checksum\n+\t * feature.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_ENABLE      UINT32_C(0x4)\n+\t/*\n+\t * Set this bit is '1' to disable the SPD datapath checksum\n+\t * feature.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_CSUM_DISABLE     UINT32_C(0x8)\n+\t/*\n+\t * Set this bit is '1' to enable the SPD datapath debug\n+\t * feature.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_ENABLE       UINT32_C(0x10)\n+\t/*\n+\t * Set this bit is '1' to disable the SPD datapath debug\n+\t * feature.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_FLAGS_DBG_DISABLE      UINT32_C(0x20)\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the ethertype field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_ETHERTYPE \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the hash_mode_flags field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_MODE_FLAGS \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the hash_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_TYPE \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the ring_tbl_addr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_RING_TBL_ADDR \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the hash_key_tbl_addr field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_ENABLES_HASH_KEY_TBL_ADDR \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * Ethertype value used in the encapsulated SPD packet header.\n+\t * The user must chooose a value that is not conflicting with\n+\t * publicly defined ethertype values. By default, the ethertype\n+\t * value of 0xffff is used if there is no user specified value.\n+\t */\n+\tuint16_t\tethertype;\n+\t/* Flags to specify different RSS hash modes. */\n+\tuint8_t\thash_mode_flags;\n+\t/*\n+\t * When this bit is '1', it indicates using current RSS\n+\t * hash mode setting configured in the device.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_DEFAULT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 4 tuples {l3.src, l3.dest,\n+\t * l4.src, l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_4 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_INNERMOST_2 \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,\n+\t * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_4 \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_MODE_FLAGS_OUTERMOST_2 \\\n+\t\tUINT32_C(0x10)\n+\tuint8_t\tunused_1;\n+\tuint32_t\thash_type;\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv4\n+\t * packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV4         UINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of TCP/IPv4 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV4     UINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of UDP/IPv4 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV4     UINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv6\n+\t * packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_IPV6         UINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of TCP/IPv6 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_TCP_IPV6     UINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of UDP/IPv6 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_CFG_INPUT_HASH_TYPE_UDP_IPV6     UINT32_C(0x20)\n+\t/* This is the address for rss ring group table */\n+\tuint64_t\tring_grp_tbl_addr;\n+\t/* This is the address for rss hash key table */\n+\tuint64_t\thash_key_tbl_addr;\n+} __rte_packed;\n+\n+/* hwrm_func_spd_cfg_output (size:128b/16B) */\n+struct hwrm_func_spd_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/**********************\n+ * hwrm_func_spd_qcfg *\n+ **********************/\n+\n+\n+/* hwrm_func_spd_qcfg_input (size:128b/16B) */\n+struct hwrm_func_spd_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+} __rte_packed;\n+\n+/* hwrm_func_spd_qcfg_output (size:512b/64B) */\n+struct hwrm_func_spd_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint32_t\tflags;\n+\t/*\n+\t * The SPD datapath forwarding is currently enabled when this\n+\t * flag is set to '1'.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_FWD_ENABLED      UINT32_C(0x1)\n+\t/*\n+\t * The SPD datapath checksum feature is currently enabled when\n+\t * this flag is set to '1'.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_CSUM_ENABLED     UINT32_C(0x2)\n+\t/*\n+\t * The SPD datapath debug feature is currently enabled when\n+\t * this flag is set to '1'.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_FLAGS_DBG_ENABLED      UINT32_C(0x4)\n+\tuint32_t\thash_type;\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv4\n+\t * packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV4         UINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of TCP/IPv4 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV4     UINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv4 addresses and\n+\t * source/destination ports of UDP/IPv4 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV4     UINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source and destination IPv4 addresses of IPv6\n+\t * packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_IPV6         UINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of TCP/IPv6 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_TCP_IPV6     UINT32_C(0x10)\n+\t/*\n+\t * When this bit is '1', the RSS hash shall be computed\n+\t * over source/destination IPv6 addresses and\n+\t * source/destination ports of UDP/IPv6 packets.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_TYPE_UDP_IPV6     UINT32_C(0x20)\n+\t/* This is the value of rss hash key */\n+\tuint32_t\thash_key[10];\n+\t/* Flags to specify different RSS hash modes. */\n+\tuint8_t\thash_mode_flags;\n+\t/*\n+\t * When this bit is '1', it indicates using current RSS\n+\t * hash mode setting configured in the device.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_DEFAULT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 4 tuples {l3.src, l3.dest,\n+\t * l4.src, l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_4 \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over innermost 2 tuples {l3.src, l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_INNERMOST_2 \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 4 tuples {t_l3.src, t_l3.dest,\n+\t * t_l4.src, t_l4.dest} for tunnel packets. For none-tunnel\n+\t * packets, the RSS hash is computed over the normal\n+\t * src/dest l3 and src/dest l4 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_4 \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * When this bit is '1', it indicates requesting support of\n+\t * RSS hashing over outermost 2 tuples {t_l3.src, t_l3.dest} for\n+\t * tunnel packets. For none-tunnel packets, the RSS hash is\n+\t * computed over the normal src/dest l3 headers.\n+\t */\n+\t#define HWRM_FUNC_SPD_QCFG_OUTPUT_HASH_MODE_FLAGS_OUTERMOST_2 \\\n+\t\tUINT32_C(0x10)\n+\tuint8_t\tunused_1;\n+\t/*\n+\t * Ethertype value used in the encapsulated SPD packet header.\n+\t * The user must chooose a value that is not conflicting with\n+\t * publicly defined ethertype values. By default, the ethertype\n+\t * value of 0xffff is used if there is no user specified value.\n+\t */\n+\tuint16_t\tethertype;\n+\tuint8_t\tunused_2[3];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*********************\n  * hwrm_port_phy_cfg *\n  *********************/\n \n@@ -18855,6 +20019,12 @@ struct hwrm_port_phy_qcfg_output {\n \t#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_MEDIA_AUTO_DETECT \\\n \t\tUINT32_C(0x1)\n \t/*\n+\t * When this bit is '1', active_fec_signal_mode can be\n+\t * trusted.\n+\t */\n+\t#define HWRM_PORT_PHY_QCFG_OUTPUT_OPTION_FLAGS_SIGNAL_MODE_KNOWN \\\n+\t\tUINT32_C(0x2)\n+\t/*\n \t * Up to 16 bytes of null padded ASCII string representing\n \t * PHY vendor.\n \t * If the string is set to null, then the vendor name is not\n@@ -21432,13 +22602,23 @@ struct hwrm_port_phy_qcaps_output {\n \t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_LOCAL_LPBK_NOT_SUPPORTED \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * Reserved field. The HWRM shall set this field to 0.\n-\t * An HWRM client shall ignore this field.\n+\t * If set to 1, then this field indicates that the\n+\t * PHY/Link down policy during PF shutdown is totally\n+\t * controlled by the firmware. It can shutdown the link\n+\t * even when there are active VFs associated with the PF.\n+\t * Host PF driver can send HWRM_PHY_CFG command to bring\n+\t * down the PHY even when the port is shared between VFs\n+\t * and PFs.\n+\t */\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_FW_MANAGED_LINK_DOWN \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * If set to 1, this field indicates that the FCS may\n+\t * be disabled for a given packet via the transmit\n+\t * buffer descriptor.\n \t */\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_MASK \\\n-\t\tUINT32_C(0xc0)\n-\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_RSVD1_SFT \\\n-\t\t6\n+\t#define HWRM_PORT_PHY_QCAPS_OUTPUT_FLAGS_NO_FCS \\\n+\t\tUINT32_C(0x80)\n \t/* Number of front panel ports for this device. */\n \tuint8_t\tport_cnt;\n \t/* Not supported or unknown */\n@@ -23885,21 +25065,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id0;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id0_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -23923,21 +25103,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id1;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id1_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -23961,21 +25141,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id2;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id2_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -23999,21 +25179,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id3;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id3_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -24037,21 +25217,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id4;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id4_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -24075,21 +25255,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id5;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id5_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -24113,21 +25293,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id6;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id6_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -24151,21 +25331,21 @@ struct hwrm_queue_qportcfg_output {\n \t * # Available queues may not be in sequential order.\n \t */\n \tuint8_t\tqueue_id7;\n-\t/* This value is applicable to CoS queues only. */\n+\t/* This value specifies service profile kind for CoS queue */\n \tuint8_t\tqueue_id7_service_profile;\n \t/* Lossy (best-effort) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY \\\n \t\tUINT32_C(0x0)\n-\t/* Lossless (legacy) */\n+\t/* Lossless */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS \\\n \t\tUINT32_C(0x1)\n-\t/* Lossless RoCE */\n+\t/* Lossless RoCE (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE \\\n \t\tUINT32_C(0x1)\n-\t/* Lossy RoCE CNP */\n+\t/* Lossy RoCE CNP (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP \\\n \t\tUINT32_C(0x2)\n-\t/* Lossless NIC */\n+\t/* Lossless NIC (deprecated) */\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC \\\n \t\tUINT32_C(0x3)\n \t/* Set to 0xFF... (All Fs) if there is no service profile specified */\n@@ -24173,7 +25353,22 @@ struct hwrm_queue_qportcfg_output {\n \t\tUINT32_C(0xff)\n \t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_LAST \\\n \t\tHWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN\n-\tuint8_t\tunused_0;\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id0_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID0_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n \t/*\n \t * Up to 16 bytes of null padded ASCII string describing this queue.\n \t * The queue name includes a CoS queue index and, in some cases, text\n@@ -24194,7 +25389,118 @@ struct hwrm_queue_qportcfg_output {\n \tchar\tqid6_name[16];\n \t/* Up to 16 bytes of null padded ASCII string describing this queue. */\n \tchar\tqid7_name[16];\n-\tuint8_t\tunused_1[7];\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id1_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID1_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id2_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID2_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id3_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID3_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id4_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID4_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id5_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID5_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id6_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID6_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This value specifies traffic type for the service profile. We can\n+\t * have a TC mapped to multiple traffic types. For example shared\n+\t * CoS Q for CNP and NIC will have both cnp and nic bits set (0x6).\n+\t * A value of zero is considered as invalid.\n+\t */\n+\tuint8_t\tqueue_id7_service_profile_type;\n+\t/* Recommended to be used for RoCE traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_ROCE \\\n+\t\tUINT32_C(0x1)\n+\t/* Recommended to be used for NIC/L2 traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_NIC \\\n+\t\tUINT32_C(0x2)\n+\t/* Recommended to be used for CNP traffic only. */\n+\t#define HWRM_QUEUE_QPORTCFG_OUTPUT_QUEUE_ID7_SERVICE_PROFILE_TYPE_CNP \\\n+\t\tUINT32_C(0x4)\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n@@ -27583,104 +28889,441 @@ struct hwrm_queue_mplstc2pri_cfg_input {\n \tuint64_t\tresp_addr;\n \tuint32_t\tenables;\n \t/*\n-\t * This bit must be '1' for the mplstc0_pri_queue_id field to be\n+\t * This bit must be '1' for the mplstc0_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the mplstc1_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the mplstc2_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This bit must be '1' for the mplstc3_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x8)\n+\t/*\n+\t * This bit must be '1' for the mplstc4_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x10)\n+\t/*\n+\t * This bit must be '1' for the mplstc5_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x20)\n+\t/*\n+\t * This bit must be '1' for the mplstc6_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x40)\n+\t/*\n+\t * This bit must be '1' for the mplstc7_pri_queue_id field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \\\n+\t\tUINT32_C(0x80)\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure MPLS TC(EXP)to pri mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[3];\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 0. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc0_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 1. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc1_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 2  This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc2_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 3. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc3_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 4. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc4_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 5. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc5_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 6. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc6_pri_queue_id;\n+\t/*\n+\t * pri assigned to MPLS TC(EXP) 7. This value can only\n+\t * be changed before traffic has started.\n+\t */\n+\tuint8_t\ttc7_pri_queue_id;\n+} __rte_packed;\n+\n+/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */\n+struct hwrm_queue_mplstc2pri_cfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/****************************\n+ * hwrm_queue_vlanpri_qcaps *\n+ ****************************/\n+\n+\n+/* hwrm_queue_vlanpri_qcaps_input (size:192b/24B) */\n+struct hwrm_queue_vlanpri_qcaps_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure VLAN priority to user priority mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/* hwrm_queue_vlanpri_qcaps_output (size:128b/16B) */\n+struct hwrm_queue_vlanpri_qcaps_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * This is the default user priority which all VLAN priority values\n+\t * are mapped to if there is no VLAN priority to user priority mapping.\n+\t */\n+\tuint8_t\thw_default_pri;\n+\tuint8_t\tunused_0[6];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/*******************************\n+ * hwrm_queue_vlanpri2pri_qcfg *\n+ *******************************/\n+\n+\n+/* hwrm_queue_vlanpri2pri_qcfg_input (size:192b/24B) */\n+struct hwrm_queue_vlanpri2pri_qcfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/*\n+\t * Port ID of port for which the table is being configured.\n+\t * The HWRM needs to check whether this function is allowed\n+\t * to configure VLAN priority to user priority mapping on this port.\n+\t */\n+\tuint8_t\tport_id;\n+\tuint8_t\tunused_0[7];\n+} __rte_packed;\n+\n+/* hwrm_queue_vlanpri2pri_qcfg_output (size:192b/24B) */\n+struct hwrm_queue_vlanpri2pri_qcfg_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/*\n+\t * User priority assigned to VLAN priority 0. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri0_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 1. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri1_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 2. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri2_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 3. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri3_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 4. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri4_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 5. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri5_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 6. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri6_user_pri_id;\n+\t/*\n+\t * User priority assigned to VLAN priority 7. A value of 0xff\n+\t * indicates that no user priority is assigned. The default user\n+\t * priority will be used.\n+\t */\n+\tuint8_t\tvlanpri7_user_pri_id;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM. This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal processor,\n+\t * the order of writes has to be such that this field is written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n+/******************************\n+ * hwrm_queue_vlanpri2pri_cfg *\n+ ******************************/\n+\n+\n+/* hwrm_queue_vlanpri2pri_cfg_input (size:256b/32B) */\n+struct hwrm_queue_vlanpri2pri_cfg_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the vlanpri0_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC0_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI0_USER_PRI_ID \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * This bit must be '1' for the mplstc1_pri_queue_id field to be\n+\t * This bit must be '1' for the vlanpri1_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC1_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI1_USER_PRI_ID \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * This bit must be '1' for the mplstc2_pri_queue_id field to be\n+\t * This bit must be '1' for the vlanpri2_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC2_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI2_USER_PRI_ID \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * This bit must be '1' for the mplstc3_pri_queue_id field to be\n+\t * This bit must be '1' for the vlanpri3_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC3_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI3_USER_PRI_ID \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * This bit must be '1' for the mplstc4_pri_queue_id field to be\n+\t * This bit must be '1' for the vlanpri4_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC4_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI4_USER_PRI_ID \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * This bit must be '1' for the mplstc5_pri_queue_id field to be\n+\t * This bit must be '1' for the vlanpri5_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC5_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI5_USER_PRI_ID \\\n \t\tUINT32_C(0x20)\n \t/*\n-\t * This bit must be '1' for the mplstc6_pri_queue_id field to be\n+\t * This bit must be '1' for the vlanpri6_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC6_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI6_USER_PRI_ID \\\n \t\tUINT32_C(0x40)\n \t/*\n-\t * This bit must be '1' for the mplstc7_pri_queue_id field to be\n+\t * This bit must be '1' for the vlanpri7_user_pri_id field to be\n \t * configured.\n \t */\n-\t#define HWRM_QUEUE_MPLSTC2PRI_CFG_INPUT_ENABLES_TC7_PRI_QUEUE_ID \\\n+\t#define HWRM_QUEUE_VLANPRI2PRI_CFG_INPUT_ENABLES_VLANPRI7_USER_PRI_ID \\\n \t\tUINT32_C(0x80)\n \t/*\n \t * Port ID of port for which the table is being configured.\n \t * The HWRM needs to check whether this function is allowed\n-\t * to configure MPLS TC(EXP)to pri mapping on this port.\n+\t * to configure VLAN priority to user priority mapping on this port.\n \t */\n \tuint8_t\tport_id;\n \tuint8_t\tunused_0[3];\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 0. This value can only\n+\t * User priority assigned to VLAN priority 0. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc0_pri_queue_id;\n+\tuint8_t\tvlanpri0_user_pri_id;\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 1. This value can only\n+\t * User priority assigned to VLAN priority 1. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc1_pri_queue_id;\n+\tuint8_t\tvlanpri1_user_pri_id;\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 2  This value can only\n+\t * User priority assigned to VLAN priority 2. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc2_pri_queue_id;\n+\tuint8_t\tvlanpri2_user_pri_id;\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 3. This value can only\n+\t * User priority assigned to VLAN priority 3. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc3_pri_queue_id;\n+\tuint8_t\tvlanpri3_user_pri_id;\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 4. This value can only\n+\t * User priority assigned to VLAN priority 4. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc4_pri_queue_id;\n+\tuint8_t\tvlanpri4_user_pri_id;\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 5. This value can only\n+\t * User priority assigned to VLAN priority 5. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc5_pri_queue_id;\n+\tuint8_t\tvlanpri5_user_pri_id;\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 6. This value can only\n+\t * User priority assigned to VLAN priority 6. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc6_pri_queue_id;\n+\tuint8_t\tvlanpri6_user_pri_id;\n \t/*\n-\t * pri assigned to MPLS TC(EXP) 7. This value can only\n+\t * User priority assigned to VLAN priority 7. This value can only\n \t * be changed before traffic has started.\n \t */\n-\tuint8_t\ttc7_pri_queue_id;\n+\tuint8_t\tvlanpri7_user_pri_id;\n } __rte_packed;\n \n-/* hwrm_queue_mplstc2pri_cfg_output (size:128b/16B) */\n-struct hwrm_queue_mplstc2pri_cfg_output {\n+/* hwrm_queue_vlanpri2pri_cfg_output (size:128b/16B) */\n+struct hwrm_queue_vlanpri2pri_cfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n \t/* The HWRM command request type. */\n@@ -27740,8 +29383,22 @@ struct hwrm_vnic_alloc_input {\n \t * When this bit is '1', this VNIC is requested to\n \t * be the default VNIC for this function.\n \t */\n-\t#define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT     UINT32_C(0x1)\n-\tuint8_t\tunused_0[4];\n+\t#define HWRM_VNIC_ALLOC_INPUT_FLAGS_DEFAULT \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * When this bit is '1', proxy VEE PF is requesting\n+\t * allocation of a default VNIC on behalf of virtio-net\n+\t * function given in virtio_net_fid field.\n+\t */\n+\t#define HWRM_VNIC_ALLOC_INPUT_FLAGS_VIRTIO_NET_FID_VALID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * Virtio-net function's FID.\n+\t * This virtio-net function is requesting allocation of default\n+\t * VNIC through proxy VEE PF.\n+\t */\n+\tuint16_t\tvirtio_net_fid;\n+\tuint8_t\tunused_0[2];\n } __rte_packed;\n \n /* hwrm_vnic_alloc_output (size:128b/16B) */\n@@ -27767,6 +29424,132 @@ struct hwrm_vnic_alloc_output {\n \tuint8_t\tvalid;\n } __rte_packed;\n \n+/********************\n+ * hwrm_vnic_update *\n+ ********************/\n+\n+\n+/* hwrm_vnic_update_input (size:256b/32B) */\n+struct hwrm_vnic_update_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Logical vnic ID */\n+\tuint32_t\tvnic_id;\n+\tuint32_t\tenables;\n+\t/*\n+\t * This bit must be '1' for the vnic_state field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_VNIC_UPDATE_INPUT_ENABLES_VNIC_STATE_VALID \\\n+\t\tUINT32_C(0x1)\n+\t/*\n+\t * This bit must be '1' for the mru field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_VNIC_UPDATE_INPUT_ENABLES_MRU_VALID \\\n+\t\tUINT32_C(0x2)\n+\t/*\n+\t * This bit must be '1' for the metadata_format_type field to be\n+\t * configured.\n+\t */\n+\t#define HWRM_VNIC_UPDATE_INPUT_ENABLES_METADATA_FORMAT_TYPE_VALID \\\n+\t\tUINT32_C(0x4)\n+\t/*\n+\t * This will update the context variable with the same name if\n+\t * the corresponding enable is set.\n+\t */\n+\tuint8_t\tvnic_state;\n+\t/* Normal operation state for the VNIC. */\n+\t#define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_NORMAL UINT32_C(0x0)\n+\t/* All packets are dropped in this state. */\n+\t#define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP   UINT32_C(0x1)\n+\t#define HWRM_VNIC_UPDATE_INPUT_VNIC_STATE_LAST \\\n+\t\tHWRM_VNIC_UPDATE_INPUT_VNIC_STATE_DROP\n+\t/*\n+\t * The metadata format type used in all the RX packet completions\n+\t * going through this VNIC.\n+\t */\n+\tuint8_t\tmetadata_format_type;\n+\t/* No metadata information. */\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_NONE \\\n+\t\tUINT32_C(0x0)\n+\t/*\n+\t * Action record pointer (table_scope[4:0], act_rec_ptr[25:0],\n+\t * vtag[19:0]).\n+\t */\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_ACT_RECORD_PTR \\\n+\t\tUINT32_C(0x1)\n+\t/* Tunnel ID (tunnel_id[31:0], vtag[19:0]) */\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_TUNNEL_ID \\\n+\t\tUINT32_C(0x2)\n+\t/* Custom header data (updated_chdr_data[31:0], vtag[19:0]) */\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_CUSTOM_HDR_DATA \\\n+\t\tUINT32_C(0x3)\n+\t/* Header offsets (hdr_offsets[31:0], vtag[19:0]) */\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS \\\n+\t\tUINT32_C(0x4)\n+\t#define HWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_LAST \\\n+\t\tHWRM_VNIC_UPDATE_INPUT_METADATA_FORMAT_TYPE_HDR_OFFSETS\n+\t/*\n+\t * The maximum receive unit of the vnic.\n+\t * Each vnic is associated with a function.\n+\t * The vnic mru value overwrites the mru setting of the\n+\t * associated function.\n+\t * The HWRM shall make sure that vnic mru does not exceed\n+\t * the mru of the port the function is associated with.\n+\t */\n+\tuint16_t\tmru;\n+\tuint8_t\tunused_1[4];\n+} __rte_packed;\n+\n+/* hwrm_vnic_update_output (size:128b/16B) */\n+struct hwrm_vnic_update_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\tuint8_t\tunused_0[7];\n+\t/*\n+\t * This field is used in Output records to indicate that the output\n+\t * is completely written to RAM.  This field should be read as '1'\n+\t * to indicate that the output has been completely written.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n+\t */\n+\tuint8_t\tvalid;\n+} __rte_packed;\n+\n /******************\n  * hwrm_vnic_free *\n  ******************/\n@@ -28032,7 +29815,7 @@ struct hwrm_vnic_cfg_input {\n \t * queue ID will be arriving on this VNIC.  Packet priority to CoS mapping\n \t * rules can be specified using HWRM_QUEUE_PRI2COS_CFG.  In this mode,\n \t * ntuple filters with VNIC destination specified are invalid since they\n-\t * conflict with the CoS to VNIC steering rules in this mode.\n+\t * conflict with the the CoS to VNIC steering rules in this mode.\n \t *\n \t * If this field is not specified, packet to VNIC steering will be\n \t * subject to the standard L2 filter rules and any additional ntuple\n@@ -28243,6 +30026,12 @@ struct hwrm_vnic_qcfg_output {\n \t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE \\\n \t\tUINT32_C(0x40)\n \t/*\n+\t * When this bit is '0', VNIC is in normal operation state.\n+\t * When this bit is '1', VNIC drops all the received packets.\n+\t */\n+\t#define HWRM_VNIC_QCFG_OUTPUT_FLAGS_OPERATION_STATE \\\n+\t\tUINT32_C(0x80)\n+\t/*\n \t * When returned with a valid CoS Queue id, the CoS Queue/VNIC association\n \t * is valid.  Otherwise it will return 0xFFFF to indicate no VNIC/CoS\n \t * queue association.\n@@ -28423,6 +30212,32 @@ struct hwrm_vnic_qcaps_output {\n \t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_RX_CMPL_V2_CAP \\\n \t\tUINT32_C(0x200)\n \t/*\n+\t * When this bit is '1', it indicates that HW and firmware support\n+\t * vnic state change. Host drivers can change the vnic state using\n+\t * HWRM_VNIC_UPDATE. If set to '0', the HW and firmware do not\n+\t * support this feature.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VNIC_STATE_CAP \\\n+\t\tUINT32_C(0x400)\n+\t/*\n+\t * When this bit is '1', it indicates that firmware supports\n+\t * virtio-net functions default VNIC allocation using\n+\t * HWRM_VNIC_ALLOC.\n+\t * This capability is available only on Proxy VEE PF. If set to '0',\n+\t * firmware does not support this feature.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_VIRTIO_NET_VNIC_ALLOC_CAP \\\n+\t\tUINT32_C(0x800)\n+\t/*\n+\t * When this bit is set '1', then the capability to configure the\n+\t * metadata format in the RX completion is supported for the VNIC.\n+\t * When this bit is set to '0', then the capability to configure\n+\t * the metadata format in the RX completion is not supported for\n+\t * the VNIC.\n+\t */\n+\t#define HWRM_VNIC_QCAPS_OUTPUT_FLAGS_METADATA_FORMAT_CAP \\\n+\t\tUINT32_C(0x1000)\n+\t/*\n \t * This field advertises the maximum concurrent TPA aggregations\n \t * supported by the VNIC on new devices that support TPA v2.\n \t * '0' means that TPA v2 is not supported.\n@@ -29796,7 +31611,20 @@ struct hwrm_ring_alloc_output {\n \tuint16_t\tring_id;\n \t/* Logical number of ring allocated. */\n \tuint16_t\tlogical_ring_id;\n-\tuint8_t\tunused_0[3];\n+\t/*\n+\t * This field will tell whether to use ping or pong buffer\n+\t * for first push operation.\n+\t */\n+\tuint8_t\tpush_buffer_index;\n+\t/* Start push from ping buffer index */\n+\t#define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \\\n+\t\tUINT32_C(0x0)\n+\t/* Start push from pong buffer index */\n+\t#define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_LAST \\\n+\t\tHWRM_RING_ALLOC_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER\n+\tuint8_t\tunused_0[2];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -29957,7 +31785,20 @@ struct hwrm_ring_reset_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\tuint8_t\tunused_0[4];\n+\t/*\n+\t * This field will tell whether to use ping or pong buffer\n+\t * for first push operation.\n+\t */\n+\tuint8_t\tpush_buffer_index;\n+\t/* Start push from ping buffer index */\n+\t#define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PING_BUFFER \\\n+\t\tUINT32_C(0x0)\n+\t/* Start push from pong buffer index */\n+\t#define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER \\\n+\t\tUINT32_C(0x1)\n+\t#define HWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_LAST \\\n+\t\tHWRM_RING_RESET_OUTPUT_PUSH_BUFFER_INDEX_PONG_BUFFER\n+\tuint8_t\tunused_0[3];\n \t/* Position of consumer index after ring reset completes. */\n \tuint8_t\tconsumer_idx[3];\n \t/*\n@@ -29975,7 +31816,7 @@ struct hwrm_ring_reset_output {\n  *****************/\n \n \n-/* hwrm_ring_cfg_input (size:256b/32B) */\n+/* hwrm_ring_cfg_input (size:320b/40B) */\n struct hwrm_ring_cfg_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -30063,6 +31904,16 @@ struct hwrm_ring_cfg_input {\n \t#define HWRM_RING_CFG_INPUT_ENABLES_CMPL_RING_ID_UPDATE \\\n \t\tUINT32_C(0x10)\n \t/*\n+\t * When set to '1', metadata value provided by tx_metadata\n+\t * field in this command is inserted in the lb_header_metadata\n+\t * QP context field. When set to '0', no change done to metadata.\n+\t * Firmware rejects the tx ring metadata programming with\n+\t * HWRM_ERR_CODE_UNSUPPORTED error if the per function CFA BD\n+\t * metadata feature is not disabled.\n+\t */\n+\t#define HWRM_RING_CFG_INPUT_ENABLES_TX_METADATA \\\n+\t\tUINT32_C(0x20)\n+\t/*\n \t * Proxy function FID value.\n \t * This value is only used when either proxy_mode_enable flag or\n \t * tx_proxy_svif_override is set to '1'.\n@@ -30091,6 +31942,12 @@ struct hwrm_ring_cfg_input {\n \t */\n \tuint8_t\trx_sop_pad_bytes;\n \tuint8_t\tunused_1[3];\n+\t/*\n+\t * When tx_metadata enable bit is set, value specified in this field\n+\t * is copied to lb_header_metadata in the QP context.\n+\t */\n+\tuint32_t\ttx_metadata;\n+\tuint8_t\tunused_2[4];\n } __rte_packed;\n \n /* hwrm_ring_cfg_output (size:128b/16B) */\n@@ -30163,7 +32020,7 @@ struct hwrm_ring_qcfg_input {\n \tuint16_t\tring_id;\n } __rte_packed;\n \n-/* hwrm_ring_qcfg_output (size:192b/24B) */\n+/* hwrm_ring_qcfg_output (size:256b/32B) */\n struct hwrm_ring_qcfg_output {\n \t/* The specific error status for the command. */\n \tuint16_t\terror_code;\n@@ -30242,7 +32099,10 @@ struct hwrm_ring_qcfg_output {\n \t * This value is only used when rx_sop_pad_enable flag is set to '1'.\n \t */\n \tuint8_t\trx_sop_pad_bytes;\n-\tuint8_t\tunused_0[6];\n+\tuint8_t\tunused_0[3];\n+\t/* lb_header_metadata in the QP context is copied to this field. */\n+\tuint32_t\ttx_metadata;\n+\tuint8_t\tunused_1[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM.  This field should be read as '1'\n@@ -31686,12 +33546,15 @@ struct hwrm_cfa_l2_filter_alloc_input {\n \t\tUINT32_C(0x1)\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_LAST \\\n \t\tHWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_PATH_RX\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t/*\n+\t * Setting of this flag indicates the applicability to the loopback\n+\t * path.\n+\t */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n+\t * Setting of this flag indicates drop action. If this flag is not\n+\t * set, then it should be considered accept action.\n \t */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_FLAGS_DROP \\\n \t\tUINT32_C(0x4)\n@@ -31985,13 +33848,19 @@ struct hwrm_cfa_l2_filter_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_L2_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -32107,8 +33976,9 @@ struct hwrm_cfa_l2_filter_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -32170,8 +34040,9 @@ struct hwrm_cfa_l2_filter_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -32228,8 +34099,8 @@ struct hwrm_cfa_l2_filter_cfg_input {\n \t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_LAST \\\n \t\tHWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_PATH_RX\n \t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n+\t * Setting of this flag indicates drop action. If this flag is not\n+\t * set, then it should be considered accept action.\n \t */\n \t#define HWRM_CFA_L2_FILTER_CFG_INPUT_FLAGS_DROP \\\n \t\tUINT32_C(0x2)\n@@ -32298,8 +34169,9 @@ struct hwrm_cfa_l2_filter_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -32480,8 +34352,9 @@ struct hwrm_cfa_l2_set_rx_mask_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -32573,8 +34446,9 @@ struct hwrm_cfa_vlan_antispoof_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -32653,8 +34527,9 @@ struct hwrm_cfa_vlan_antispoof_qcfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -32695,7 +34570,10 @@ struct hwrm_cfa_tunnel_filter_alloc_input {\n \t */\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t/*\n+\t * Setting of this flag indicates the applicability to the loopback\n+\t * path.\n+\t */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n \t\tUINT32_C(0x1)\n \tuint32_t\tenables;\n@@ -32838,13 +34716,19 @@ struct hwrm_cfa_tunnel_filter_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_TUNNEL_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -32963,8 +34847,9 @@ struct hwrm_cfa_tunnel_filter_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -33023,8 +34908,9 @@ struct hwrm_cfa_tunnel_filter_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -33098,13 +34984,19 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -33114,7 +35006,10 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_input {\n \t\tHWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_TUNNEL_TYPE_ANYTUNNEL\n \t/* Tunnel alloc flags. */\n \tuint8_t\tflags;\n-\t/* Setting of this flag indicates modify existing redirect tunnel to new destination function ID. */\n+\t/*\n+\t * Setting of this flag indicates modify existing redirect tunnel\n+\t * to new destination function ID.\n+\t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC_INPUT_FLAGS_MODIFY_DST \\\n \t\tUINT32_C(0x1)\n \tuint8_t\tunused_0[4];\n@@ -33135,8 +35030,9 @@ struct hwrm_cfa_redirect_tunnel_type_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -33210,13 +35106,19 @@ struct hwrm_cfa_redirect_tunnel_type_free_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -33242,8 +35144,9 @@ struct hwrm_cfa_redirect_tunnel_type_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -33317,13 +35220,19 @@ struct hwrm_cfa_redirect_tunnel_type_info_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -33351,8 +35260,9 @@ struct hwrm_cfa_redirect_tunnel_type_info_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -33455,7 +35365,10 @@ struct hwrm_cfa_encap_data_vxlan {\n \tuint16_t\tdst_port;\n \t/* VXLAN Network Identifier. */\n \tuint32_t\tvni;\n-\t/* 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN header. */\n+\t/*\n+\t * 3 bytes VXLAN header reserve fields from 1st dword of the VXLAN\n+\t * header.\n+\t */\n \tuint8_t\thdr_rsvd0[3];\n \t/* 1 byte VXLAN header reserve field from 2nd dword of the VXLAN header. */\n \tuint8_t\thdr_rsvd1;\n@@ -33500,13 +35413,16 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t */\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t/*\n+\t * Setting of this flag indicates the applicability to the loopback\n+\t * path.\n+\t */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_LOOPBACK \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * Setting of this flag indicates this encap record is external encap record.\n-\t * Resetting of this flag indicates this flag is internal encap record and\n-\t * this is the default setting.\n+\t * Setting of this flag indicates this encap record is external\n+\t * encap record. Resetting of this flag indicates this flag is\n+\t * internal encap record and this is the default setting.\n \t */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_FLAGS_EXTERNAL \\\n \t\tUINT32_C(0x2)\n@@ -33539,13 +35455,19 @@ struct hwrm_cfa_encap_record_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t#define HWRM_CFA_ENCAP_RECORD_ALLOC_INPUT_ENCAP_TYPE_LAST \\\n@@ -33572,8 +35494,9 @@ struct hwrm_cfa_encap_record_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -33633,8 +35556,9 @@ struct hwrm_cfa_encap_record_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -33675,39 +35599,44 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t */\n \tuint64_t\tresp_addr;\n \tuint32_t\tflags;\n-\t/* Setting of this flag indicates the applicability to the loopback path. */\n+\t/*\n+\t * Setting of this flag indicates the applicability to the loopback\n+\t * path.\n+\t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_LOOPBACK \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n+\t * Setting of this flag indicates drop action. If this flag is not\n+\t * set, then it should be considered accept action.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DROP \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * Setting of this flag indicates that a meter is expected to be attached\n-\t * to this flow. This hint can be used when choosing the action record\n-\t * format required for the flow.\n+\t * Setting of this flag indicates that a meter is expected to be\n+\t * attached to this flow. This hint can be used when choosing the\n+\t * action record format required for the flow.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_METER \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * Setting of this flag indicates that the dst_id field contains function ID.\n-\t * If this is not set it indicates dest_id is VNIC or VPORT.\n+\t * Setting of this flag indicates that the dst_id field contains\n+\t * function ID. If this is not set it indicates dest_id is VNIC\n+\t * or VPORT.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_FID \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * Setting of this flag indicates match on arp reply when ethertype is 0x0806.\n-\t * If this is not set it indicates no specific arp opcode matching.\n+\t * Setting of this flag indicates match on arp reply when ethertype\n+\t * is 0x0806. If this is not set it indicates no specific arp opcode\n+\t * matching.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_ARP_REPLY \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * Setting of this flag indicates that the dst_id field contains RFS ring\n-\t * table index. If this is not set it indicates dst_id is VNIC or VPORT\n-\t * or function ID.  Note dest_fid and dest_rfs_ring_idx can’t be set at\n-\t * the same time.\n+\t * Setting of this flag indicates that the dst_id field contains RFS\n+\t * ring table index. If this is not set it indicates dst_id is VNIC\n+\t * or VPORT or function ID.  Note dest_fid and dest_rfs_ring_idx\n+\t * can’t be set at the same time.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_FLAGS_DEST_RFS_RING_IDX \\\n \t\tUINT32_C(0x20)\n@@ -33928,13 +35857,19 @@ struct hwrm_cfa_ntuple_filter_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_NTUPLE_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -34071,8 +36006,9 @@ struct hwrm_cfa_ntuple_filter_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -34149,8 +36085,9 @@ struct hwrm_cfa_ntuple_filter_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -34212,15 +36149,16 @@ struct hwrm_cfa_ntuple_filter_cfg_input {\n \tuint32_t\tflags;\n \t/*\n \t * Setting this bit to 1 indicates that dest_id field contains FID.\n-\t * Setting this to 0 indicates that dest_id field contains VNIC or VPORT.\n+\t * Setting this to 0 indicates that dest_id field contains VNIC or\n+\t * VPORT.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_FID \\\n \t\tUINT32_C(0x1)\n \t/*\n \t * Setting of this flag indicates that the new_dst_id field contains\n-\t * RFS ring table index. If this is not set it indicates new_dst_id is\n-\t * VNIC or VPORT or function ID.  Note dest_fid and dest_rfs_ring_idx\n-\t * can’t be set at the same time.\n+\t * RFS ring table index. If this is not set it indicates new_dst_id\n+\t * is VNIC or VPORT or function ID.  Note dest_fid and\n+\t * dest_rfs_ring_idx can’t be set at the same time.\n \t */\n \t#define HWRM_CFA_NTUPLE_FILTER_CFG_INPUT_FLAGS_DEST_RFS_RING_IDX \\\n \t\tUINT32_C(0x2)\n@@ -34270,8 +36208,9 @@ struct hwrm_cfa_ntuple_filter_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -34325,28 +36264,34 @@ struct hwrm_cfa_em_flow_alloc_input {\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_LAST \\\n \t\tHWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PATH_RX\n \t/*\n-\t * Setting of this flag indicates enabling of a byte counter for a given\n-\t * flow.\n+\t * Setting of this flag indicates enabling of a byte counter for a\n+\t * given flow.\n \t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_BYTE_CTR     UINT32_C(0x2)\n \t/*\n-\t * Setting of this flag indicates enabling of a packet counter for a given\n-\t * flow.\n+\t * Setting of this flag indicates enabling of a packet counter for a\n+\t * given flow.\n \t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_PKT_CTR      UINT32_C(0x4)\n-\t/* Setting of this flag indicates de-capsulation action for the given flow. */\n+\t/*\n+\t * Setting of this flag indicates de-capsulation action for the\n+\t * given flow.\n+\t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DECAP        UINT32_C(0x8)\n-\t/* Setting of this flag indicates encapsulation action for the given flow. */\n+\t/*\n+\t * Setting of this flag indicates encapsulation action for the\n+\t * given flow.\n+\t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_ENCAP        UINT32_C(0x10)\n \t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n+\t * Setting of this flag indicates drop action. If this flag is not\n+\t * set, then it should be considered accept action.\n \t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_DROP         UINT32_C(0x20)\n \t/*\n-\t * Setting of this flag indicates that a meter is expected to be attached\n-\t * to this flow. This hint can be used when choosing the action record\n-\t * format required for the flow.\n+\t * Setting of this flag indicates that a meter is expected to be\n+\t * attached to this flow. This hint can be used when choosing the\n+\t * action record format required for the flow.\n \t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_FLAGS_METER        UINT32_C(0x40)\n \tuint32_t\tenables;\n@@ -34495,13 +36440,19 @@ struct hwrm_cfa_em_flow_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_EM_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -34676,8 +36627,9 @@ struct hwrm_cfa_em_flow_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -34736,8 +36688,9 @@ struct hwrm_cfa_em_flow_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -34791,9 +36744,9 @@ struct hwrm_cfa_meter_qcaps_output {\n \tuint16_t\tresp_len;\n \tuint32_t\tflags;\n \t/*\n-\t * Enumeration denoting the clock at which the Meter is running with.\n-\t * This enumeration is used for resources that are similar for both\n-\t * TX and RX paths of the chip.\n+\t * Enumeration denoting the clock at which the Meter is running\n+\t * with. This enumeration is used for resources that are similar\n+\t * for both TX and RX paths of the chip.\n \t */\n \t#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_MASK  UINT32_C(0xf)\n \t#define HWRM_CFA_METER_QCAPS_OUTPUT_FLAGS_CLOCK_SFT   0\n@@ -34849,8 +36802,9 @@ struct hwrm_cfa_meter_qcaps_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -35127,8 +37081,9 @@ struct hwrm_cfa_meter_profile_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -35212,8 +37167,9 @@ struct hwrm_cfa_meter_profile_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -35483,8 +37439,9 @@ struct hwrm_cfa_meter_profile_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -35579,8 +37536,9 @@ struct hwrm_cfa_meter_instance_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -35650,8 +37608,8 @@ struct hwrm_cfa_meter_instance_cfg_input {\n \t#define HWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_LAST \\\n \t\tHWRM_CFA_METER_INSTANCE_CFG_INPUT_METER_PROFILE_ID_INVALID\n \t/*\n-\t * This value identifies the ID of a meter instance that needs to be updated with\n-\t * a new meter profile specified in this command.\n+\t * This value identifies the ID of a meter instance that needs to be\n+\t * updated with a new meter profile specified in this command.\n \t */\n \tuint16_t\tmeter_instance_id;\n \tuint8_t\tunused_1[2];\n@@ -35672,8 +37630,9 @@ struct hwrm_cfa_meter_instance_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -35757,8 +37716,9 @@ struct hwrm_cfa_meter_instance_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -35945,13 +37905,19 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_DECAP_FILTER_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -36059,8 +38025,8 @@ struct hwrm_cfa_decap_filter_alloc_input {\n \t */\n \tuint16_t\tdst_id;\n \t/*\n-\t * If set, this value shall represent the L2 context that matches the L2\n-\t * information of the decap filter.\n+\t * If set, this value shall represent the L2 context that matches the\n+\t * L2 information of the decap filter.\n \t */\n \tuint16_t\tl2_ctxt_ref_id;\n } __rte_packed;\n@@ -36082,8 +38048,9 @@ struct hwrm_cfa_decap_filter_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -36143,8 +38110,9 @@ struct hwrm_cfa_decap_filter_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -36219,29 +38187,35 @@ struct hwrm_cfa_flow_alloc_input {\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_LAST \\\n \t\tHWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_FLOWTYPE_IPV6\n \t/*\n-\t * when set to 1, indicates TX flow offload for function specified in src_fid and\n-\t * the dst_fid should be set to invalid value. To indicate a VM to VM flow, both\n-\t * of the path_tx and path_rx flags need to be set. For virtio vSwitch offload\n-\t * case, the src_fid and dst_fid is set to the same fid value. For the SRIOV\n-\t * vSwitch offload case, the src_fid and dst_fid must be set to the same VF FID\n-\t * belong to the children VFs of the same PF to indicate VM to VM flow.\n+\t * when set to 1, indicates TX flow offload for function specified\n+\t * in src_fid and the dst_fid should be set to invalid value. To\n+\t * indicate a VM to VM flow, both of the path_tx and path_rx flags\n+\t * need to be set. For virtio vSwitch offload case, the src_fid and\n+\t * dst_fid is set to the same fid value. For the SRIOV vSwitch\n+\t * offload case, the src_fid and dst_fid must be set to the same VF\n+\t * FID belong to the children VFs of the same PF to indicate VM to\n+\t * VM flow.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_TX \\\n \t\tUINT32_C(0x40)\n \t/*\n-\t * when set to 1, indicates RX flow offload for function specified in dst_fid and\n-\t * the src_fid should be set to invalid value.\n+\t * when set to 1, indicates RX flow offload for function specified\n+\t * in dst_fid and the src_fid should be set to invalid value.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_PATH_RX \\\n \t\tUINT32_C(0x80)\n \t/*\n-\t * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan header is\n-\t * required and the VXLAN VNI value is stored in the first 24 bits of the dmac field.\n-\t * This flag is only valid when the flow direction is RX.\n+\t * Set to 1 to indicate matching of VXLAN VNI from the custom vxlan\n+\t * header is required and the VXLAN VNI value is stored in the first\n+\t * 24 bits of the dmac field. This flag is only valid when the flow\n+\t * direction is RX.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_MATCH_VXLAN_IP_VNI \\\n \t\tUINT32_C(0x100)\n-\t/* Set to 1 to indicate vhost_id is specified in the outer_vlan_tci field. */\n+\t/*\n+\t * Set to 1 to indicate vhost_id is specified in the outer_vlan_tci\n+\t * field.\n+\t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_FLAGS_VHOST_ID_USE_VLAN \\\n \t\tUINT32_C(0x200)\n \t/*\n@@ -36253,8 +38227,8 @@ struct hwrm_cfa_flow_alloc_input {\n \tuint32_t\ttunnel_handle;\n \tuint16_t\taction_flags;\n \t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n+\t * Setting of this flag indicates drop action. If this flag is not\n+\t * set, then it should be considered accept action.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FWD \\\n \t\tUINT32_C(0x1)\n@@ -36262,8 +38236,8 @@ struct hwrm_cfa_flow_alloc_input {\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_RECYCLE \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * Setting of this flag indicates drop action. If this flag is not set,\n-\t * then it should be considered accept action.\n+\t * Setting of this flag indicates drop action. If this flag is not\n+\t * set, then it should be considered accept action.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_DROP \\\n \t\tUINT32_C(0x4)\n@@ -36289,10 +38263,10 @@ struct hwrm_cfa_flow_alloc_input {\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TTL_DECREMENT \\\n \t\tUINT32_C(0x200)\n \t/*\n-\t * If set to 1 and flow direction is TX, it indicates decap of L2 header\n-\t * and encap of tunnel header. If set to 1 and flow direction is RX, it\n-\t * indicates decap of tunnel header and encap L2 header. The type of tunnel\n-\t * is specified in the tunnel_type field.\n+\t * If set to 1 and flow direction is TX, it indicates decap of L2\n+\t * header and encap of tunnel header. If set to 1 and flow direction\n+\t * is RX, it indicates decap of tunnel header and encap L2 header.\n+\t * The type of tunnel is specified in the tunnel_type field.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_TUNNEL_IP \\\n \t\tUINT32_C(0x400)\n@@ -36300,18 +38274,19 @@ struct hwrm_cfa_flow_alloc_input {\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_FLOW_AGING_ENABLED \\\n \t\tUINT32_C(0x800)\n \t/*\n-\t * If set to 1 an attempt will be made to try to offload this flow to the\n-\t * most optimal flow table resource. If set to 0, the flow will be\n-\t * placed to the default flow table resource.\n+\t * If set to 1 an attempt will be made to try to offload this flow\n+\t * to the most optimal flow table resource. If set to 0, the flow\n+\t * will be placed to the default flow table resource.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_PRI_HINT \\\n \t\tUINT32_C(0x1000)\n \t/*\n-\t * If set to 1 there will be no attempt to allocate an on-chip try to\n-\t * offload this flow. If set to 0, which will keep compatibility with the\n-\t * older drivers, will cause the FW to attempt to allocate an on-chip flow\n-\t * counter for the newly created flow. This will keep the existing behavior\n-\t * with EM flows which always had an associated flow counter.\n+\t * If set to 1 there will be no attempt to allocate an on-chip try\n+\t * to offload this flow. If set to 0, which will keep compatibility\n+\t * with the older drivers, will cause the FW to attempt to allocate\n+\t * an on-chip flow counter for the newly created flow. This will\n+\t * keep the existing behavior with EM flows which always had an\n+\t * associated flow counter.\n \t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_ACTION_FLAGS_NO_FLOW_COUNTER_ALLOC \\\n \t\tUINT32_C(0x2000)\n@@ -36415,13 +38390,19 @@ struct hwrm_cfa_flow_alloc_input {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_FLOW_ALLOC_INPUT_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -36492,8 +38473,9 @@ struct hwrm_cfa_flow_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -36589,8 +38571,9 @@ struct hwrm_cfa_flow_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -36614,9 +38597,9 @@ struct hwrm_cfa_flow_action_data {\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * If set to 1 and flow direction is TX, it indicates decap of L2 header\n-\t * and encap of tunnel header. If set to 1 and flow direction is RX, it\n-\t * indicates decap of tunnel header and encap L2 header.\n+\t * If set to 1 and flow direction is TX, it indicates decap of L2\n+\t * header and encap of tunnel header. If set to 1 and flow direction\n+\t * is RX, it indicates decap of tunnel header and encap L2 header.\n \t */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ACTION_FLAGS_TUNNEL_IP \\\n \t\tUINT32_C(0x20)\n@@ -36663,11 +38646,17 @@ struct hwrm_cfa_flow_action_data {\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE        UINT32_C(0x8)\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_V4     UINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_IPGRE_V1     UINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_L2_ETYPE     UINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6 UINT32_C(0xc)\n \t#define HWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_LAST \\\n \t\tHWRM_CFA_FLOW_ACTION_DATA_ENCAP_TYPE_VXLAN_GPE_V6\n@@ -36710,13 +38699,19 @@ struct hwrm_cfa_flow_tunnel_hdr_data {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_V4 \\\n \t\tUINT32_C(0x9)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_IPGRE_V1 \\\n \t\tUINT32_C(0xa)\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_L2_ETYPE \\\n \t\tUINT32_C(0xb)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_FLOW_TUNNEL_HDR_DATA_TUNNEL_TYPE_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0xc)\n \t/* Any tunneled traffic */\n@@ -36923,8 +38918,9 @@ struct hwrm_cfa_flow_info_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -36967,32 +38963,39 @@ struct hwrm_cfa_flow_flush_input {\n \t/* flags is 32 b */\n \tuint32_t\tflags;\n \t/*\n-\t * Set to 1 to indicate the page size, page layers, and flow_handle_table_dma_addr\n-\t * fields are valid. The flow flush operation should only flush the flows from the\n-\t * flow table specified. This flag is set to 0 by older driver. For older firmware,\n-\t * setting this flag has no effect.\n+\t * Set to 1 to indicate the page size, page layers, and\n+\t * flow_handle_table_dma_addr fields are valid. The flow flush\n+\t * operation should only flush the flows from the flow table\n+\t * specified. This flag is set to 0 by older driver. For older\n+\t * firmware, setting this flag has no effect.\n \t */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_TABLE_VALID \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * Set to 1 to indicate flow flush operation to cleanup all the flows, meters, CFA\n-\t * context memory tables etc. This flag is set to 0 by older driver. For older firmware,\n-\t * setting this flag has no effect.\n+\t * Set to 1 to indicate flow flush operation to cleanup all the\n+\t * flows, meters, CFA context memory tables etc. This flag is set to\n+\t * 0 by older driver. For older firmware, setting this flag has no\n+\t * effect.\n \t */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_ALL \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * Set to 1 to indicate flow flush operation to cleanup all the flows by the caller.\n-\t * This flag is set to 0 by older driver. For older firmware, setting this flag has no effect.\n+\t * Set to 1 to indicate flow flush operation to cleanup all the\n+\t * flows by the caller. This flag is set to 0 by older driver. For\n+\t * older firmware, setting this flag has no effect.\n \t */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_RESET_PORT \\\n \t\tUINT32_C(0x4)\n-\t/* Set to 1 to indicate the flow counter IDs are included in the flow table. */\n+\t/*\n+\t * Set to 1 to indicate the flow counter IDs are included in the\n+\t * flow table.\n+\t */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_INCL_FC \\\n \t\tUINT32_C(0x8000000)\n \t/*\n-\t * This specifies the size of flow handle entries provided by the driver\n-\t * in the flow table specified below. Only two flow handle size enums are defined.\n+\t * This specifies the size of flow handle entries provided by the\n+\t * driver in the flow table specified below. Only two flow handle\n+\t * size enums are defined.\n \t */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_FLAGS_FLOW_HANDLE_ENTRY_SIZE_MASK \\\n \t\tUINT32_C(0xc0000000)\n@@ -37032,7 +39035,10 @@ struct hwrm_cfa_flow_flush_input {\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n-\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n \t#define HWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LAST \\\n \t\tHWRM_CFA_FLOW_FLUSH_INPUT_PAGE_LEVEL_LVL_2\n@@ -37057,8 +39063,9 @@ struct hwrm_cfa_flow_flush_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37198,8 +39205,9 @@ struct hwrm_cfa_flow_stats_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37266,8 +39274,9 @@ struct hwrm_cfa_flow_aging_timer_reset_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37309,28 +39318,52 @@ struct hwrm_cfa_flow_aging_cfg_input {\n \tuint64_t\tresp_addr;\n \t/* The bit field to enable per flow aging configuration. */\n \tuint16_t\tenables;\n-\t/* This bit must be '1' for the tcp flow timer field to be configured */\n+\t/*\n+\t * This bit must be '1' for the tcp flow timer field to be\n+\t * configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FLOW_TIMER \\\n \t\tUINT32_C(0x1)\n-\t/* This bit must be '1' for the tcp finish timer field to be configured */\n+\t/*\n+\t * This bit must be '1' for the tcp finish timer field to be\n+\t * configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_TCP_FIN_TIMER \\\n \t\tUINT32_C(0x2)\n-\t/* This bit must be '1' for the udp flow timer field to be configured */\n+\t/*\n+\t * This bit must be '1' for the udp flow timer field to be\n+\t * configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_UDP_FLOW_TIMER \\\n \t\tUINT32_C(0x4)\n-\t/* This bit must be '1' for the eem dma interval field to be configured */\n+\t/*\n+\t * This bit must be '1' for the eem dma interval field to be\n+\t * configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_DMA_INTERVAL \\\n \t\tUINT32_C(0x8)\n-\t/* This bit must be '1' for the eem notice interval field to be configured */\n+\t/*\n+\t * This bit must be '1' for the eem notice interval field to be\n+\t * configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_NOTICE_INTERVAL \\\n \t\tUINT32_C(0x10)\n-\t/* This bit must be '1' for the eem context memory maximum entries field to be configured */\n+\t/*\n+\t * This bit must be '1' for the eem context memory maximum entries\n+\t * field to be configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MAX_ENTRIES \\\n \t\tUINT32_C(0x20)\n-\t/* This bit must be '1' for the eem context memory ID field to be configured */\n+\t/*\n+\t * This bit must be '1' for the eem context memory ID field to be\n+\t * configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_ID \\\n \t\tUINT32_C(0x40)\n-\t/* This bit must be '1' for the eem context memory type field to be configured */\n+\t/*\n+\t * This bit must be '1' for the eem context memory type field to be\n+\t * configured\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_ENABLES_EEM_CTX_MEM_TYPE \\\n \t\tUINT32_C(0x80)\n \tuint8_t\tflags;\n@@ -37342,7 +39375,10 @@ struct hwrm_cfa_flow_aging_cfg_input {\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX      UINT32_C(0x1)\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_LAST \\\n \t\tHWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_PATH_RX\n-\t/* Enumeration denoting the enable, disable eem flow aging configuration. */\n+\t/*\n+\t * Enumeration denoting the enable, disable eem flow aging\n+\t * configuration.\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM        UINT32_C(0x2)\n \t/* tx path */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_DISABLE \\\n@@ -37353,22 +39389,40 @@ struct hwrm_cfa_flow_aging_cfg_input {\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_LAST \\\n \t\tHWRM_CFA_FLOW_AGING_CFG_INPUT_FLAGS_EEM_ENABLE\n \tuint8_t\tunused_0;\n-\t/* The flow aging timer for all TCP flows, the unit is 100 milliseconds. */\n+\t/*\n+\t * The flow aging timer for all TCP flows, the unit is 100\n+\t * milliseconds.\n+\t */\n \tuint32_t\ttcp_flow_timer;\n-\t/* The TCP finished timer for all TCP flows, the unit is 100 milliseconds. */\n+\t/*\n+\t * The TCP finished timer for all TCP flows, the unit is 100\n+\t * milliseconds.\n+\t */\n \tuint32_t\ttcp_fin_timer;\n-\t/* The flow aging timer for all UDP flows, the unit is 100 milliseconds. */\n+\t/*\n+\t * The flow aging timer for all UDP flows, the unit is 100\n+\t * milliseconds.\n+\t */\n \tuint32_t\tudp_flow_timer;\n-\t/* The interval to dma eem ejection data to host memory, the unit is milliseconds. */\n+\t/*\n+\t * The interval to dma eem ejection data to host memory, the unit is\n+\t * milliseconds.\n+\t */\n \tuint16_t\teem_dma_interval;\n-\t/* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */\n+\t/*\n+\t * The interval to notify driver to read the eem ejection data, the\n+\t * unit is milliseconds.\n+\t */\n \tuint16_t\teem_notice_interval;\n \t/* The maximum entries number in the eem context memory. */\n \tuint32_t\teem_ctx_max_entries;\n \t/* The context memory ID for eem flow aging. */\n \tuint16_t\teem_ctx_id;\n \tuint16_t\teem_ctx_mem_type;\n-\t/* The content of context memory is eem ejection data, the size of each entry is 4 bytes. */\n+\t/*\n+\t * The content of context memory is eem ejection data, the size of\n+\t * each entry is 4 bytes.\n+\t */\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_EJECTION_DATA \\\n \t\tUINT32_C(0x0)\n \t#define HWRM_CFA_FLOW_AGING_CFG_INPUT_EEM_CTX_MEM_TYPE_LAST \\\n@@ -37391,8 +39445,9 @@ struct hwrm_cfa_flow_aging_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37432,7 +39487,10 @@ struct hwrm_cfa_flow_aging_qcfg_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */\n+\t/*\n+\t * The direction for the flow aging configuration, 1 is rx path, 2 is\n+\t * tx path.\n+\t */\n \tuint8_t\tflags;\n \t/* Enumeration denoting the RX, TX type of the resource. */\n \t#define HWRM_CFA_FLOW_AGING_QCFG_INPUT_FLAGS_PATH     UINT32_C(0x1)\n@@ -37455,15 +39513,30 @@ struct hwrm_cfa_flow_aging_qcfg_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* The current flow aging timer for all TCP flows, the unit is 100 millisecond. */\n+\t/*\n+\t * The current flow aging timer for all TCP flows, the unit is 100\n+\t * millisecond.\n+\t */\n \tuint32_t\ttcp_flow_timer;\n-\t/* The current TCP finished timer for all TCP flows, the unit is 100 millisecond. */\n+\t/*\n+\t * The current TCP finished timer for all TCP flows, the unit is 100\n+\t * millisecond.\n+\t */\n \tuint32_t\ttcp_fin_timer;\n-\t/* The current flow aging timer for all UDP flows, the unit is 100 millisecond. */\n+\t/*\n+\t * The current flow aging timer for all UDP flows, the unit is 100\n+\t * millisecond.\n+\t */\n \tuint32_t\tudp_flow_timer;\n-\t/* The interval to dma eem ejection data to host memory, the unit is milliseconds. */\n+\t/*\n+\t * The interval to dma eem ejection data to host memory, the unit is\n+\t * milliseconds.\n+\t */\n \tuint16_t\teem_dma_interval;\n-\t/* The interval to notify driver to read the eem ejection data, the unit is milliseconds. */\n+\t/*\n+\t * The interval to notify driver to read the eem ejection data, the\n+\t * unit is milliseconds.\n+\t */\n \tuint16_t\teem_notice_interval;\n \t/* The maximum entries number in the eem context memory. */\n \tuint32_t\teem_ctx_max_entries;\n@@ -37476,8 +39549,9 @@ struct hwrm_cfa_flow_aging_qcfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37517,7 +39591,10 @@ struct hwrm_cfa_flow_aging_qcaps_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* The direction for the flow aging configuration, 1 is rx path, 2 is tx path. */\n+\t/*\n+\t * The direction for the flow aging configuration, 1 is rx path, 2 is\n+\t * tx path.\n+\t */\n \tuint8_t\tflags;\n \t/* Enumeration denoting the RX, TX type of the resource. */\n \t#define HWRM_CFA_FLOW_AGING_QCAPS_INPUT_FLAGS_PATH     UINT32_C(0x1)\n@@ -37540,11 +39617,20 @@ struct hwrm_cfa_flow_aging_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* The maximum flow aging timer for all TCP flows, the unit is 100 millisecond. */\n+\t/*\n+\t * The maximum flow aging timer for all TCP flows, the unit is 100\n+\t * millisecond.\n+\t */\n \tuint32_t\tmax_tcp_flow_timer;\n-\t/* The maximum TCP finished timer for all TCP flows, the unit is 100 millisecond. */\n+\t/*\n+\t * The maximum TCP finished timer for all TCP flows, the unit is 100\n+\t * millisecond.\n+\t */\n \tuint32_t\tmax_tcp_fin_timer;\n-\t/* The maximum flow aging timer for all UDP flows, the unit is 100 millisecond. */\n+\t/*\n+\t * The maximum flow aging timer for all UDP flows, the unit is 100\n+\t * millisecond.\n+\t */\n \tuint32_t\tmax_udp_flow_timer;\n \t/* The maximum aging flows that HW can support. */\n \tuint32_t\tmax_aging_flows;\n@@ -37553,8 +39639,9 @@ struct hwrm_cfa_flow_aging_qcaps_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37610,17 +39697,24 @@ struct hwrm_cfa_tcp_flag_process_qcfg_output {\n \tuint16_t\trx_ar_id_port0;\n \t/* The port 1 RX mirror action record ID. */\n \tuint16_t\trx_ar_id_port1;\n-\t/* The port 0 RX action record ID for TX TCP flag packets from loopback path. */\n+\t/*\n+\t * The port 0 RX action record ID for TX TCP flag packets from\n+\t * loopback path.\n+\t */\n \tuint16_t\ttx_ar_id_port0;\n-\t/* The port 1 RX action record ID for TX TCP flag packets from loopback path. */\n+\t/*\n+\t * The port 1 RX action record ID for TX TCP flag packets from\n+\t * loopback path.\n+\t */\n \tuint16_t\ttx_ar_id_port1;\n \tuint8_t\tunused_0[7];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37684,8 +39778,9 @@ struct hwrm_cfa_vf_pair_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37744,8 +39839,9 @@ struct hwrm_cfa_vf_pair_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37831,8 +39927,9 @@ struct hwrm_cfa_vf_pair_info_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -37895,10 +39992,16 @@ struct hwrm_cfa_pair_alloc_input {\n \t/* Modify existing rep2fn pair and move pair to new PF. */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MOD \\\n \t\tUINT32_C(0x5)\n-\t/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */\n+\t/*\n+\t * Modify existing rep2fn pairs paired with same PF and move pairs\n+\t * to new PF.\n+\t */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_MODALL \\\n \t\tUINT32_C(0x6)\n-\t/* Truflow pair between REP on local host with PF or VF on specified host. */\n+\t/*\n+\t * Truflow pair between REP on local host with PF or VF on specified\n+\t * host.\n+\t */\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_REP2FN_TRUFLOW \\\n \t\tUINT32_C(0x7)\n \t#define HWRM_CFA_PAIR_ALLOC_INPUT_PAIR_MODE_LAST \\\n@@ -37991,8 +40094,9 @@ struct hwrm_cfa_pair_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38056,9 +40160,15 @@ struct hwrm_cfa_pair_free_input {\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_PFPAIR         UINT32_C(0x4)\n \t/* Modify existing rep2fn pair and move pair to new PF. */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MOD     UINT32_C(0x5)\n-\t/* Modify existing rep2fn pairs paired with same PF and move pairs to new PF. */\n+\t/*\n+\t * Modify existing rep2fn pairs paired with same PF and move pairs\n+\t * to new PF.\n+\t */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_MODALL  UINT32_C(0x6)\n-\t/* Truflow pair between REP on local host with PF or VF on specified host. */\n+\t/*\n+\t * Truflow pair between REP on local host with PF or VF on\n+\t * specified host.\n+\t */\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW UINT32_C(0x7)\n \t#define HWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_LAST \\\n \t\tHWRM_CFA_PAIR_FREE_INPUT_PAIR_MODE_REP2FN_TRUFLOW\n@@ -38079,8 +40189,9 @@ struct hwrm_cfa_pair_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38200,8 +40311,9 @@ struct hwrm_cfa_pair_info_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38272,8 +40384,9 @@ struct hwrm_cfa_vfr_alloc_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38340,8 +40453,9 @@ struct hwrm_cfa_vfr_free_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38428,7 +40542,10 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \t/* IPV4 over virtual eXtensible Local Area Network (IPV4oVXLAN) */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_V4 \\\n \t\tUINT32_C(0x200)\n-\t/* Enhance Generic Routing Encapsulation (GRE version 1) inside IP datagram payload */\n+\t/*\n+\t * Enhance Generic Routing Encapsulation (GRE version 1) inside IP\n+\t * datagram payload\n+\t */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_IPGRE_V1 \\\n \t\tUINT32_C(0x400)\n \t/* Any tunneled traffic */\n@@ -38437,7 +40554,10 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \t/* Use fixed layer 2 ether type of 0xFFFF */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_L2_ETYPE \\\n \t\tUINT32_C(0x1000)\n-\t/* IPV6 over virtual eXtensible Local Area Network with GPE header (IPV6oVXLANGPE) */\n+\t/*\n+\t * IPV6 over virtual eXtensible Local Area Network with GPE header\n+\t * (IPV6oVXLANGPE)\n+\t */\n \t#define HWRM_CFA_REDIRECT_QUERY_TUNNEL_TYPE_OUTPUT_TUNNEL_MASK_VXLAN_GPE_V6 \\\n \t\tUINT32_C(0x2000)\n \tuint8_t\tunused_0[3];\n@@ -38445,8 +40565,9 @@ struct hwrm_cfa_redirect_query_tunnel_type_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38493,7 +40614,10 @@ struct hwrm_cfa_ctx_mem_rgtr_input {\n \t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n \t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n-\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n \t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n \t#define HWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LAST \\\n \t\tHWRM_CFA_CTX_MEM_RGTR_INPUT_PAGE_LEVEL_LVL_2\n@@ -38533,8 +40657,8 @@ struct hwrm_cfa_ctx_mem_rgtr_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * Id/Handle to the recently register context memory. This handle is passed\n-\t * to the CFA feature.\n+\t * Id/Handle to the recently register context memory. This handle is\n+\t * passed to the CFA feature.\n \t */\n \tuint16_t\tctx_id;\n \tuint8_t\tunused_0[5];\n@@ -38542,8 +40666,9 @@ struct hwrm_cfa_ctx_mem_rgtr_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38584,8 +40709,8 @@ struct hwrm_cfa_ctx_mem_unrgtr_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * Id/Handle to the recently register context memory. This handle is passed\n-\t * to the CFA feature.\n+\t * Id/Handle to the recently register context memory. This handle is\n+\t * passed to the CFA feature.\n \t */\n \tuint16_t\tctx_id;\n \tuint8_t\tunused_0[6];\n@@ -38606,8 +40731,9 @@ struct hwrm_cfa_ctx_mem_unrgtr_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38648,8 +40774,8 @@ struct hwrm_cfa_ctx_mem_qctx_input {\n \t */\n \tuint64_t\tresp_addr;\n \t/*\n-\t * Id/Handle to the recently register context memory. This handle is passed\n-\t * to the CFA feature.\n+\t * Id/Handle to the recently register context memory. This handle is\n+\t * passed to the CFA feature.\n \t */\n \tuint16_t\tctx_id;\n \tuint8_t\tunused_0[6];\n@@ -38672,7 +40798,10 @@ struct hwrm_cfa_ctx_mem_qctx_output {\n \t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_0 UINT32_C(0x0)\n \t/* PBL pointer points to PTE table. */\n \t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_1 UINT32_C(0x1)\n-\t/* PBL pointer points to PDE table with each entry pointing to PTE tables. */\n+\t/*\n+\t * PBL pointer points to PDE table with each entry pointing to PTE\n+\t * tables.\n+\t */\n \t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2 UINT32_C(0x2)\n \t#define HWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LAST \\\n \t\tHWRM_CFA_CTX_MEM_QCTX_OUTPUT_PAGE_LEVEL_LVL_2\n@@ -38704,8 +40833,9 @@ struct hwrm_cfa_ctx_mem_qctx_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38757,15 +40887,19 @@ struct hwrm_cfa_ctx_mem_qcaps_output {\n \tuint16_t\tseq_id;\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n-\t/* Indicates the maximum number of context memory which can be registered. */\n+\t/*\n+\t * Indicates the maximum number of context memory which can be\n+\t * registered.\n+\t */\n \tuint16_t\tmax_entries;\n \tuint8_t\tunused_0[5];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -38831,53 +40965,53 @@ struct hwrm_cfa_counter_qcaps_output {\n \t\tHWRM_CFA_COUNTER_QCAPS_OUTPUT_FLAGS_COUNTER_FORMAT_64_BIT\n \tuint32_t\tunused_0;\n \t/*\n-\t * Minimum guaranteed number of flow counters supported for this function,\n-\t * in RX direction.\n+\t * Minimum guaranteed number of flow counters supported for this\n+\t * function, in RX direction.\n \t */\n \tuint32_t\tmin_rx_fc;\n \t/*\n-\t * Maximum non-guaranteed number of flow counters supported for this function,\n-\t * in RX direction.\n+\t * Maximum non-guaranteed number of flow counters supported for this\n+\t * function, in RX direction.\n \t */\n \tuint32_t\tmax_rx_fc;\n \t/*\n-\t * Minimum guaranteed number of flow counters supported for this function,\n-\t * in TX direction.\n+\t * Minimum guaranteed number of flow counters supported for this\n+\t * function, in TX direction.\n \t */\n \tuint32_t\tmin_tx_fc;\n \t/*\n-\t * Maximum non-guaranteed number of flow counters supported for this function,\n-\t * in TX direction.\n+\t * Maximum non-guaranteed number of flow counters supported for this\n+\t * function, in TX direction.\n \t */\n \tuint32_t\tmax_tx_fc;\n \t/*\n-\t * Minimum guaranteed number of extension flow counters supported for this\n-\t * function, in RX direction.\n+\t * Minimum guaranteed number of extension flow counters supported for\n+\t * this function, in RX direction.\n \t */\n \tuint32_t\tmin_rx_efc;\n \t/*\n-\t * Maximum non-guaranteed number of extension flow counters supported for\n-\t * this function, in RX direction.\n+\t * Maximum non-guaranteed number of extension flow counters supported\n+\t * for this function, in RX direction.\n \t */\n \tuint32_t\tmax_rx_efc;\n \t/*\n-\t * Minimum guaranteed number of extension flow counters supported for this\n-\t * function, in TX direction.\n+\t * Minimum guaranteed number of extension flow counters supported for\n+\t * this function, in TX direction.\n \t */\n \tuint32_t\tmin_tx_efc;\n \t/*\n-\t * Maximum non-guaranteed number of extension flow counters supported for\n-\t * this function, in TX direction.\n+\t * Maximum non-guaranteed number of extension flow counters supported\n+\t * for this function, in TX direction.\n \t */\n \tuint32_t\tmax_tx_efc;\n \t/*\n-\t * Minimum guaranteed number of meter drop counters supported for this\n-\t * function, in RX direction.\n+\t * Minimum guaranteed number of meter drop counters supported for\n+\t * this function, in RX direction.\n \t */\n \tuint32_t\tmin_rx_mdc;\n \t/*\n-\t * Maximum non-guaranteed number of meter drop counters supported for this\n-\t * function, in RX direction.\n+\t * Maximum non-guaranteed number of meter drop counters supported for\n+\t * this function, in RX direction.\n \t */\n \tuint32_t\tmax_rx_mdc;\n \t/*\n@@ -38886,19 +41020,23 @@ struct hwrm_cfa_counter_qcaps_output {\n \t */\n \tuint32_t\tmin_tx_mdc;\n \t/*\n-\t * Maximum non-guaranteed number of meter drop counters supported for this\n-\t * function, in TX direction.\n+\t * Maximum non-guaranteed number of meter drop counters supported for\n+\t * this function, in TX direction.\n \t */\n \tuint32_t\tmax_tx_mdc;\n-\t/* Maximum guaranteed number of flow counters which can be used during flow alloc. */\n+\t/*\n+\t * Maximum guaranteed number of flow counters which can be used during\n+\t * flow alloc.\n+\t */\n \tuint32_t\tmax_flow_alloc_fc;\n \tuint8_t\tunused_1[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39009,8 +41147,9 @@ struct hwrm_cfa_counter_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39084,8 +41223,9 @@ struct hwrm_cfa_counter_qstats_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39172,14 +41312,14 @@ struct hwrm_cfa_eem_qcaps_output {\n \t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_PATH_RX \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * When set to 1, indicates the FW supports the Centralized\n+\t * When set to 1, indicates the the FW supports the Centralized\n \t * Memory Model. The concept designates one entity for the\n \t * memory allocation while all others ‘subscribe’ to it.\n \t */\n \t#define HWRM_CFA_EEM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * When set to 1, indicates the FW supports the Detached\n+\t * When set to 1, indicates the the FW supports the Detached\n \t * Centralized Memory Model. The memory is allocated and managed\n \t * as a separate entity. All PFs and VFs will be granted direct\n \t * or semi-direct access to the allocated memory while none of\n@@ -39215,17 +41355,21 @@ struct hwrm_cfa_eem_qcaps_output {\n \t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_EXTERNAL_FLOW_COUNTERS_TABLE \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * If set to 1, then FID table used for implicit flow flush is supported.\n-\t * If set to 0, then FID table used for implicit flow flush is not supported.\n+\t * If set to 1, then FID table used for implicit flow flush is\n+\t * supported.\n+\t * If set to 0, then FID table used for implicit flow flush is\n+\t * not supported.\n \t */\n \t#define HWRM_CFA_EEM_QCAPS_OUTPUT_SUPPORTED_FID_TABLE \\\n \t\tUINT32_C(0x10)\n \t/*\n-\t * The maximum number of entries supported by EEM. When configuring the host memory\n-\t * the number of numbers of entries that can supported are -\n-\t *      32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M entries.\n-\t * Any value that are not these values, the FW will round down to the closest support\n-\t * number of entries.\n+\t * The maximum number of entries supported by EEM. When configuring\n+\t * the host memory, the number of numbers of entries that can\n+\t * supported are:\n+\t *     32k, 64k 128k, 256k, 512k, 1M, 2M, 4M, 8M, 32M, 64M, 128M\n+\t *     entries.\n+\t * Any value that are not these values, the FW will round down to the\n+\t * closest support number of entries.\n \t */\n \tuint32_t\tmax_entries_supported;\n \t/* The entry size in bytes of each entry in the EEM KEY0/KEY1 tables. */\n@@ -39241,8 +41385,9 @@ struct hwrm_cfa_eem_qcaps_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39310,9 +41455,10 @@ struct hwrm_cfa_eem_cfg_input {\n \tuint16_t\tgroup_id;\n \tuint16_t\tunused_0;\n \t/*\n-\t * Configured EEM with the given number of entries. All the EEM tables KEY0, KEY1,\n-\t * RECORD, EFC all have the same number of entries and all tables will be configured\n-\t * using this value. Current minimum value is 32k. Current maximum value is 128M.\n+\t * Configured EEM with the given number of entries. All the EEM tables\n+\t * KEY0, KEY1, RECORD, EFC all have the same number of entries and all\n+\t * tables will be configured using this value. Current minimum value\n+\t * is 32k. Current maximum value is 128M.\n \t */\n \tuint32_t\tnum_entries;\n \tuint32_t\tunused_1;\n@@ -39345,8 +41491,9 @@ struct hwrm_cfa_eem_cfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39431,8 +41578,9 @@ struct hwrm_cfa_eem_qcfg_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39528,8 +41676,9 @@ struct hwrm_cfa_eem_op_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39596,24 +41745,26 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_HND_64BIT_SUPPORTED \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * Value of 1 to indicate firmware support flow batch delete operation through\n-\t * HWRM_CFA_FLOW_FLUSH command.\n-\t * Value of 0 to indicate that the firmware does not support flow batch delete\n-\t * operation.\n+\t * Value of 1 to indicate firmware support flow batch delete\n+\t * operation through HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 to indicate that the firmware does not support flow\n+\t * batch delete operation.\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_BATCH_DELETE_SUPPORTED \\\n \t\tUINT32_C(0x4)\n \t/*\n-\t * Value of 1 to indicate that the firmware support flow reset all operation through\n-\t * HWRM_CFA_FLOW_FLUSH command.\n-\t * Value of 0 indicates firmware does not support flow reset all operation.\n+\t * Value of 1 to indicate that the firmware support flow reset all\n+\t * operation through HWRM_CFA_FLOW_FLUSH command.\n+\t * Value of 0 indicates firmware does not support flow reset all\n+\t * operation.\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_RESET_ALL_SUPPORTED \\\n \t\tUINT32_C(0x8)\n \t/*\n-\t * Value of 1 to indicate that firmware supports use of FID as dest_id in\n-\t * HWRM_CFA_NTUPLE_ALLOC/CFG commands.\n-\t * Value of 0 indicates firmware does not support use of FID as dest_id.\n+\t * Value of 1 to indicate that firmware supports use of FID as\n+\t * dest_id in HWRM_CFA_NTUPLE_ALLOC/CFG commands.\n+\t * Value of 0 indicates firmware does not support use of FID as\n+\t * dest_id.\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_DEST_FUNC_SUPPORTED \\\n \t\tUINT32_C(0x10)\n@@ -39630,10 +41781,10 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_RX_EEM_FLOW_SUPPORTED \\\n \t\tUINT32_C(0x40)\n \t/*\n-\t * Value of 1 to indicate that firmware supports the dynamic allocation of an\n-\t * on-chip flow counter which can be used for EEM flows.\n-\t * Value of 0 indicates firmware does not support the dynamic allocation of an\n-\t * on-chip flow counter.\n+\t * Value of 1 to indicate that firmware supports the dynamic\n+\t * allocation of an on-chip flow counter which can be used for EEM\n+\t * flows. Value of 0 indicates firmware does not support the dynamic\n+\t * allocation of an on-chip flow counter.\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_FLOW_COUNTER_ALLOC_SUPPORTED \\\n \t\tUINT32_C(0x80)\n@@ -39689,13 +41840,28 @@ struct hwrm_cfa_adv_flow_mgnt_qcaps_output {\n \t */\n \t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_NTUPLE_FLOW_RX_ETHERTYPE_IP_SUPPORTED \\\n \t\tUINT32_C(0x4000)\n+\t/*\n+\t * When this bit is '1', it indicates that core firmware is\n+\t * capable of TruFlow. Driver can restrict sending HWRM CFA_FLOW_XXX\n+\t * and CFA_ENCAP_XXX, CFA_DECAP_XXX commands.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_TRUFLOW_CAPABLE \\\n+\t\tUINT32_C(0x8000)\n+\t/*\n+\t * If set to 1, firmware is capable of supporting L2/ROCE as\n+\t * traffic type in flags field of HWRM_CFA_L2_FILTER_ALLOC command.\n+\t * By default, this flag should be 0 for older version of firmware.\n+\t */\n+\t#define HWRM_CFA_ADV_FLOW_MGNT_QCAPS_OUTPUT_FLAGS_L2_FILTER_TRAFFIC_TYPE_L2_ROCE_SUPPORTED \\\n+\t\tUINT32_C(0x10000)\n \tuint8_t\tunused_0[3];\n \t/*\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -39769,8 +41935,9 @@ struct hwrm_cfa_tflib_output {\n \t * This field is used in Output records to indicate that the output\n \t * is completely written to RAM. This field should be read as '1'\n \t * to indicate that the output has been completely written.\n-\t * When writing a command completion or response to an internal processor,\n-\t * the order of writes has to be such that this field is written last.\n+\t * When writing a command completion or response to an internal\n+\t * processor, the order of writes has to be such that this field is\n+\t * written last.\n \t */\n \tuint8_t\tvalid;\n } __rte_packed;\n@@ -41016,8 +43183,8 @@ struct hwrm_tf_ctxt_mem_alloc_input {\n \tuint64_t\tresp_addr;\n \t/* Size in KB of memory to be allocated. */\n \tuint32_t\tmem_size;\n-\t/* unused. */\n-\tuint32_t\tunused0;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n } __rte_packed;\n \n /* hwrm_tf_ctxt_mem_alloc_output (size:192b/24B) */\n@@ -41032,6 +43199,8 @@ struct hwrm_tf_ctxt_mem_alloc_output {\n \tuint16_t\tresp_len;\n \t/* Pointer to the PBL, or PDL depending on number of levels */\n \tuint64_t\tpage_dir;\n+\t/* Size of memory allocated. */\n+\tuint32_t\tmem_size;\n \t/* Counter PBL indirect levels. */\n \tuint8_t\tpage_level;\n \t/* PBL pointer is physical start address. */\n@@ -41072,7 +43241,7 @@ struct hwrm_tf_ctxt_mem_alloc_output {\n \t#define HWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_LAST \\\n \t\tHWRM_TF_CTXT_MEM_ALLOC_OUTPUT_PAGE_SIZE_1G\n \t/* unused. */\n-\tuint8_t\tunused0[5];\n+\tuint8_t\tunused0;\n \t/*\n \t * This field is used in Output records to indicate that the\n \t * output is completely written to RAM. This field should be\n@@ -41089,7 +43258,7 @@ struct hwrm_tf_ctxt_mem_alloc_output {\n  *************************/\n \n \n-/* hwrm_tf_ctxt_mem_free_input (size:256b/32B) */\n+/* hwrm_tf_ctxt_mem_free_input (size:320b/40B) */\n struct hwrm_tf_ctxt_mem_free_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -41119,8 +43288,8 @@ struct hwrm_tf_ctxt_mem_free_input {\n \t * point to a physically contiguous block of memory.\n \t */\n \tuint64_t\tresp_addr;\n-\t/* Pointer to the PBL, or PDL depending on number of levels */\n-\tuint64_t\tpage_dir;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* Counter PBL indirect levels. */\n \tuint8_t\tpage_level;\n \t/* PBL pointer is physical start address. */\n@@ -41161,7 +43330,13 @@ struct hwrm_tf_ctxt_mem_free_input {\n \t#define HWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_LAST \\\n \t\tHWRM_TF_CTXT_MEM_FREE_INPUT_PAGE_SIZE_1G\n \t/* unused. */\n-\tuint8_t\tunused0[6];\n+\tuint8_t\tunused0[2];\n+\t/* Pointer to the PBL, or PDL depending on number of levels */\n+\tuint64_t\tpage_dir;\n+\t/* Size of memory allocated. */\n+\tuint32_t\tmem_size;\n+\t/* unused. */\n+\tuint8_t\tunused1[4];\n } __rte_packed;\n \n /* hwrm_tf_ctxt_mem_free_output (size:128b/16B) */\n@@ -41263,8 +43438,8 @@ struct hwrm_tf_ctxt_mem_rgtr_input {\n \t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G   UINT32_C(0x12)\n \t#define HWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_LAST \\\n \t\tHWRM_TF_CTXT_MEM_RGTR_INPUT_PAGE_SIZE_1G\n-\t/* unused. */\n-\tuint32_t\tunused0;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* Pointer to the PBL, or PDL depending on number of levels */\n \tuint64_t\tpage_dir;\n } __rte_packed;\n@@ -41338,7 +43513,9 @@ struct hwrm_tf_ctxt_mem_unrgtr_input {\n \t */\n \tuint16_t\tctx_id;\n \t/* unused. */\n-\tuint8_t\tunused0[6];\n+\tuint8_t\tunused0[2];\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n } __rte_packed;\n \n /* hwrm_tf_ctxt_mem_unrgtr_output (size:128b/16B) */\n@@ -41415,8 +43592,8 @@ struct hwrm_tf_ext_em_qcaps_input {\n \t/* When set to 1, all offloaded flows will be sent to EXT EM. */\n \t#define HWRM_TF_EXT_EM_QCAPS_INPUT_FLAGS_PREFERRED_OFFLOAD \\\n \t\tUINT32_C(0x2)\n-\t/* unused. */\n-\tuint32_t\tunused0;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n } __rte_packed;\n \n /* hwrm_tf_ext_em_qcaps_output (size:384b/48B) */\n@@ -41431,14 +43608,14 @@ struct hwrm_tf_ext_em_qcaps_output {\n \tuint16_t\tresp_len;\n \tuint32_t\tflags;\n \t/*\n-\t * When set to 1, indicates the FW supports the Centralized\n+\t * When set to 1, indicates the the FW supports the Centralized\n \t * Memory Model. The concept designates one entity for the\n \t * memory allocation while all others ‘subscribe’ to it.\n \t */\n \t#define HWRM_TF_EXT_EM_QCAPS_OUTPUT_FLAGS_CENTRALIZED_MEMORY_MODEL_SUPPORTED \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * When set to 1, indicates the FW supports the Detached\n+\t * When set to 1, indicates the the FW supports the Detached\n \t * Centralized Memory Model. The memory is allocated and managed\n \t * as a separate entity. All PFs and VFs will be granted direct\n \t * or semi-direct access to the allocated memory while none of\n@@ -41531,13 +43708,8 @@ struct hwrm_tf_ext_em_qcaps_output {\n \t * table scopes.\n \t */\n \tuint32_t\tmax_static_buckets;\n-\t/*\n-\t * Maximum number of all (static and dynamic) buckets that can\n-\t * be assigned to lookup table scopes.\n-\t */\n-\tuint32_t\tmax_total_buckets;\n \t/* unused. */\n-\tuint8_t\tunused1[3];\n+\tuint8_t\tunused1[7];\n \t/*\n \t * This field is used in Output records to indicate that the\n \t * output is completely written to RAM. This field should be\n@@ -41554,7 +43726,7 @@ struct hwrm_tf_ext_em_qcaps_output {\n  *********************/\n \n \n-/* hwrm_tf_ext_em_op_input (size:192b/24B) */\n+/* hwrm_tf_ext_em_op_input (size:256b/32B) */\n struct hwrm_tf_ext_em_op_input {\n \t/* The HWRM command request type. */\n \tuint16_t\treq_type;\n@@ -41625,6 +43797,10 @@ struct hwrm_tf_ext_em_op_input {\n \t\tHWRM_TF_EXT_EM_OP_INPUT_OP_EXT_EM_CLEANUP\n \t/* unused. */\n \tuint16_t\tunused1;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n+\t/* unused. */\n+\tuint32_t\tunused2;\n } __rte_packed;\n \n /* hwrm_tf_ext_em_op_output (size:128b/16B) */\n@@ -41803,12 +43979,6 @@ struct hwrm_tf_ext_em_cfg_input {\n \t */\n \t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_STATIC_BUCKETS \\\n \t\tUINT32_C(0x1000)\n-\t/*\n-\t * This bit must be '1' for the lkup_dynamic_buckets field to be\n-\t * configured.\n-\t */\n-\t#define HWRM_TF_EXT_EM_CFG_INPUT_ENABLES_LKUP_DYNAMIC_BUCKETS \\\n-\t\tUINT32_C(0x2000)\n \t/* Configured EXT EM with the given context if for KEY0 table. */\n \tuint16_t\tkey0_ctx_id;\n \t/* Configured EXT EM with the given context if for KEY1 table. */\n@@ -41834,8 +44004,8 @@ struct hwrm_tf_ext_em_cfg_input {\n \t * of table scope.\n \t */\n \tuint32_t\tlkup_static_buckets;\n-\t/* Number of 32B dynamic buckets to be allocated. */\n-\tuint32_t\tlkup_dynamic_buckets;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n \t/* unused. */\n \tuint32_t\tunused2;\n } __rte_packed;\n@@ -41908,8 +44078,8 @@ struct hwrm_tf_ext_em_qcfg_input {\n \t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n \t#define HWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_LAST \\\n \t\tHWRM_TF_EXT_EM_QCFG_INPUT_FLAGS_DIR_TX\n-\t/* unused. */\n-\tuint32_t\tunused0;\n+\t/* Firmware session id returned when HWRM_TF_SESSION_OPEN is sent. */\n+\tuint32_t\tfw_session_id;\n } __rte_packed;\n \n /* hwrm_tf_ext_em_qcfg_output (size:448b/56B) */\n@@ -41992,9 +44162,6 @@ struct hwrm_tf_ext_em_qcfg_output {\n \t/* This bit must be '1' for the lkup_static_buckets field is set. */\n \t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_STATIC_BUCKETS \\\n \t\tUINT32_C(0x1000)\n-\t/* This bit must be '1' for the lkup_dynamic_buckets field is set. */\n-\t#define HWRM_TF_EXT_EM_QCFG_OUTPUT_SUPPORTED_LKUP_DYNAMIC_BUCKETS \\\n-\t\tUINT32_C(0x2000)\n \t/*\n \t * Group id is used by firmware to identify memory pools belonging\n \t * to certain group.\n@@ -42017,10 +44184,8 @@ struct hwrm_tf_ext_em_qcfg_output {\n \t * of table scope.\n \t */\n \tuint32_t\tlkup_static_buckets;\n-\t/* Number of 32B dynamic buckets to be allocated. */\n-\tuint32_t\tlkup_dynamic_buckets;\n \t/* unused. */\n-\tuint8_t\tunused2[3];\n+\tuint8_t\tunused2[7];\n \t/*\n \t * This field is used in Output records to indicate that the\n \t * output is completely written to RAM. This field should be\n@@ -42113,6 +44278,87 @@ struct hwrm_tf_em_insert_output {\n \tuint32_t\tunused0;\n } __rte_packed;\n \n+/**************************\n+ * hwrm_tf_em_hash_insert *\n+ **************************/\n+\n+\n+/* hwrm_tf_em_hash_insert_input (size:1024b/128B) */\n+struct hwrm_tf_em_hash_insert_input {\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/*\n+\t * The completion ring to send the completion event on. This should\n+\t * be the NQ ID returned from the `nq_alloc` HWRM command.\n+\t */\n+\tuint16_t\tcmpl_ring;\n+\t/*\n+\t * The sequence ID is used by the driver for tracking multiple\n+\t * commands. This ID is treated as opaque data by the firmware and\n+\t * the value is returned in the `hwrm_resp_hdr` upon completion.\n+\t */\n+\tuint16_t\tseq_id;\n+\t/*\n+\t * The target ID of the command:\n+\t * * 0x0-0xFFF8 - The function ID\n+\t * * 0xFFF8-0xFFFC, 0xFFFE - Reserved for internal processors\n+\t * * 0xFFFD - Reserved for user-space HWRM interface\n+\t * * 0xFFFF - HWRM\n+\t */\n+\tuint16_t\ttarget_id;\n+\t/*\n+\t * A physical address pointer pointing to a host buffer that the\n+\t * command's response data will be written. This can be either a host\n+\t * physical address (HPA) or a guest physical address (GPA) and must\n+\t * point to a physically contiguous block of memory.\n+\t */\n+\tuint64_t\tresp_addr;\n+\t/* Firmware Session Id. */\n+\tuint32_t\tfw_session_id;\n+\t/* Control Flags. */\n+\tuint16_t\tflags;\n+\t/* Indicates the flow direction. */\n+\t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR     UINT32_C(0x1)\n+\t/* If this bit set to 0, then it indicates rx flow. */\n+\t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_RX    UINT32_C(0x0)\n+\t/* If this bit is set to 1, then it indicates that tx flow. */\n+\t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX    UINT32_C(0x1)\n+\t#define HWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_LAST \\\n+\t\tHWRM_TF_EM_HASH_INSERT_INPUT_FLAGS_DIR_TX\n+\t/* Number of bits in the EM record. */\n+\tuint16_t\tem_record_size_bits;\n+\t/* CRC32 hash of key. */\n+\tuint32_t\tkey0_hash;\n+\t/* Lookup3 hash of key. */\n+\tuint32_t\tkey1_hash;\n+\t/* Index of EM record. */\n+\tuint32_t\tem_record_idx;\n+\t/* Unused. */\n+\tuint32_t\tunused0;\n+\t/* EM record. */\n+\tuint64_t\tem_record[11];\n+} __rte_packed;\n+\n+/* hwrm_tf_em_hash_insert_output (size:128b/16B) */\n+struct hwrm_tf_em_hash_insert_output {\n+\t/* The specific error status for the command. */\n+\tuint16_t\terror_code;\n+\t/* The HWRM command request type. */\n+\tuint16_t\treq_type;\n+\t/* The sequence ID from the original command. */\n+\tuint16_t\tseq_id;\n+\t/* The length of the response data in number of bytes. */\n+\tuint16_t\tresp_len;\n+\t/* EM record pointer index. */\n+\tuint16_t\trptr_index;\n+\t/* EM record offset 0~3. */\n+\tuint8_t\trptr_entry;\n+\t/* Number of word entries consumed by the key. */\n+\tuint8_t\tnum_of_entries;\n+\t/* unused. */\n+\tuint32_t\tunused0;\n+} __rte_packed;\n+\n /*********************\n  * hwrm_tf_em_delete *\n  *********************/\n@@ -44742,10 +46988,7 @@ struct hwrm_nvm_write_input {\n \t * This is where the source data is.\n \t */\n \tuint64_t\thost_src_addr;\n-\t/*\n-\t * The Directory Entry Type (valid values are defined in the bnxnvm\n-\t * directory_type enum defined in the file bnxnvm_defs.h).\n-\t */\n+\t/* The Directory Entry Type (valid values are defined in the bnxnvm_directory_type enum defined in the file bnxnvm_defs.h). */\n \tuint16_t\tdir_type;\n \t/*\n \t * Directory ordinal.\n@@ -44757,10 +47000,8 @@ struct hwrm_nvm_write_input {\n \t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* in the file bnxnvm_defs.h). */\n \tuint16_t\tdir_attr;\n \t/*\n-\t * Length of data to write, in bytes. May be less than or equal to the allocated\n-\t * size for the directory entry.\n-\t * The data length stored in the directory entry will be updated to reflect\n-\t * this value once the write is complete.\n+\t * Length of data to write, in bytes. May be less than or equal to the allocated size for the directory entry.\n+\t * The data length stored in the directory entry will be updated to reflect this value once the write is complete.\n \t */\n \tuint32_t\tdir_data_length;\n \t/* Option. */\n@@ -44773,15 +47014,11 @@ struct hwrm_nvm_write_input {\n \t#define HWRM_NVM_WRITE_INPUT_FLAGS_KEEP_ORIG_ACTIVE_IMG \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * The requested length of the allocated NVM for the item, in bytes. This\n-\t * value may be greater than or equal to the specified data length (dir_data_length).\n+\t * The requested length of the allocated NVM for the item, in bytes. This value may be greater than or equal to the specified data length (dir_data_length).\n \t * If this value is less than the specified data length, it will be ignored.\n-\t * The response will contain the actual allocated item length, which may be\n-\t * greater than the requested item length.\n-\t * The purpose for allocating more than the required number of bytes for\n-\t * an item's data is to pre-allocate extra storage (padding) to accommodate\n-\t * the potential future growth of an item (e.g. upgraded firmware with a\n-\t * size increase, log growth, expanded configuration data).\n+\t * The response will contain the actual allocated item length, which may be greater than the requested item length.\n+\t * The purpose for allocating more than the required number of bytes for an item's data is to pre-allocate extra storage (padding) to accommodate\n+\t * the potential future growth of an item (e.g. upgraded firmware with a size increase, log growth, expanded configuration data).\n \t */\n \tuint32_t\tdir_item_length;\n \tuint32_t\tunused_0;\n@@ -44798,11 +47035,8 @@ struct hwrm_nvm_write_output {\n \t/* The length of the response data in number of bytes. */\n \tuint16_t\tresp_len;\n \t/*\n-\t * Length of the allocated NVM for the item, in bytes. The value may be\n-\t * greater than or equal to the specified data length or the requested\n-\t * item length.\n-\t * The actual item length used when creating a new directory entry will be\n-\t * a multiple of an NVM block size.\n+\t * Length of the allocated NVM for the item, in bytes. The value may be greater than or equal to the specified data length or the requested item length.\n+\t * The actual item length used when creating a new directory entry will be a multiple of an NVM block size.\n \t */\n \tuint32_t\tdir_item_length;\n \t/* The directory index of the created or modified item. */\n@@ -45146,10 +47380,7 @@ struct hwrm_nvm_get_dev_info_output {\n \t/* Total size, in bytes of the NVRAM device. */\n \tuint32_t\tnvram_size;\n \tuint32_t\treserved_size;\n-\t/*\n-\t * Available size that can be used, in bytes.  Available size is the\n-\t * NVRAM size take away the used size and reserved size.\n-\t */\n+\t/* Available size that can be used, in bytes.  Available size is the NVRAM size take away the used size and reserved size. */\n \tuint32_t\tavailable_size;\n \t/* This field represents the major version of NVM cfg */\n \tuint8_t\tnvm_cfg_ver_maj;\n@@ -45291,15 +47522,9 @@ struct hwrm_nvm_mod_dir_entry_input {\n \t * The (0-based) instance of this Directory Type.\n \t */\n \tuint16_t\tdir_ordinal;\n-\t/*\n-\t * The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension\n-\t * flag definitions).\n-\t */\n+\t/* The Directory Entry Extension flags (see BNX_DIR_EXT_* for extension flag definitions). */\n \tuint16_t\tdir_ext;\n-\t/*\n-\t * Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag\n-\t * definitions).\n-\t */\n+\t/* Directory Entry Attribute flags (see BNX_DIR_ATTR_* for attribute flag definitions). */\n \tuint16_t\tdir_attr;\n \t/*\n \t * If valid, then this field updates the checksum\n@@ -45466,16 +47691,13 @@ struct hwrm_nvm_install_update_input {\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ERASE_UNUSED_SPACE \\\n \t\tUINT32_C(0x1)\n \t/*\n-\t * If set to 1, then unspecified images, images not in the package file,\n-\t * will be safely deleted.\n-\t * When combined with erase_unused_space then unspecified images will be\n-\t * securely erased.\n+\t * If set to 1, then unspecified images, images not in the package file, will be safely deleted.\n+\t * When combined with erase_unused_space then unspecified images will be securely erased.\n \t */\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_REMOVE_UNUSED_PKG \\\n \t\tUINT32_C(0x2)\n \t/*\n-\t * If set to 1, FW will defragment the NVM if defragmentation is required\n-\t * for the update.\n+\t * If set to 1, FW will defragment the NVM if defragmentation is required for the update.\n \t * Allow additional time for this command to complete if this bit is set to 1.\n \t */\n \t#define HWRM_NVM_INSTALL_UPDATE_INPUT_FLAGS_ALLOWED_TO_DEFRAG \\\n@@ -45855,10 +48077,7 @@ struct hwrm_nvm_set_variable_input {\n \t/* index for the 4th dimensions */\n \tuint16_t\tindex_3;\n \tuint8_t\tflags;\n-\t/*\n-\t * When this bit is 1, flush internal cache after this write operation\n-\t * (see hwrm_nvm_flush command.)\n-\t */\n+\t/* When this bit is 1, flush internal cache after this write operation (see hwrm_nvm_flush command.) */\n \t#define HWRM_NVM_SET_VARIABLE_INPUT_FLAGS_FORCE_FLUSH \\\n \t\tUINT32_C(0x1)\n \t/* encryption method */\n@@ -46160,10 +48379,7 @@ struct hwrm_fw_reset_input {\n \t */\n \t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_HOST \\\n \t\tUINT32_C(0x4)\n-\t/*\n-\t * AP processor complex (in multi-host environment). Use host_idx to\n-\t * control which core is reset\n-\t */\n+\t/* AP processor complex (in multi-host environment). Use host_idx to control which core is reset */\n \t#define HWRM_FW_RESET_INPUT_EMBEDDED_PROC_TYPE_AP \\\n \t\tUINT32_C(0x5)\n \t/* Reset all blocks of the chip (including all processors) */\n",
    "prefixes": [
        "05/11"
    ]
}