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GET /api/patches/88428/?format=api
{ "id": 88428, "url": "http://patchwork.dpdk.org/api/patches/88428/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/1614793612-91528-3-git-send-email-huawei.xhw@alibaba-inc.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1614793612-91528-3-git-send-email-huawei.xhw@alibaba-inc.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1614793612-91528-3-git-send-email-huawei.xhw@alibaba-inc.com", "date": "2021-03-03T17:46:52", "name": "[v9,2/2] bus/pci: support MMIO in PCI ioport accessors", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7df838a9edc33f95eb8011c4fbe392ecef7b4f36", "submitter": { "id": 1977, "url": "http://patchwork.dpdk.org/api/people/1977/?format=api", "name": "谢华伟(此时此刻）", "email": "huawei.xhw@alibaba-inc.com" }, "delegate": { "id": 24651, "url": "http://patchwork.dpdk.org/api/users/24651/?format=api", "username": "dmarchand", "first_name": "David", "last_name": "Marchand", "email": "david.marchand@redhat.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/1614793612-91528-3-git-send-email-huawei.xhw@alibaba-inc.com/mbox/", "series": [ { "id": 15477, "url": "http://patchwork.dpdk.org/api/series/15477/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=15477", "date": "2021-03-03T17:46:50", "name": "support both PIO and MMIO BAR for legacy device in virtio PMD", "version": 9, "mbox": "http://patchwork.dpdk.org/series/15477/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/88428/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/88428/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 7F980A055D;\n\tWed, 3 Mar 2021 18:47:15 +0100 (CET)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 462DF160728;\n\tWed, 3 Mar 2021 18:47:05 +0100 (CET)", "from out0-135.mail.aliyun.com (out0-135.mail.aliyun.com\n [140.205.0.135])\n by mails.dpdk.org (Postfix) with ESMTP id 4DCB416071D\n for <dev@dpdk.org>; Wed, 3 Mar 2021 18:47:02 +0100 (CET)", "from\n rs3a10040.et2sqa.z1.et2sqa.tbsite.net(mailfrom:huawei.xhw@alibaba-inc.com\n fp:SMTPD_---.JfzMLkz_1614793613) by smtp.aliyun-inc.com(127.0.0.1);\n Thu, 04 Mar 2021 01:47:00 +0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=alibaba-inc.com; s=default;\n t=1614793620; h=From:To:Subject:Date:Message-Id;\n bh=an+X3Fy7xY9SmwgC5epi0AVxDtFpTWHl8y6myahv4+8=;\n b=H6a3rOojPJgAmzZo5hJfNw8pLib/U253g1l9o0YkSxlhFy6heVKv+lG2YQfoj7oUEn06JSjyc4n7cLvN0JPuzkbztRT85wTAH9NzBaTgiQGeFhg+zJrMHNKVcQURWeYNSZn/gC8etmVYzY/bRB6JR+pmD6s4A7oFiAHaCdzICSo=", "X-Alimail-AntiSpam": "AC=PASS; BC=-1|-1; BR=01201311R931e4; CH=green;\n DM=||false|;\n DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018047199;\n MF=huawei.xhw@alibaba-inc.com; NM=1; PH=DS; RN=9; SR=0;\n TI=SMTPD_---.JfzMLkz_1614793613;", "From": "\" =?utf-8?b?6LCi5Y2O5LyfKOatpOaXtuatpOWIu++8iQ==?= \"\n <huawei.xhw@alibaba-inc.com>", "To": "ferruh.yigit@intel.com, maxime.coquelin@redhat.com,\n david.marchand@redhat.com", "Cc": "<dev@dpdk.org>, <anatoly.burakov@intel.com>, <xuemingl@nvidia.com>,\n <grive@u256.net>, <chenbo.xia@intel.com>, \" =?utf-8?b?6LCi5Y2O5LyfKOatpA==?=\n\t=?utf-8?b?5pe25q2k5Yi777yJ?= \" <huawei.xhw@alibaba-inc.com>", "Date": "Thu, 04 Mar 2021 01:46:52 +0800", "Message-Id": "<1614793612-91528-3-git-send-email-huawei.xhw@alibaba-inc.com>", "X-Mailer": "git-send-email 1.8.3.1", "In-Reply-To": "<1614793612-91528-1-git-send-email-huawei.xhw@alibaba-inc.com>", "References": "<1614614483-75891-1-git-send-email-huawei.xhw@alibaba-inc.com>\n <1614793612-91528-1-git-send-email-huawei.xhw@alibaba-inc.com>", "Subject": "[dpdk-dev] [PATCH v9 2/2] bus/pci: support MMIO in PCI ioport\n accessors", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: \"huawei.xhw\" <huawei.xhw@alibaba-inc.com>\n\nWith IO BAR, we get PIO(programmed IO) address.\nWith MMIO BAR, we get mapped virtual address.\nWe distinguish PIO(Programmed IO) and MMIO(memory mapped IO) by their address like how kernel does.\nioread/write8/16/32 is provided to access PIO/MMIO.\nBy the way, for virtio on arch other than x86, BAR flag indicates PIO but is mapped.\n\nSigned-off-by: huawei xie <huawei.xhw@alibaba-inc.com>\nReviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com>\n---\n drivers/bus/pci/linux/pci.c | 4 --\n drivers/bus/pci/linux/pci_uio.c | 156 +++++++++++++++++++++++++++++-----------\n 2 files changed, 113 insertions(+), 47 deletions(-)", "diff": "diff --git a/drivers/bus/pci/linux/pci.c b/drivers/bus/pci/linux/pci.c\nindex 0f38abf..0dc99e9 100644\n--- a/drivers/bus/pci/linux/pci.c\n+++ b/drivers/bus/pci/linux/pci.c\n@@ -715,8 +715,6 @@ int rte_pci_write_config(const struct rte_pci_device *device,\n \t\tbreak;\n #endif\n \tcase RTE_PCI_KDRV_IGB_UIO:\n-\t\tpci_uio_ioport_read(p, data, len, offset);\n-\t\tbreak;\n \tcase RTE_PCI_KDRV_UIO_GENERIC:\n \t\tpci_uio_ioport_read(p, data, len, offset);\n \t\tbreak;\n@@ -736,8 +734,6 @@ int rte_pci_write_config(const struct rte_pci_device *device,\n \t\tbreak;\n #endif\n \tcase RTE_PCI_KDRV_IGB_UIO:\n-\t\tpci_uio_ioport_write(p, data, len, offset);\n-\t\tbreak;\n \tcase RTE_PCI_KDRV_UIO_GENERIC:\n \t\tpci_uio_ioport_write(p, data, len, offset);\n \t\tbreak;\ndiff --git a/drivers/bus/pci/linux/pci_uio.c b/drivers/bus/pci/linux/pci_uio.c\nindex 01f2a40..0907051 100644\n--- a/drivers/bus/pci/linux/pci_uio.c\n+++ b/drivers/bus/pci/linux/pci_uio.c\n@@ -368,6 +368,8 @@\n \treturn -1;\n }\n \n+#define PIO_MAX 0x10000\n+\n #if defined(RTE_ARCH_X86)\n int\n pci_uio_ioport_map(struct rte_pci_device *dev, int bar,\n@@ -381,12 +383,6 @@\n \tunsigned long base;\n \tint i;\n \n-\tif (rte_eal_iopl_init() != 0) {\n-\t\tRTE_LOG(ERR, EAL, \"%s(): insufficient ioport permissions for PCI device %s\\n\",\n-\t\t\t__func__, dev->name);\n-\t\treturn -1;\n-\t}\n-\n \t/* open and read addresses of the corresponding resource in sysfs */\n \tsnprintf(filename, sizeof(filename), \"%s/\" PCI_PRI_FMT \"/resource\",\n \t\trte_pci_get_sysfs_path(), dev->addr.domain, dev->addr.bus,\n@@ -408,15 +404,27 @@\n \t\t&end_addr, &flags) < 0)\n \t\tgoto error;\n \n-\tif (!(flags & IORESOURCE_IO)) {\n-\t\tRTE_LOG(ERR, EAL, \"%s(): bar resource other than IO is not supported\\n\", __func__);\n-\t\tgoto error;\n-\t}\n-\tbase = (unsigned long)phys_addr;\n-\tRTE_LOG(INFO, EAL, \"%s(): PIO BAR %08lx detected\\n\", __func__, base);\n+\tif (flags & IORESOURCE_IO) {\n+\t\tif (rte_eal_iopl_init()) {\n+\t\t\tRTE_LOG(ERR, EAL, \"%s(): insufficient ioport permissions for PCI device %s\\n\",\n+\t\t\t\t__func__, dev->name);\n+\t\t\tgoto error;\n+\t\t}\n \n-\tif (base > UINT16_MAX)\n+\t\tbase = (unsigned long)phys_addr;\n+\t\tif (base > PIO_MAX) {\n+\t\t\tRTE_LOG(ERR, EAL, \"%s(): %08lx too large PIO resource\\n\", __func__, base);\n+\t\t\tgoto error;\n+\t\t}\n+\n+\t\tRTE_LOG(DEBUG, EAL, \"%s(): PIO BAR %08lx detected\\n\", __func__, base);\n+\t} else if (flags & IORESOURCE_MEM) {\n+\t\tbase = (unsigned long)dev->mem_resource[bar].addr;\n+\t\tRTE_LOG(DEBUG, EAL, \"%s(): MMIO BAR %08lx detected\\n\", __func__, base);\n+\t} else {\n+\t\tRTE_LOG(ERR, EAL, \"%s(): unknown BAR type\\n\", __func__);\n \t\tgoto error;\n+\t}\n \n \t/* FIXME only for primary process ? */\n \tif (dev->intr_handle.type == RTE_INTR_HANDLE_UNKNOWN) {\n@@ -517,6 +525,92 @@\n }\n #endif\n \n+#if defined(RTE_ARCH_X86)\n+static inline uint8_t ioread8(void *addr)\n+{\n+\tuint8_t val;\n+\n+\tval = (uint64_t)(uintptr_t)addr >= PIO_MAX ?\n+\t\t*(volatile uint8_t *)addr :\n+\t\tinb_p((unsigned long)addr);\n+\n+\treturn val;\n+}\n+\n+static inline uint16_t ioread16(void *addr)\n+{\n+\tuint16_t val;\n+\n+\tval = (uint64_t)(uintptr_t)addr >= PIO_MAX ?\n+\t\t*(volatile uint16_t *)addr :\n+\t\tinw_p((unsigned long)addr);\n+\n+\treturn val;\n+}\n+\n+static inline uint32_t ioread32(void *addr)\n+{\n+\tuint32_t val;\n+\n+\tval = (uint64_t)(uintptr_t)addr >= PIO_MAX ?\n+\t\t*(volatile uint32_t *)addr :\n+\t\tinl_p((unsigned long)addr);\n+\n+\treturn val;\n+}\n+\n+static inline void iowrite8(uint8_t val, void *addr)\n+{\n+\t(uint64_t)(uintptr_t)addr >= PIO_MAX ?\n+\t\t*(volatile uint8_t *)addr = val :\n+\t\toutb_p(val, (unsigned long)addr);\n+}\n+\n+static inline void iowrite16(uint16_t val, void *addr)\n+{\n+\t(uint64_t)(uintptr_t)addr >= PIO_MAX ?\n+\t\t*(volatile uint16_t *)addr = val :\n+\t\toutw_p(val, (unsigned long)addr);\n+}\n+\n+static inline void iowrite32(uint32_t val, void *addr)\n+{\n+\t(uint64_t)(uintptr_t)addr >= PIO_MAX ?\n+\t\t*(volatile uint32_t *)addr = val :\n+\t\toutl_p(val, (unsigned long)addr);\n+}\n+#else\n+static inline uint8_t ioread8(void *addr)\n+{\n+\treturn *(volatile uint8_t *)addr;\n+}\n+\n+static inline uint16_t ioread16(void *addr)\n+{\n+\treturn *(volatile uint16_t *)addr;\n+}\n+\n+static inline uint32_t ioread32(void *addr)\n+{\n+\treturn *(volatile uint32_t *)addr;\n+}\n+\n+static inline void iowrite8(uint8_t val, void *addr)\n+{\n+\t*(volatile uint8_t *)addr = val;\n+}\n+\n+static inline void iowrite16(uint16_t val, void *addr)\n+{\n+\t*(volatile uint16_t *)addr = val;\n+}\n+\n+static inline void iowrite32(uint32_t val, void *addr)\n+{\n+\t*(volatile uint32_t *)addr = val;\n+}\n+#endif\n+\n void\n pci_uio_ioport_read(struct rte_pci_ioport *p,\n \t\t void *data, size_t len, off_t offset)\n@@ -528,25 +622,13 @@\n \tfor (d = data; len > 0; d += size, reg += size, len -= size) {\n \t\tif (len >= 4) {\n \t\t\tsize = 4;\n-#if defined(RTE_ARCH_X86)\n-\t\t\t*(uint32_t *)d = inl(reg);\n-#else\n-\t\t\t*(uint32_t *)d = *(volatile uint32_t *)reg;\n-#endif\n+\t\t\t*(uint32_t *)d = ioread32((void *)reg);\n \t\t} else if (len >= 2) {\n \t\t\tsize = 2;\n-#if defined(RTE_ARCH_X86)\n-\t\t\t*(uint16_t *)d = inw(reg);\n-#else\n-\t\t\t*(uint16_t *)d = *(volatile uint16_t *)reg;\n-#endif\n+\t\t\t*(uint16_t *)d = ioread16((void *)reg);\n \t\t} else {\n \t\t\tsize = 1;\n-#if defined(RTE_ARCH_X86)\n-\t\t\t*d = inb(reg);\n-#else\n-\t\t\t*d = *(volatile uint8_t *)reg;\n-#endif\n+\t\t\t*d = ioread8((void *)reg);\n \t\t}\n \t}\n }\n@@ -562,25 +644,13 @@\n \tfor (s = data; len > 0; s += size, reg += size, len -= size) {\n \t\tif (len >= 4) {\n \t\t\tsize = 4;\n-#if defined(RTE_ARCH_X86)\n-\t\t\toutl_p(*(const uint32_t *)s, reg);\n-#else\n-\t\t\t*(volatile uint32_t *)reg = *(const uint32_t *)s;\n-#endif\n+\t\t\tiowrite32(*(const uint32_t *)s, (void *)reg);\n \t\t} else if (len >= 2) {\n \t\t\tsize = 2;\n-#if defined(RTE_ARCH_X86)\n-\t\t\toutw_p(*(const uint16_t *)s, reg);\n-#else\n-\t\t\t*(volatile uint16_t *)reg = *(const uint16_t *)s;\n-#endif\n+\t\t\tiowrite16(*(const uint16_t *)s, (void *)reg);\n \t\t} else {\n \t\t\tsize = 1;\n-#if defined(RTE_ARCH_X86)\n-\t\t\toutb_p(*s, reg);\n-#else\n-\t\t\t*(volatile uint8_t *)reg = *s;\n-#endif\n+\t\t\tiowrite8(*s, (void *)reg);\n \t\t}\n \t}\n }\n", "prefixes": [ "v9", "2/2" ] }