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GET /api/patches/95255/?format=api
{ "id": 95255, "url": "http://patchwork.dpdk.org/api/patches/95255/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210705040942.1524345-2-psatheesh@marvell.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210705040942.1524345-2-psatheesh@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210705040942.1524345-2-psatheesh@marvell.com", "date": "2021-07-05T04:09:42", "name": "[2/2] net/cnxk: add support for rte flow item raw", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "04e2ffb1d3073a5c8fbc67aaa60f6a594376ce03", "submitter": { "id": 1663, "url": "http://patchwork.dpdk.org/api/people/1663/?format=api", "name": "Satheesh Paul Antonysamy", "email": "psatheesh@marvell.com" }, "delegate": { "id": 310, "url": "http://patchwork.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210705040942.1524345-2-psatheesh@marvell.com/mbox/", "series": [ { "id": 17614, "url": "http://patchwork.dpdk.org/api/series/17614/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17614", "date": "2021-07-05T04:09:41", "name": "[1/2] common/cnxk: add support for rte flow item raw", "version": 1, "mbox": "http://patchwork.dpdk.org/series/17614/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/95255/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/95255/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 5DC41A0A0F;\n\tMon, 5 Jul 2021 06:10:01 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id BF9E641140;\n\tMon, 5 Jul 2021 06:09:59 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 311EE4113F\n for <dev@dpdk.org>; Mon, 5 Jul 2021 06:09:58 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.0.43/8.16.0.43) with SMTP id\n 16541JjL026578 for <dev@dpdk.org>; Sun, 4 Jul 2021 21:09:57 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 39kt2m841x-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Sun, 04 Jul 2021 21:09:57 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Sun, 4 Jul 2021 21:09:55 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Sun, 4 Jul 2021 21:09:55 -0700", "from localhost.localdomain (unknown [10.28.34.33])\n by maili.marvell.com (Postfix) with ESMTP id 2EC9B5B6921;\n Sun, 4 Jul 2021 21:09:52 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=HAbc9TmkFmvvh559eTgiYwKC4x0jtnDhX50S0qfwxSs=;\n b=TxY5vcckO4578bQe5qvXJHgRGslhih1c9iPRERy8LOvpieCu7Vjf8eWFapxlLNjxkqlA\n 6TD7ATyT4MMrXbxbKZhwyx4963MDrwYW/NR2Q11N2yex5xwKi6C2aYsRGX0mCHw3tr/d\n iW6pmIedG8NJgor122HxOt+/dbJTdzXzawHX0inbjUujVFBJoiQQLtr7SCCPaRX6lOWV\n 5I8CxF4OoD5W0GLYe2IBkrF+yoyl/iicuOudq48kGD7Sx+0xvScJapoldm3k65huVSWc\n CjzA6YHFGWXlaSSlqfFRV0qSm8WSwbbScpWz1ikOx08h1M/1g0XT3gTutm2vsWm48NKY yw==", "From": "<psatheesh@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<dev@dpdk.org>, Satheesh Paul <psatheesh@marvell.com>", "Date": "Mon, 5 Jul 2021 09:39:42 +0530", "Message-ID": "<20210705040942.1524345-2-psatheesh@marvell.com>", "X-Mailer": "git-send-email 2.25.4", "In-Reply-To": "<20210705040942.1524345-1-psatheesh@marvell.com>", "References": "<20210705040942.1524345-1-psatheesh@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "8G-MlvE5KkLbdcsiY9L5vqZs7F7yDJFB", "X-Proofpoint-GUID": "8G-MlvE5KkLbdcsiY9L5vqZs7F7yDJFB", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.391, 18.0.790\n definitions=2021-07-05_03:2021-07-02,\n 2021-07-05 signatures=0", "Subject": "[dpdk-dev] [PATCH 2/2] net/cnxk: add support for rte flow item raw", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Satheesh Paul <psatheesh@marvell.com>\n\nAdd support for rte_flow_item_raw to parse custom L2 and L3 protocols.\n\nSigned-off-by: Satheesh Paul <psatheesh@marvell.com>\nReviewed-by: Kiran Kumar Kokkilagadda <kirankumark@marvell.com>\n---\n doc/guides/nics/cnxk.rst | 169 +++++++++++++++++++++++--\n drivers/net/cnxk/cnxk_ethdev_devargs.c | 7 +\n drivers/net/cnxk/cnxk_rte_flow.c | 12 +-\n 3 files changed, 172 insertions(+), 16 deletions(-)", "diff": "diff --git a/doc/guides/nics/cnxk.rst b/doc/guides/nics/cnxk.rst\nindex cb2a51e1d..a7b59a48e 100644\n--- a/doc/guides/nics/cnxk.rst\n+++ b/doc/guides/nics/cnxk.rst\n@@ -104,7 +104,7 @@ Runtime Config Options\n \n - ``Rx&Tx scalar mode enable`` (default ``0``)\n \n- PMD supports both scalar and vector mode, it may be selected at runtime\n+ Ethdev supports both scalar and vector mode, it may be selected at runtime\n using ``scalar_enable`` ``devargs`` parameter.\n \n - ``RSS reta size`` (default ``64``)\n@@ -151,7 +151,7 @@ Runtime Config Options\n \n -a 0002:02:00.0,max_sqb_count=64\n \n- With the above configuration, each send queue's descriptor buffer count is\n+ With the above configuration, each send queue's decscriptor buffer count is\n limited to a maximum of 64 buffers.\n \n - ``Switch header enable`` (default ``none``)\n@@ -165,7 +165,7 @@ Runtime Config Options\n \n With the above configuration, higig2 will be enabled on that port and the\n traffic on this port should be higig2 traffic only. Supported switch header\n- types are \"higig2\", \"dsa\", \"chlen90b\" and \"chlen24b\".\n+ types are \"chlen24b\", \"chlen90b\", \"dsa\", \"exdsa\", \"higig2\" and \"vlan_exdsa\".\n \n - ``RSS tag as XOR`` (default ``0``)\n \n@@ -186,6 +186,7 @@ Runtime Config Options\n -a 0002:02:00.0,tag_as_xor=1\n \n \n+\n .. note::\n \n Above devarg parameters are configurable per device, user needs to pass the\n@@ -196,7 +197,7 @@ Limitations\n -----------\n \n ``mempool_cnxk`` external mempool handler dependency\n-~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n \n The OCTEON CN9K/CN10K SoC family NIC has inbuilt HW assisted external mempool manager.\n ``net_cnxk`` pmd only works with ``mempool_cnxk`` mempool handler\n@@ -209,12 +210,6 @@ CRC stripping\n The OCTEON CN9K/CN10K SoC family NICs strip the CRC for every packet being received by\n the host interface irrespective of the offload configuration.\n \n-RTE flow GRE support\n-~~~~~~~~~~~~~~~~~~~~\n-\n-- ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing\n- bits in the GRE header are equal to 0.\n-\n Debugging Options\n -----------------\n \n@@ -229,3 +224,157 @@ Debugging Options\n +---+------------+-------------------------------------------------------+\n | 2 | NPC | --log-level='pmd\\.net.cnxk\\.flow,8' |\n +---+------------+-------------------------------------------------------+\n+\n+RTE Flow Support\n+----------------\n+\n+The OCTEON CN9K/CN10K SoC family NIC has support for the following patterns and\n+actions.\n+\n+Patterns:\n+\n+.. _table_cnxk_supported_flow_item_types:\n+\n+.. table:: Item types\n+\n+ +----+--------------------------------+\n+ | # | Pattern Type |\n+ +====+================================+\n+ | 1 | RTE_FLOW_ITEM_TYPE_ETH |\n+ +----+--------------------------------+\n+ | 2 | RTE_FLOW_ITEM_TYPE_VLAN |\n+ +----+--------------------------------+\n+ | 3 | RTE_FLOW_ITEM_TYPE_E_TAG |\n+ +----+--------------------------------+\n+ | 4 | RTE_FLOW_ITEM_TYPE_IPV4 |\n+ +----+--------------------------------+\n+ | 5 | RTE_FLOW_ITEM_TYPE_IPV6 |\n+ +----+--------------------------------+\n+ | 6 | RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4|\n+ +----+--------------------------------+\n+ | 7 | RTE_FLOW_ITEM_TYPE_MPLS |\n+ +----+--------------------------------+\n+ | 8 | RTE_FLOW_ITEM_TYPE_ICMP |\n+ +----+--------------------------------+\n+ | 9 | RTE_FLOW_ITEM_TYPE_UDP |\n+ +----+--------------------------------+\n+ | 10 | RTE_FLOW_ITEM_TYPE_TCP |\n+ +----+--------------------------------+\n+ | 11 | RTE_FLOW_ITEM_TYPE_SCTP |\n+ +----+--------------------------------+\n+ | 12 | RTE_FLOW_ITEM_TYPE_ESP |\n+ +----+--------------------------------+\n+ | 13 | RTE_FLOW_ITEM_TYPE_GRE |\n+ +----+--------------------------------+\n+ | 14 | RTE_FLOW_ITEM_TYPE_NVGRE |\n+ +----+--------------------------------+\n+ | 15 | RTE_FLOW_ITEM_TYPE_VXLAN |\n+ +----+--------------------------------+\n+ | 16 | RTE_FLOW_ITEM_TYPE_GTPC |\n+ +----+--------------------------------+\n+ | 17 | RTE_FLOW_ITEM_TYPE_GTPU |\n+ +----+--------------------------------+\n+ | 18 | RTE_FLOW_ITEM_TYPE_GENEVE |\n+ +----+--------------------------------+\n+ | 19 | RTE_FLOW_ITEM_TYPE_VXLAN_GPE |\n+ +----+--------------------------------+\n+ | 20 | RTE_FLOW_ITEM_TYPE_IPV6_EXT |\n+ +----+--------------------------------+\n+ | 21 | RTE_FLOW_ITEM_TYPE_VOID |\n+ +----+--------------------------------+\n+ | 22 | RTE_FLOW_ITEM_TYPE_ANY |\n+ +----+--------------------------------+\n+ | 23 | RTE_FLOW_ITEM_TYPE_GRE_KEY |\n+ +----+--------------------------------+\n+ | 24 | RTE_FLOW_ITEM_TYPE_HIGIG2 |\n+ +----+--------------------------------+\n+ | 25 | RTE_FLOW_ITEM_TYPE_RAW |\n+ +----+--------------------------------+\n+\n+.. note::\n+\n+ ``RTE_FLOW_ITEM_TYPE_GRE_KEY`` works only when checksum and routing\n+ bits in the GRE header are equal to 0.\n+\n+Actions:\n+\n+.. _table_cnxk_supported_ingress_action_types:\n+\n+.. table:: Ingress action types\n+\n+ +----+-----------------------------------------+\n+ | # | Action Type |\n+ +====+=========================================+\n+ | 1 | RTE_FLOW_ACTION_TYPE_VOID |\n+ +----+-----------------------------------------+\n+ | 2 | RTE_FLOW_ACTION_TYPE_MARK |\n+ +----+-----------------------------------------+\n+ | 3 | RTE_FLOW_ACTION_TYPE_FLAG |\n+ +----+-----------------------------------------+\n+ | 4 | RTE_FLOW_ACTION_TYPE_COUNT |\n+ +----+-----------------------------------------+\n+ | 5 | RTE_FLOW_ACTION_TYPE_DROP |\n+ +----+-----------------------------------------+\n+ | 6 | RTE_FLOW_ACTION_TYPE_QUEUE |\n+ +----+-----------------------------------------+\n+ | 7 | RTE_FLOW_ACTION_TYPE_RSS |\n+ +----+-----------------------------------------+\n+ | 8 | RTE_FLOW_ACTION_TYPE_PF |\n+ +----+-----------------------------------------+\n+ | 9 | RTE_FLOW_ACTION_TYPE_VF |\n+ +----+-----------------------------------------+\n+ | 10 | RTE_FLOW_ACTION_TYPE_OF_POP_VLAN |\n+ +----+-----------------------------------------+\n+\n+.. _table_cnxk_supported_egress_action_types:\n+\n+.. table:: Egress action types\n+\n+ +----+-----------------------------------------+\n+ | # | Action Type |\n+ +====+=========================================+\n+ | 1 | RTE_FLOW_ACTION_TYPE_COUNT |\n+ +----+-----------------------------------------+\n+ | 2 | RTE_FLOW_ACTION_TYPE_DROP |\n+ +----+-----------------------------------------+\n+ | 3 | RTE_FLOW_ACTION_TYPE_OF_PUSH_VLAN |\n+ +----+-----------------------------------------+\n+ | 4 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_VID |\n+ +----+-----------------------------------------+\n+ | 5 | RTE_FLOW_ACTION_TYPE_OF_SET_VLAN_PCP |\n+ +----+-----------------------------------------+\n+\n+Custom protocols supported in RTE Flow\n+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n+\n+The ``RTE_FLOW_ITEM_TYPE_RAW`` can be used to parse the below custom protocols.\n+\n+* ``vlan_exdsa`` and ``exdsa`` can be parsed at L2 level.\n+* ``NGIO`` can be parsed at L3 level.\n+\n+For ``vlan_exdsa`` and ``exdsa``, the port has to be configured with the\n+respective switch header.\n+\n+For example::\n+\n+ -a 0002:02:00.0,switch_header=\"vlan_exdsa\"\n+\n+The below fields of ``struct rte_flow_item_raw`` shall be used to specify the\n+pattern.\n+\n+- ``relative`` Selects the layer at which parsing is done.\n+\n+ - 0 for ``exdsa`` and ``vlan_exdsa``.\n+\n+ - 1 for ``NGIO``.\n+\n+- ``offset`` The offset in the header where the pattern should be matched.\n+- ``length`` Length of the pattern.\n+- ``pattern`` Pattern as a byte string.\n+\n+Example usage in testpmd::\n+\n+ ./dpdk-testpmd -c 3 -w 0002:02:00.0,switch_header=exdsa -- -i \\\n+ --rx-offloads=0x00080000 --rxq 8 --txq 8\n+ testpmd> flow create 0 ingress pattern eth / raw relative is 0 pattern \\\n+ spec ab pattern mask ab offset is 4 / end actions queue index 1 / end\ndiff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c\nindex c76b6281c..36b437a18 100644\n--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c\n+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c\n@@ -99,6 +99,13 @@ parse_switch_header_type(const char *key, const char *value, void *extra_args)\n \n \tif (strcmp(value, \"chlen90b\") == 0)\n \t\t*(uint16_t *)extra_args = ROC_PRIV_FLAGS_LEN_90B;\n+\n+\tif (strcmp(value, \"exdsa\") == 0)\n+\t\t*(uint16_t *)extra_args = ROC_PRIV_FLAGS_EXDSA;\n+\n+\tif (strcmp(value, \"vlan_exdsa\") == 0)\n+\t\t*(uint16_t *)extra_args = ROC_PRIV_FLAGS_VLAN_EXDSA;\n+\n \treturn 0;\n }\n \ndiff --git a/drivers/net/cnxk/cnxk_rte_flow.c b/drivers/net/cnxk/cnxk_rte_flow.c\nindex 213125b56..32c1b5dee 100644\n--- a/drivers/net/cnxk/cnxk_rte_flow.c\n+++ b/drivers/net/cnxk/cnxk_rte_flow.c\n@@ -15,8 +15,8 @@ const struct cnxk_rte_flow_term_info term[] = {\n \t[RTE_FLOW_ITEM_TYPE_IPV6] = {ROC_NPC_ITEM_TYPE_IPV6,\n \t\t\t\t sizeof(struct rte_flow_item_ipv6)},\n \t[RTE_FLOW_ITEM_TYPE_ARP_ETH_IPV4] = {\n-\t\tROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,\n-\t\tsizeof(struct rte_flow_item_arp_eth_ipv4)},\n+\t\t\tROC_NPC_ITEM_TYPE_ARP_ETH_IPV4,\n+\t\t\tsizeof(struct rte_flow_item_arp_eth_ipv4)},\n \t[RTE_FLOW_ITEM_TYPE_MPLS] = {ROC_NPC_ITEM_TYPE_MPLS,\n \t\t\t\t sizeof(struct rte_flow_item_mpls)},\n \t[RTE_FLOW_ITEM_TYPE_ICMP] = {ROC_NPC_ITEM_TYPE_ICMP,\n@@ -50,10 +50,10 @@ const struct cnxk_rte_flow_term_info term[] = {\n \t[RTE_FLOW_ITEM_TYPE_ANY] = {ROC_NPC_ITEM_TYPE_ANY, 0},\n \t[RTE_FLOW_ITEM_TYPE_GRE_KEY] = {ROC_NPC_ITEM_TYPE_GRE_KEY,\n \t\t\t\t\tsizeof(uint32_t)},\n-\t[RTE_FLOW_ITEM_TYPE_HIGIG2] = {\n-\t\tROC_NPC_ITEM_TYPE_HIGIG2,\n-\t\tsizeof(struct rte_flow_item_higig2_hdr)}\n-};\n+\t[RTE_FLOW_ITEM_TYPE_HIGIG2] = {ROC_NPC_ITEM_TYPE_HIGIG2,\n+\t\t\t\t sizeof(struct rte_flow_item_higig2_hdr)},\n+\t[RTE_FLOW_ITEM_TYPE_RAW] = {ROC_NPC_ITEM_TYPE_RAW,\n+\t\t\t\t sizeof(struct rte_flow_item_raw)}};\n \n static int\n npc_rss_action_validate(struct rte_eth_dev *eth_dev,\n", "prefixes": [ "2/2" ] }