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{
    "id": 95353,
    "url": "http://patchwork.dpdk.org/api/patches/95353/?format=api",
    "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210706095545.10776-9-jiawenwu@trustnetic.com/",
    "project": {
        "id": 1,
        "url": "http://patchwork.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210706095545.10776-9-jiawenwu@trustnetic.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210706095545.10776-9-jiawenwu@trustnetic.com",
    "date": "2021-07-06T09:55:34",
    "name": "[v7,08/19] net/ngbe: identify PHY and reset PHY",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": true,
    "hash": "5b45404e405dc8c8b8318423cf49ca77f1aa60cf",
    "submitter": {
        "id": 1932,
        "url": "http://patchwork.dpdk.org/api/people/1932/?format=api",
        "name": "Jiawen Wu",
        "email": "jiawenwu@trustnetic.com"
    },
    "delegate": {
        "id": 3961,
        "url": "http://patchwork.dpdk.org/api/users/3961/?format=api",
        "username": "arybchenko",
        "first_name": "Andrew",
        "last_name": "Rybchenko",
        "email": "andrew.rybchenko@oktetlabs.ru"
    },
    "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210706095545.10776-9-jiawenwu@trustnetic.com/mbox/",
    "series": [
        {
            "id": 17659,
            "url": "http://patchwork.dpdk.org/api/series/17659/?format=api",
            "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17659",
            "date": "2021-07-06T09:55:28",
            "name": "net: ngbe PMD",
            "version": 7,
            "mbox": "http://patchwork.dpdk.org/series/17659/mbox/"
        }
    ],
    "comments": "http://patchwork.dpdk.org/api/patches/95353/comments/",
    "check": "warning",
    "checks": "http://patchwork.dpdk.org/api/patches/95353/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<dev-bounces@dpdk.org>",
        "X-Original-To": "patchwork@inbox.dpdk.org",
        "Delivered-To": "patchwork@inbox.dpdk.org",
        "Received": [
            "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1125AA0C47;\n\tTue,  6 Jul 2021 11:57:31 +0200 (CEST)",
            "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id C48C7412A9;\n\tTue,  6 Jul 2021 11:56:13 +0200 (CEST)",
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            "from jiawenwu.trustnetic.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Tue, 06 Jul 2021 17:56:05 +0800 (CST)"
        ],
        "X-QQ-mid": "bizesmtp51t1625565366tjciedr7",
        "X-QQ-SSF": "01400000002000D0E000B00A0000000",
        "X-QQ-FEAT": "PAtBXkQ2bGCVtS1NlorGsfnhbBIpWDjFnQBda2mz6E77Kqaw1NlEBNTwXeN5y\n zNowGW5WER1fVJZYIZB9YlLxmaNyCe5rp1N6OYHlrhotDuzYmfJM7+wbozQcskvG1nFEOUU\n EkcE1eotv9T0zqNWnjcYi02tkIIZSvkuRkJGuYBNYlPPlUQmXipIrAE2aQ60m4uCvQAHaw5\n NiBQxTsIgAmh/4dVqhbOwjzZfyOo7DUdahMJ1Yet25PXGz+GGft8QTLKmshLvOp/KqWXEPl\n scdzICqgL53YcdhNurjEFmrCnR8feClK9sEiNZPHY3ac7m7lg9DLHjccMspFRZfOOlz0Ntf\n pVbv6ya4ImEGyvqbF/5ftv4jqcqgw==",
        "X-QQ-GoodBg": "2",
        "From": "Jiawen Wu <jiawenwu@trustnetic.com>",
        "To": "dev@dpdk.org",
        "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>",
        "Date": "Tue,  6 Jul 2021 17:55:34 +0800",
        "Message-Id": "<20210706095545.10776-9-jiawenwu@trustnetic.com>",
        "X-Mailer": "git-send-email 2.21.0.windows.1",
        "In-Reply-To": "<20210706095545.10776-1-jiawenwu@trustnetic.com>",
        "References": "<20210706095545.10776-1-jiawenwu@trustnetic.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
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        "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign5",
        "X-QQ-Bgrelay": "1",
        "Subject": "[dpdk-dev] [PATCH v7 08/19] net/ngbe: identify PHY and reset PHY",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
        "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>",
        "List-Archive": "<http://mails.dpdk.org/archives/dev/>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Identify PHY to get the PHY type, and perform a PHY reset.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n drivers/net/ngbe/base/meson.build    |   4 +\n drivers/net/ngbe/base/ngbe_dummy.h   |  40 +++\n drivers/net/ngbe/base/ngbe_hw.c      |  38 +++\n drivers/net/ngbe/base/ngbe_hw.h      |   2 +\n drivers/net/ngbe/base/ngbe_phy.c     | 426 +++++++++++++++++++++++++++\n drivers/net/ngbe/base/ngbe_phy.h     |  60 ++++\n drivers/net/ngbe/base/ngbe_phy_mvl.c |  89 ++++++\n drivers/net/ngbe/base/ngbe_phy_mvl.h |  92 ++++++\n drivers/net/ngbe/base/ngbe_phy_rtl.c |  65 ++++\n drivers/net/ngbe/base/ngbe_phy_rtl.h |  83 ++++++\n drivers/net/ngbe/base/ngbe_phy_yt.c  | 112 +++++++\n drivers/net/ngbe/base/ngbe_phy_yt.h  |  67 +++++\n drivers/net/ngbe/base/ngbe_type.h    |  17 ++\n 13 files changed, 1095 insertions(+)\n create mode 100644 drivers/net/ngbe/base/ngbe_phy.c\n create mode 100644 drivers/net/ngbe/base/ngbe_phy.h\n create mode 100644 drivers/net/ngbe/base/ngbe_phy_mvl.c\n create mode 100644 drivers/net/ngbe/base/ngbe_phy_mvl.h\n create mode 100644 drivers/net/ngbe/base/ngbe_phy_rtl.c\n create mode 100644 drivers/net/ngbe/base/ngbe_phy_rtl.h\n create mode 100644 drivers/net/ngbe/base/ngbe_phy_yt.c\n create mode 100644 drivers/net/ngbe/base/ngbe_phy_yt.h",
    "diff": "diff --git a/drivers/net/ngbe/base/meson.build b/drivers/net/ngbe/base/meson.build\nindex d206cc6d74..9420786245 100644\n--- a/drivers/net/ngbe/base/meson.build\n+++ b/drivers/net/ngbe/base/meson.build\n@@ -5,6 +5,10 @@ sources = [\n \t'ngbe_eeprom.c',\n \t'ngbe_hw.c',\n \t'ngbe_mng.c',\n+\t'ngbe_phy.c',\n+\t'ngbe_phy_rtl.c',\n+\t'ngbe_phy_mvl.c',\n+\t'ngbe_phy_yt.c',\n ]\n \n error_cflags = []\ndiff --git a/drivers/net/ngbe/base/ngbe_dummy.h b/drivers/net/ngbe/base/ngbe_dummy.h\nindex 3445e7475a..51ae0acd2c 100644\n--- a/drivers/net/ngbe/base/ngbe_dummy.h\n+++ b/drivers/net/ngbe/base/ngbe_dummy.h\n@@ -64,6 +64,39 @@ static inline s32 ngbe_mac_init_thermal_ssth_dummy(struct ngbe_hw *TUP0)\n {\n \treturn NGBE_ERR_OPS_DUMMY;\n }\n+static inline s32 ngbe_mac_check_overtemp_dummy(struct ngbe_hw *TUP0)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n+/* struct ngbe_phy_operations */\n+static inline s32 ngbe_phy_identify_dummy(struct ngbe_hw *TUP0)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n+static inline s32 ngbe_phy_reset_hw_dummy(struct ngbe_hw *TUP0)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n+static inline s32 ngbe_phy_read_reg_dummy(struct ngbe_hw *TUP0, u32 TUP1,\n+\t\t\t\t\tu32 TUP2, u16 *TUP3)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n+static inline s32 ngbe_phy_write_reg_dummy(struct ngbe_hw *TUP0, u32 TUP1,\n+\t\t\t\t\tu32 TUP2, u16 TUP3)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n+static inline s32 ngbe_phy_read_reg_unlocked_dummy(struct ngbe_hw *TUP0,\n+\t\t\t\t\tu32 TUP1, u32 TUP2, u16 *TUP3)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n+static inline s32 ngbe_phy_write_reg_unlocked_dummy(struct ngbe_hw *TUP0,\n+\t\t\t\t\tu32 TUP1, u32 TUP2, u16 TUP3)\n+{\n+\treturn NGBE_ERR_OPS_DUMMY;\n+}\n static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw)\n {\n \thw->bus.set_lan_id = ngbe_bus_set_lan_id_dummy;\n@@ -75,6 +108,13 @@ static inline void ngbe_init_ops_dummy(struct ngbe_hw *hw)\n \thw->mac.acquire_swfw_sync = ngbe_mac_acquire_swfw_sync_dummy;\n \thw->mac.release_swfw_sync = ngbe_mac_release_swfw_sync_dummy;\n \thw->mac.init_thermal_sensor_thresh = ngbe_mac_init_thermal_ssth_dummy;\n+\thw->mac.check_overtemp = ngbe_mac_check_overtemp_dummy;\n+\thw->phy.identify = ngbe_phy_identify_dummy;\n+\thw->phy.reset_hw = ngbe_phy_reset_hw_dummy;\n+\thw->phy.read_reg = ngbe_phy_read_reg_dummy;\n+\thw->phy.write_reg = ngbe_phy_write_reg_dummy;\n+\thw->phy.read_reg_unlocked = ngbe_phy_read_reg_unlocked_dummy;\n+\thw->phy.write_reg_unlocked = ngbe_phy_write_reg_unlocked_dummy;\n }\n \n #endif /* _NGBE_TYPE_DUMMY_H_ */\ndiff --git a/drivers/net/ngbe/base/ngbe_hw.c b/drivers/net/ngbe/base/ngbe_hw.c\nindex 446f4b52b5..662fb17532 100644\n--- a/drivers/net/ngbe/base/ngbe_hw.c\n+++ b/drivers/net/ngbe/base/ngbe_hw.c\n@@ -4,6 +4,7 @@\n  */\n \n #include \"ngbe_type.h\"\n+#include \"ngbe_phy.h\"\n #include \"ngbe_eeprom.h\"\n #include \"ngbe_mng.h\"\n #include \"ngbe_hw.h\"\n@@ -124,6 +125,15 @@ s32 ngbe_reset_hw_em(struct ngbe_hw *hw)\n \tif (status != 0)\n \t\treturn status;\n \n+\t/* Identify PHY and related function pointers */\n+\tstatus = ngbe_init_phy(hw);\n+\tif (status)\n+\t\treturn status;\n+\n+\t/* Reset PHY */\n+\tif (!hw->phy.reset_disable)\n+\t\thw->phy.reset_hw(hw);\n+\n \twr32(hw, NGBE_RST, NGBE_RST_LAN(hw->bus.lan_id));\n \tngbe_flush(hw);\n \tmsec_delay(50);\n@@ -307,6 +317,24 @@ s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw)\n \treturn 0;\n }\n \n+s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw)\n+{\n+\ts32 status = 0;\n+\tu32 ts_state;\n+\n+\tDEBUGFUNC(\"ngbe_mac_check_overtemp\");\n+\n+\t/* Check that the LASI temp alarm status was triggered */\n+\tts_state = rd32(hw, NGBE_TSALM);\n+\n+\tif (ts_state & NGBE_TSALM_HI)\n+\t\tstatus = NGBE_ERR_UNDERTEMP;\n+\telse if (ts_state & NGBE_TSALM_LO)\n+\t\tstatus = NGBE_ERR_OVERTEMP;\n+\n+\treturn status;\n+}\n+\n void ngbe_disable_rx(struct ngbe_hw *hw)\n {\n \tu32 pfdtxgswc;\n@@ -434,6 +462,7 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw)\n {\n \tstruct ngbe_bus_info *bus = &hw->bus;\n \tstruct ngbe_mac_info *mac = &hw->mac;\n+\tstruct ngbe_phy_info *phy = &hw->phy;\n \tstruct ngbe_rom_info *rom = &hw->rom;\n \n \tDEBUGFUNC(\"ngbe_init_ops_pf\");\n@@ -441,6 +470,14 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw)\n \t/* BUS */\n \tbus->set_lan_id = ngbe_set_lan_id_multi_port;\n \n+\t/* PHY */\n+\tphy->identify = ngbe_identify_phy;\n+\tphy->read_reg = ngbe_read_phy_reg;\n+\tphy->write_reg = ngbe_write_phy_reg;\n+\tphy->read_reg_unlocked = ngbe_read_phy_reg_mdi;\n+\tphy->write_reg_unlocked = ngbe_write_phy_reg_mdi;\n+\tphy->reset_hw = ngbe_reset_phy;\n+\n \t/* MAC */\n \tmac->init_hw = ngbe_init_hw;\n \tmac->reset_hw = ngbe_reset_hw_em;\n@@ -450,6 +487,7 @@ s32 ngbe_init_ops_pf(struct ngbe_hw *hw)\n \n \t/* Manageability interface */\n \tmac->init_thermal_sensor_thresh = ngbe_init_thermal_sensor_thresh;\n+\tmac->check_overtemp = ngbe_mac_check_overtemp;\n \n \t/* EEPROM */\n \trom->init_params = ngbe_init_eeprom_params;\ndiff --git a/drivers/net/ngbe/base/ngbe_hw.h b/drivers/net/ngbe/base/ngbe_hw.h\nindex 207d4b269d..2205156eb9 100644\n--- a/drivers/net/ngbe/base/ngbe_hw.h\n+++ b/drivers/net/ngbe/base/ngbe_hw.h\n@@ -21,10 +21,12 @@ s32 ngbe_acquire_swfw_sync(struct ngbe_hw *hw, u32 mask);\n void ngbe_release_swfw_sync(struct ngbe_hw *hw, u32 mask);\n \n s32 ngbe_init_thermal_sensor_thresh(struct ngbe_hw *hw);\n+s32 ngbe_mac_check_overtemp(struct ngbe_hw *hw);\n void ngbe_disable_rx(struct ngbe_hw *hw);\n s32 ngbe_init_shared_code(struct ngbe_hw *hw);\n s32 ngbe_set_mac_type(struct ngbe_hw *hw);\n s32 ngbe_init_ops_pf(struct ngbe_hw *hw);\n+s32 ngbe_init_phy(struct ngbe_hw *hw);\n void ngbe_map_device_id(struct ngbe_hw *hw);\n \n #endif /* _NGBE_HW_H_ */\ndiff --git a/drivers/net/ngbe/base/ngbe_phy.c b/drivers/net/ngbe/base/ngbe_phy.c\nnew file mode 100644\nindex 0000000000..61bb953b6a\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy.c\n@@ -0,0 +1,426 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ * Copyright(c) 2010-2017 Intel Corporation\n+ */\n+\n+#include \"ngbe_hw.h\"\n+#include \"ngbe_phy.h\"\n+\n+s32 ngbe_mdi_map_register(mdi_reg_t *reg, mdi_reg_22_t *reg22)\n+{\n+\tbool match = 1;\n+\tswitch (reg->device_type) {\n+\tcase NGBE_MD_DEV_PMA_PMD:\n+\t\tswitch (reg->addr) {\n+\t\tcase NGBE_MD_PHY_ID_HIGH:\n+\t\tcase NGBE_MD_PHY_ID_LOW:\n+\t\t\treg22->page = 0;\n+\t\t\treg22->addr = reg->addr;\n+\t\t\treg22->device_type = 0;\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tmatch = 0;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\tmatch = 0;\n+\t\tbreak;\n+\t}\n+\n+\tif (!match) {\n+\t\treg22->page = reg->device_type;\n+\t\treg22->device_type = reg->device_type;\n+\t\treg22->addr = reg->addr;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ * ngbe_probe_phy - Identify a single address for a PHY\n+ * @hw: pointer to hardware structure\n+ * @phy_addr: PHY address to probe\n+ *\n+ * Returns true if PHY found\n+ */\n+static bool ngbe_probe_phy(struct ngbe_hw *hw, u16 phy_addr)\n+{\n+\tif (!ngbe_validate_phy_addr(hw, phy_addr)) {\n+\t\tDEBUGOUT(\"Unable to validate PHY address 0x%04X\\n\",\n+\t\t\tphy_addr);\n+\t\treturn false;\n+\t}\n+\n+\tif (ngbe_get_phy_id(hw))\n+\t\treturn false;\n+\n+\thw->phy.type = ngbe_get_phy_type_from_id(hw);\n+\tif (hw->phy.type == ngbe_phy_unknown)\n+\t\treturn false;\n+\n+\treturn true;\n+}\n+\n+/**\n+ *  ngbe_identify_phy - Get physical layer module\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Determines the physical layer module found on the current adapter.\n+ **/\n+s32 ngbe_identify_phy(struct ngbe_hw *hw)\n+{\n+\ts32 err = NGBE_ERR_PHY_ADDR_INVALID;\n+\tu16 phy_addr;\n+\n+\tDEBUGFUNC(\"ngbe_identify_phy\");\n+\n+\tif (hw->phy.type != ngbe_phy_unknown)\n+\t\treturn 0;\n+\n+\t/* select clause22 */\n+\twr32(hw, NGBE_MDIOMODE, NGBE_MDIOMODE_MASK);\n+\n+\tfor (phy_addr = 0; phy_addr < NGBE_MAX_PHY_ADDR; phy_addr++) {\n+\t\tif (ngbe_probe_phy(hw, phy_addr)) {\n+\t\t\terr = 0;\n+\t\t\tbreak;\n+\t\t}\n+\t}\n+\n+\treturn err;\n+}\n+\n+/**\n+ * ngbe_check_reset_blocked - check status of MNG FW veto bit\n+ * @hw: pointer to the hardware structure\n+ *\n+ * This function checks the STAT.MNGVETO bit to see if there are\n+ * any constraints on link from manageability.  For MAC's that don't\n+ * have this bit just return faluse since the link can not be blocked\n+ * via this method.\n+ **/\n+s32 ngbe_check_reset_blocked(struct ngbe_hw *hw)\n+{\n+\tu32 mmngc;\n+\n+\tDEBUGFUNC(\"ngbe_check_reset_blocked\");\n+\n+\tmmngc = rd32(hw, NGBE_STAT);\n+\tif (mmngc & NGBE_STAT_MNGVETO) {\n+\t\tDEBUGOUT(\"MNG_VETO bit detected.\\n\");\n+\t\treturn true;\n+\t}\n+\n+\treturn false;\n+}\n+\n+/**\n+ *  ngbe_validate_phy_addr - Determines phy address is valid\n+ *  @hw: pointer to hardware structure\n+ *  @phy_addr: PHY address\n+ *\n+ **/\n+bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr)\n+{\n+\tu16 phy_id = 0;\n+\tbool valid = false;\n+\n+\tDEBUGFUNC(\"ngbe_validate_phy_addr\");\n+\n+\tif (hw->sub_device_id == NGBE_SUB_DEV_ID_EM_YT8521S_SFP)\n+\t\treturn true;\n+\n+\thw->phy.addr = phy_addr;\n+\thw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH,\n+\t\t\t     NGBE_MD_DEV_PMA_PMD, &phy_id);\n+\n+\tif (phy_id != 0xFFFF && phy_id != 0x0)\n+\t\tvalid = true;\n+\n+\tDEBUGOUT(\"PHY ID HIGH is 0x%04X\\n\", phy_id);\n+\n+\treturn valid;\n+}\n+\n+/**\n+ *  ngbe_get_phy_id - Get the phy ID\n+ *  @hw: pointer to hardware structure\n+ *\n+ **/\n+s32 ngbe_get_phy_id(struct ngbe_hw *hw)\n+{\n+\tu32 err;\n+\tu16 phy_id_high = 0;\n+\tu16 phy_id_low = 0;\n+\n+\tDEBUGFUNC(\"ngbe_get_phy_id\");\n+\n+\terr = hw->phy.read_reg(hw, NGBE_MD_PHY_ID_HIGH,\n+\t\t\t\t      NGBE_MD_DEV_PMA_PMD,\n+\t\t\t\t      &phy_id_high);\n+\thw->phy.id = (u32)(phy_id_high << 16);\n+\n+\terr = hw->phy.read_reg(hw, NGBE_MD_PHY_ID_LOW,\n+\t\t\t\tNGBE_MD_DEV_PMA_PMD,\n+\t\t\t\t&phy_id_low);\n+\thw->phy.id |= (u32)(phy_id_low & NGBE_PHY_REVISION_MASK);\n+\thw->phy.revision = (u32)(phy_id_low & ~NGBE_PHY_REVISION_MASK);\n+\n+\tDEBUGOUT(\"PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\\n\",\n+\t\t  phy_id_high, phy_id_low);\n+\n+\treturn err;\n+}\n+\n+/**\n+ *  ngbe_get_phy_type_from_id - Get the phy type\n+ *  @phy_id: PHY ID information\n+ *\n+ **/\n+enum ngbe_phy_type ngbe_get_phy_type_from_id(struct ngbe_hw *hw)\n+{\n+\tenum ngbe_phy_type phy_type;\n+\n+\tDEBUGFUNC(\"ngbe_get_phy_type_from_id\");\n+\n+\tswitch (hw->phy.id) {\n+\tcase NGBE_PHYID_RTL:\n+\t\tphy_type = ngbe_phy_rtl;\n+\t\tbreak;\n+\tcase NGBE_PHYID_MVL:\n+\t\tif (hw->phy.media_type == ngbe_media_type_fiber)\n+\t\t\tphy_type = ngbe_phy_mvl_sfi;\n+\t\telse\n+\t\t\tphy_type = ngbe_phy_mvl;\n+\t\tbreak;\n+\tcase NGBE_PHYID_YT:\n+\t\tif (hw->phy.media_type == ngbe_media_type_fiber)\n+\t\t\tphy_type = ngbe_phy_yt8521s_sfi;\n+\t\telse\n+\t\t\tphy_type = ngbe_phy_yt8521s;\n+\t\tbreak;\n+\tdefault:\n+\t\tphy_type = ngbe_phy_unknown;\n+\t\tbreak;\n+\t}\n+\n+\treturn phy_type;\n+}\n+\n+/**\n+ *  ngbe_reset_phy - Performs a PHY reset\n+ *  @hw: pointer to hardware structure\n+ **/\n+s32 ngbe_reset_phy(struct ngbe_hw *hw)\n+{\n+\ts32 err = 0;\n+\n+\tDEBUGFUNC(\"ngbe_reset_phy\");\n+\n+\tif (hw->phy.type == ngbe_phy_unknown)\n+\t\terr = ngbe_identify_phy(hw);\n+\n+\tif (err != 0 || hw->phy.type == ngbe_phy_none)\n+\t\treturn err;\n+\n+\t/* Don't reset PHY if it's shut down due to overtemp. */\n+\tif (hw->mac.check_overtemp(hw) == NGBE_ERR_OVERTEMP)\n+\t\treturn err;\n+\n+\t/* Blocked by MNG FW so bail */\n+\tif (ngbe_check_reset_blocked(hw))\n+\t\treturn err;\n+\n+\tswitch (hw->phy.type) {\n+\tcase ngbe_phy_rtl:\n+\t\terr = ngbe_reset_phy_rtl(hw);\n+\t\tbreak;\n+\tcase ngbe_phy_mvl:\n+\tcase ngbe_phy_mvl_sfi:\n+\t\terr = ngbe_reset_phy_mvl(hw);\n+\t\tbreak;\n+\tcase ngbe_phy_yt8521s:\n+\tcase ngbe_phy_yt8521s_sfi:\n+\t\terr = ngbe_reset_phy_yt(hw);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\treturn err;\n+}\n+\n+/**\n+ *  ngbe_read_phy_mdi - Reads a value from a specified PHY register without\n+ *  the SWFW lock\n+ *  @hw: pointer to hardware structure\n+ *  @reg_addr: 32 bit address of PHY register to read\n+ *  @device_type: 5 bit device type\n+ *  @phy_data: Pointer to read data from PHY register\n+ **/\n+s32 ngbe_read_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\t   u16 *phy_data)\n+{\n+\tu32 command, data;\n+\n+\t/* Setup and write the address cycle command */\n+\tcommand = NGBE_MDIOSCA_REG(reg_addr) |\n+\t\t  NGBE_MDIOSCA_DEV(device_type) |\n+\t\t  NGBE_MDIOSCA_PORT(hw->phy.addr);\n+\twr32(hw, NGBE_MDIOSCA, command);\n+\n+\tcommand = NGBE_MDIOSCD_CMD_READ |\n+\t\t  NGBE_MDIOSCD_BUSY |\n+\t\t  NGBE_MDIOSCD_CLOCK(6);\n+\twr32(hw, NGBE_MDIOSCD, command);\n+\n+\t/*\n+\t * Check every 10 usec to see if the address cycle completed.\n+\t * The MDI Command bit will clear when the operation is\n+\t * complete\n+\t */\n+\tif (!po32m(hw, NGBE_MDIOSCD, NGBE_MDIOSCD_BUSY,\n+\t\t0, NULL, 100, 100)) {\n+\t\tDEBUGOUT(\"PHY address command did not complete\\n\");\n+\t\treturn NGBE_ERR_PHY;\n+\t}\n+\n+\tdata = rd32(hw, NGBE_MDIOSCD);\n+\t*phy_data = (u16)NGBE_MDIOSCD_DAT_R(data);\n+\n+\treturn 0;\n+}\n+\n+/**\n+ *  ngbe_read_phy_reg - Reads a value from a specified PHY register\n+ *  using the SWFW lock - this function is needed in most cases\n+ *  @hw: pointer to hardware structure\n+ *  @reg_addr: 32 bit address of PHY register to read\n+ *  @device_type: 5 bit device type\n+ *  @phy_data: Pointer to read data from PHY register\n+ **/\n+s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t       u32 device_type, u16 *phy_data)\n+{\n+\ts32 err;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\tDEBUGFUNC(\"ngbe_read_phy_reg\");\n+\n+\tif (hw->mac.acquire_swfw_sync(hw, gssr))\n+\t\treturn NGBE_ERR_SWFW_SYNC;\n+\n+\terr = hw->phy.read_reg_unlocked(hw, reg_addr, device_type,\n+\t\t\t\t\tphy_data);\n+\n+\thw->mac.release_swfw_sync(hw, gssr);\n+\n+\treturn err;\n+}\n+\n+/**\n+ *  ngbe_write_phy_reg_mdi - Writes a value to specified PHY register\n+ *  without SWFW lock\n+ *  @hw: pointer to hardware structure\n+ *  @reg_addr: 32 bit PHY register to write\n+ *  @device_type: 5 bit device type\n+ *  @phy_data: Data to write to the PHY register\n+ **/\n+s32 ngbe_write_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data)\n+{\n+\tu32 command;\n+\n+\t/* write command */\n+\tcommand = NGBE_MDIOSCA_REG(reg_addr) |\n+\t\t  NGBE_MDIOSCA_DEV(device_type) |\n+\t\t  NGBE_MDIOSCA_PORT(hw->phy.addr);\n+\twr32(hw, NGBE_MDIOSCA, command);\n+\n+\tcommand = NGBE_MDIOSCD_CMD_WRITE |\n+\t\t  NGBE_MDIOSCD_DAT(phy_data) |\n+\t\t  NGBE_MDIOSCD_BUSY |\n+\t\t  NGBE_MDIOSCD_CLOCK(6);\n+\twr32(hw, NGBE_MDIOSCD, command);\n+\n+\t/* wait for completion */\n+\tif (!po32m(hw, NGBE_MDIOSCD, NGBE_MDIOSCD_BUSY,\n+\t\t0, NULL, 100, 100)) {\n+\t\tTLOG_DEBUG(\"PHY write cmd didn't complete\\n\");\n+\t\treturn NGBE_ERR_PHY;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+/**\n+ *  ngbe_write_phy_reg - Writes a value to specified PHY register\n+ *  using SWFW lock- this function is needed in most cases\n+ *  @hw: pointer to hardware structure\n+ *  @reg_addr: 32 bit PHY register to write\n+ *  @device_type: 5 bit device type\n+ *  @phy_data: Data to write to the PHY register\n+ **/\n+s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data)\n+{\n+\ts32 err;\n+\tu32 gssr = hw->phy.phy_semaphore_mask;\n+\n+\tDEBUGFUNC(\"ngbe_write_phy_reg\");\n+\n+\tif (hw->mac.acquire_swfw_sync(hw, gssr))\n+\t\terr = NGBE_ERR_SWFW_SYNC;\n+\n+\terr = hw->phy.write_reg_unlocked(hw, reg_addr, device_type,\n+\t\t\t\t\t phy_data);\n+\n+\thw->mac.release_swfw_sync(hw, gssr);\n+\n+\treturn err;\n+}\n+\n+/**\n+ *  ngbe_init_phy - PHY specific init\n+ *  @hw: pointer to hardware structure\n+ *\n+ *  Initialize any function pointers that were not able to be\n+ *  set during init_shared_code because the PHY type was\n+ *  not known.\n+ *\n+ **/\n+s32 ngbe_init_phy(struct ngbe_hw *hw)\n+{\n+\tstruct ngbe_phy_info *phy = &hw->phy;\n+\ts32 err = 0;\n+\n+\tDEBUGFUNC(\"ngbe_init_phy\");\n+\n+\thw->phy.addr = 0;\n+\n+\tswitch (hw->sub_device_id) {\n+\tcase NGBE_SUB_DEV_ID_EM_RTL_SGMII:\n+\t\thw->phy.read_reg_unlocked = ngbe_read_phy_reg_rtl;\n+\t\thw->phy.write_reg_unlocked = ngbe_write_phy_reg_rtl;\n+\t\tbreak;\n+\tcase NGBE_SUB_DEV_ID_EM_MVL_RGMII:\n+\tcase NGBE_SUB_DEV_ID_EM_MVL_SFP:\n+\t\thw->phy.read_reg_unlocked = ngbe_read_phy_reg_mvl;\n+\t\thw->phy.write_reg_unlocked = ngbe_write_phy_reg_mvl;\n+\t\tbreak;\n+\tcase NGBE_SUB_DEV_ID_EM_YT8521S_SFP:\n+\t\thw->phy.read_reg_unlocked = ngbe_read_phy_reg_yt;\n+\t\thw->phy.write_reg_unlocked = ngbe_write_phy_reg_yt;\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+\n+\thw->phy.phy_semaphore_mask = NGBE_MNGSEM_SWPHY;\n+\n+\t/* Identify the PHY */\n+\terr = phy->identify(hw);\n+\n+\treturn err;\n+}\n+\ndiff --git a/drivers/net/ngbe/base/ngbe_phy.h b/drivers/net/ngbe/base/ngbe_phy.h\nnew file mode 100644\nindex 0000000000..226e0189ec\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy.h\n@@ -0,0 +1,60 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ * Copyright(c) 2010-2017 Intel Corporation\n+ */\n+\n+#ifndef _NGBE_PHY_H_\n+#define _NGBE_PHY_H_\n+\n+#include \"ngbe_type.h\"\n+#include \"ngbe_phy_rtl.h\"\n+#include \"ngbe_phy_mvl.h\"\n+#include \"ngbe_phy_yt.h\"\n+\n+/******************************************************************************\n+ * PHY MDIO Registers:\n+ ******************************************************************************/\n+#define NGBE_MAX_PHY_ADDR\t\t32\n+\n+/* (dev_type = 1) */\n+#define NGBE_MD_DEV_PMA_PMD\t\t0x1\n+#define NGBE_MD_PHY_ID_HIGH\t\t0x2 /* PHY ID High Reg*/\n+#define NGBE_MD_PHY_ID_LOW\t\t0x3 /* PHY ID Low Reg*/\n+#define   NGBE_PHY_REVISION_MASK\t0xFFFFFFF0\n+\n+/* IEEE 802.3 Clause 22 */\n+struct mdi_reg_22 {\n+\tu16 page;\n+\tu16 addr;\n+\tu16 device_type;\n+};\n+typedef struct mdi_reg_22 mdi_reg_22_t;\n+\n+/* IEEE 802.3ae Clause 45 */\n+struct mdi_reg {\n+\tu16 device_type;\n+\tu16 addr;\n+};\n+typedef struct mdi_reg mdi_reg_t;\n+\n+#define NGBE_MD22_PHY_ID_HIGH\t\t0x2 /* PHY ID High Reg*/\n+#define NGBE_MD22_PHY_ID_LOW\t\t0x3 /* PHY ID Low Reg*/\n+\n+s32 ngbe_mdi_map_register(mdi_reg_t *reg, mdi_reg_22_t *reg22);\n+\n+bool ngbe_validate_phy_addr(struct ngbe_hw *hw, u32 phy_addr);\n+enum ngbe_phy_type ngbe_get_phy_type_from_id(struct ngbe_hw *hw);\n+s32 ngbe_get_phy_id(struct ngbe_hw *hw);\n+s32 ngbe_identify_phy(struct ngbe_hw *hw);\n+s32 ngbe_reset_phy(struct ngbe_hw *hw);\n+s32 ngbe_read_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\t   u16 *phy_data);\n+s32 ngbe_write_phy_reg_mdi(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\t    u16 phy_data);\n+s32 ngbe_read_phy_reg(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t       u32 device_type, u16 *phy_data);\n+s32 ngbe_write_phy_reg(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data);\n+s32 ngbe_check_reset_blocked(struct ngbe_hw *hw);\n+\n+#endif /* _NGBE_PHY_H_ */\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.c b/drivers/net/ngbe/base/ngbe_phy_mvl.c\nnew file mode 100644\nindex 0000000000..1248478252\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.c\n@@ -0,0 +1,89 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ */\n+\n+#include \"ngbe_phy_mvl.h\"\n+\n+#define MVL_PHY_RST_WAIT_PERIOD  5\n+\n+s32 ngbe_read_phy_reg_mvl(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 *phy_data)\n+{\n+\tmdi_reg_t reg;\n+\tmdi_reg_22_t reg22;\n+\n+\treg.device_type = device_type;\n+\treg.addr = reg_addr;\n+\n+\tif (hw->phy.media_type == ngbe_media_type_fiber)\n+\t\tngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 1);\n+\telse\n+\t\tngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 0);\n+\n+\tngbe_mdi_map_register(&reg, &reg22);\n+\n+\tngbe_read_phy_reg_mdi(hw, reg22.addr, reg22.device_type, phy_data);\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 phy_data)\n+{\n+\tmdi_reg_t reg;\n+\tmdi_reg_22_t reg22;\n+\n+\treg.device_type = device_type;\n+\treg.addr = reg_addr;\n+\n+\tif (hw->phy.media_type == ngbe_media_type_fiber)\n+\t\tngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 1);\n+\telse\n+\t\tngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 0);\n+\n+\tngbe_mdi_map_register(&reg, &reg22);\n+\n+\tngbe_write_phy_reg_mdi(hw, reg22.addr, reg22.device_type, phy_data);\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw)\n+{\n+\tu32 i;\n+\tu16 ctrl = 0;\n+\ts32 status = 0;\n+\n+\tDEBUGFUNC(\"ngbe_reset_phy_mvl\");\n+\n+\tif (hw->phy.type != ngbe_phy_mvl && hw->phy.type != ngbe_phy_mvl_sfi)\n+\t\treturn NGBE_ERR_PHY_TYPE;\n+\n+\t/* select page 18 reg 20 */\n+\tstatus = ngbe_write_phy_reg_mdi(hw, MVL_PAGE_SEL, 0, 18);\n+\n+\t/* mode select to RGMII-to-copper or RGMII-to-sfi*/\n+\tif (hw->phy.type == ngbe_phy_mvl)\n+\t\tctrl = MVL_GEN_CTL_MODE_COPPER;\n+\telse\n+\t\tctrl = MVL_GEN_CTL_MODE_FIBER;\n+\tstatus = ngbe_write_phy_reg_mdi(hw, MVL_GEN_CTL, 0, ctrl);\n+\t/* mode reset */\n+\tctrl |= MVL_GEN_CTL_RESET;\n+\tstatus = ngbe_write_phy_reg_mdi(hw, MVL_GEN_CTL, 0, ctrl);\n+\n+\tfor (i = 0; i < MVL_PHY_RST_WAIT_PERIOD; i++) {\n+\t\tstatus = ngbe_read_phy_reg_mdi(hw, MVL_GEN_CTL, 0, &ctrl);\n+\t\tif (!(ctrl & MVL_GEN_CTL_RESET))\n+\t\t\tbreak;\n+\t\tmsleep(1);\n+\t}\n+\n+\tif (i == MVL_PHY_RST_WAIT_PERIOD) {\n+\t\tDEBUGOUT(\"PHY reset polling failed to complete.\\n\");\n+\t\treturn NGBE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn status;\n+}\n+\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_mvl.h b/drivers/net/ngbe/base/ngbe_phy_mvl.h\nnew file mode 100644\nindex 0000000000..ca39f3cd58\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy_mvl.h\n@@ -0,0 +1,92 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ */\n+\n+#include \"ngbe_phy.h\"\n+\n+#ifndef _NGBE_PHY_MVL_H_\n+#define _NGBE_PHY_MVL_H_\n+\n+#define NGBE_PHYID_MVL\t\t\t0x01410DD0U\n+\n+/* Page 0 for Copper, Page 1 for Fiber */\n+#define MVL_CTRL\t\t\t0x0\n+#define   MVL_CTRL_RESET\t\tMS16(15, 0x1)\n+#define   MVL_CTRL_ANE\t\t\tMS16(12, 0x1)\n+#define   MVL_CTRL_RESTART_AN\t\tMS16(9, 0x1)\n+#define MVL_ANA\t\t\t\t0x4\n+/* copper */\n+#define   MVL_CANA_ASM_PAUSE\t\tMS16(11, 0x1)\n+#define   MVL_CANA_PAUSE\t\tMS16(10, 0x1)\n+#define   MVL_PHY_100BASET_FULL\t\tMS16(8, 0x1)\n+#define   MVL_PHY_100BASET_HALF\t\tMS16(7, 0x1)\n+#define   MVL_PHY_10BASET_FULL\t\tMS16(6, 0x1)\n+#define   MVL_PHY_10BASET_HALF\t\tMS16(5, 0x1)\n+/* fiber */\n+#define   MVL_FANA_PAUSE_MASK\t\tMS16(7, 0x3)\n+#define     MVL_FANA_SYM_PAUSE\t\tLS16(1, 7, 0x3)\n+#define     MVL_FANA_ASM_PAUSE\t\tLS16(2, 7, 0x3)\n+#define   MVL_PHY_1000BASEX_HALF\tMS16(6, 0x1)\n+#define   MVL_PHY_1000BASEX_FULL\tMS16(5, 0x1)\n+#define MVL_LPAR\t\t\t0x5\n+#define   MVL_CLPAR_ASM_PAUSE\t\tMS(11, 0x1)\n+#define   MVL_CLPAR_PAUSE\t\tMS(10, 0x1)\n+#define   MVL_FLPAR_PAUSE_MASK\t\tMS(7, 0x3)\n+#define MVL_PHY_1000BASET\t\t0x9\n+#define   MVL_PHY_1000BASET_FULL\tMS16(9, 0x1)\n+#define   MVL_PHY_1000BASET_HALF\tMS16(8, 0x1)\n+#define MVL_CTRL1\t\t\t0x10\n+#define   MVL_CTRL1_INTR_POL\t\tMS16(2, 0x1)\n+#define MVL_PHYSR\t\t\t0x11\n+#define   MVL_PHYSR_SPEED_MASK\t\tMS16(14, 0x3)\n+#define     MVL_PHYSR_SPEED_1000M\tLS16(2, 14, 0x3)\n+#define     MVL_PHYSR_SPEED_100M\tLS16(1, 14, 0x3)\n+#define     MVL_PHYSR_SPEED_10M\t\tLS16(0, 14, 0x3)\n+#define   MVL_PHYSR_LINK\t\tMS16(10, 0x1)\n+#define MVL_INTR_EN\t\t\t0x12\n+#define   MVL_INTR_EN_ANC\t\tMS16(11, 0x1)\n+#define   MVL_INTR_EN_LSC\t\tMS16(10, 0x1)\n+#define MVL_INTR\t\t\t0x13\n+#define   MVL_INTR_ANC\t\t\tMS16(11, 0x1)\n+#define   MVL_INTR_LSC\t\t\tMS16(10, 0x1)\n+\n+/* Page 2 */\n+#define MVL_RGM_CTL2\t\t\t0x15\n+#define   MVL_RGM_CTL2_TTC\t\tMS16(4, 0x1)\n+#define   MVL_RGM_CTL2_RTC\t\tMS16(5, 0x1)\n+/* Page 3 */\n+#define MVL_LEDFCR\t\t\t0x10\n+#define   MVL_LEDFCR_CTL1\t\tMS16(4, 0xF)\n+#define     MVL_LEDFCR_CTL1_CONF\tLS16(6, 4, 0xF)\n+#define   MVL_LEDFCR_CTL0\t\tMS16(0, 0xF)\n+#define     MVL_LEDFCR_CTL0_CONF\tLS16(1, 0, 0xF)\n+#define MVL_LEDPCR\t\t\t0x11\n+#define   MVL_LEDPCR_CTL1\t\tMS16(2, 0x3)\n+#define     MVL_LEDPCR_CTL1_CONF\tLS16(1, 2, 0x3)\n+#define   MVL_LEDPCR_CTL0\t\tMS16(0, 0x3)\n+#define     MVL_LEDPCR_CTL0_CONF\tLS16(1, 0, 0x3)\n+#define MVL_LEDTCR\t\t\t0x12\n+#define   MVL_LEDTCR_INTR_POL\t\tMS16(11, 0x1)\n+#define   MVL_LEDTCR_INTR_EN\t\tMS16(7, 0x1)\n+/* Page 18 */\n+#define MVL_GEN_CTL\t\t\t0x14\n+#define   MVL_GEN_CTL_RESET\t\tMS16(15, 0x1)\n+#define   MVL_GEN_CTL_MODE(v)\t\tLS16(v, 0, 0x7)\n+#define     MVL_GEN_CTL_MODE_COPPER\tLS16(0, 0, 0x7)\n+#define     MVL_GEN_CTL_MODE_FIBER\tLS16(2, 0, 0x7)\n+\n+/* reg 22 */\n+#define MVL_PAGE_SEL\t\t\t22\n+\n+/* reg 19_0 INT status*/\n+#define MVL_PHY_ANC                      0x0800\n+#define MVL_PHY_LSC                      0x0400\n+\n+s32 ngbe_read_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\tu16 *phy_data);\n+s32 ngbe_write_phy_reg_mvl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\tu16 phy_data);\n+\n+s32 ngbe_reset_phy_mvl(struct ngbe_hw *hw);\n+\n+#endif /* _NGBE_PHY_MVL_H_ */\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_rtl.c b/drivers/net/ngbe/base/ngbe_phy_rtl.c\nnew file mode 100644\nindex 0000000000..400fbe8c1f\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy_rtl.c\n@@ -0,0 +1,65 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ */\n+\n+#include \"ngbe_phy_rtl.h\"\n+\n+#define RTL_PHY_RST_WAIT_PERIOD               5\n+\n+s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 *phy_data)\n+{\n+\tmdi_reg_t reg;\n+\tmdi_reg_22_t reg22;\n+\n+\treg.device_type = device_type;\n+\treg.addr = reg_addr;\n+\tngbe_mdi_map_register(&reg, &reg22);\n+\n+\twr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);\n+\t*phy_data = 0xFFFF & rd32(hw, NGBE_PHY_CONFIG(reg22.addr));\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 phy_data)\n+{\n+\tmdi_reg_t reg;\n+\tmdi_reg_22_t reg22;\n+\n+\treg.device_type = device_type;\n+\treg.addr = reg_addr;\n+\tngbe_mdi_map_register(&reg, &reg22);\n+\n+\twr32(hw, NGBE_PHY_CONFIG(RTL_PAGE_SELECT), reg22.page);\n+\twr32(hw, NGBE_PHY_CONFIG(reg22.addr), phy_data);\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw)\n+{\n+\tu16 value = 0, i;\n+\ts32 status = 0;\n+\n+\tDEBUGFUNC(\"ngbe_reset_phy_rtl\");\n+\n+\tvalue |= RTL_BMCR_RESET;\n+\tstatus = hw->phy.write_reg(hw, RTL_BMCR, RTL_DEV_ZERO, value);\n+\n+\tfor (i = 0; i < RTL_PHY_RST_WAIT_PERIOD; i++) {\n+\t\tstatus = hw->phy.read_reg(hw, RTL_BMCR, RTL_DEV_ZERO, &value);\n+\t\tif (!(value & RTL_BMCR_RESET))\n+\t\t\tbreak;\n+\t\tmsleep(1);\n+\t}\n+\n+\tif (i == RTL_PHY_RST_WAIT_PERIOD) {\n+\t\tDEBUGOUT(\"PHY reset polling failed to complete.\\n\");\n+\t\treturn NGBE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn status;\n+}\n+\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_rtl.h b/drivers/net/ngbe/base/ngbe_phy_rtl.h\nnew file mode 100644\nindex 0000000000..2da5c7b626\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy_rtl.h\n@@ -0,0 +1,83 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ */\n+\n+#include \"ngbe_phy.h\"\n+\n+#ifndef _NGBE_PHY_RTL_H_\n+#define _NGBE_PHY_RTL_H_\n+\n+#define NGBE_PHYID_RTL\t\t\t0x001CC800U\n+\n+/* Page 0 */\n+#define RTL_DEV_ZERO\t\t\t0\n+#define RTL_BMCR\t\t\t0x0\n+#define   RTL_BMCR_RESET\t\tMS16(15, 0x1)\n+#define\t  RTL_BMCR_SPEED_SELECT0\tMS16(13, 0x1)\n+#define   RTL_BMCR_ANE\t\t\tMS16(12, 0x1)\n+#define   RTL_BMCR_RESTART_AN\t\tMS16(9, 0x1)\n+#define   RTL_BMCR_DUPLEX\t\tMS16(8, 0x1)\n+#define   RTL_BMCR_SPEED_SELECT1\tMS16(6, 0x1)\n+#define RTL_BMSR\t\t\t0x1\n+#define   RTL_BMSR_ANC\t\t\tMS16(5, 0x1)\n+#define RTL_ID1_OFFSET\t\t\t0x2\n+#define RTL_ID2_OFFSET\t\t\t0x3\n+#define RTL_ID_MASK\t\t\t0xFFFFFC00U\n+#define RTL_ANAR\t\t\t0x4\n+#define   RTL_ANAR_APAUSE\t\tMS16(11, 0x1)\n+#define   RTL_ANAR_PAUSE\t\tMS16(10, 0x1)\n+#define   RTL_ANAR_100F\t\t\tMS16(8, 0x1)\n+#define   RTL_ANAR_100H\t\t\tMS16(7, 0x1)\n+#define   RTL_ANAR_10F\t\t\tMS16(6, 0x1)\n+#define   RTL_ANAR_10H\t\t\tMS16(5, 0x1)\n+#define RTL_ANLPAR\t\t\t0x5\n+#define   RTL_ANLPAR_LP\t\t\tMS16(10, 0x3)\n+#define RTL_GBCR\t\t\t0x9\n+#define   RTL_GBCR_1000F\t\tMS16(9, 0x1)\n+/* Page 0xa42*/\n+#define RTL_GSR\t\t\t\t0x10\n+#define   RTL_GSR_ST\t\t\tMS16(0, 0x7)\n+#define   RTL_GSR_ST_LANON\t\tMS16(0, 0x3)\n+#define RTL_INER\t\t\t0x12\n+#define   RTL_INER_LSC\t\t\tMS16(4, 0x1)\n+#define   RTL_INER_ANC\t\t\tMS16(3, 0x1)\n+/* Page 0xa43*/\n+#define RTL_PHYSR\t\t\t0x1A\n+#define   RTL_PHYSR_SPEED_MASK\t\tMS16(4, 0x3)\n+#define     RTL_PHYSR_SPEED_RES\t\tLS16(3, 4, 0x3)\n+#define     RTL_PHYSR_SPEED_1000M\tLS16(2, 4, 0x3)\n+#define     RTL_PHYSR_SPEED_100M\tLS16(1, 4, 0x3)\n+#define     RTL_PHYSR_SPEED_10M\t\tLS16(0, 4, 0x3)\n+#define   RTL_PHYSR_DP\t\t\tMS16(3, 0x1)\n+#define   RTL_PHYSR_RTLS\t\tMS16(2, 0x1)\n+#define RTL_INSR\t\t\t0x1D\n+#define   RTL_INSR_ACCESS\t\tMS16(5, 0x1)\n+#define   RTL_INSR_LSC\t\t\tMS16(4, 0x1)\n+#define   RTL_INSR_ANC\t\t\tMS16(3, 0x1)\n+/* Page 0xa46*/\n+#define RTL_SCR\t\t\t\t0x14\n+#define   RTL_SCR_EXTINI\t\tMS16(1, 0x1)\n+#define   RTL_SCR_EFUSE\t\t\tMS16(0, 0x1)\n+/* Page 0xa47*/\n+/* Page 0xd04*/\n+#define RTL_LCR\t\t\t\t0x10\n+#define RTL_EEELCR\t\t\t0x11\n+#define RTL_LPCR\t\t\t0x12\n+\n+/* INTERNAL PHY CONTROL */\n+#define RTL_PAGE_SELECT\t\t\t31\n+#define NGBE_INTERNAL_PHY_OFFSET_MAX\t32\n+#define NGBE_INTERNAL_PHY_ID\t\t0x000732\n+\n+#define NGBE_INTPHY_LED0\t\t0x0010\n+#define NGBE_INTPHY_LED1\t\t0x0040\n+#define NGBE_INTPHY_LED2\t\t0x2000\n+\n+s32 ngbe_read_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\tu16 *phy_data);\n+s32 ngbe_write_phy_reg_rtl(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\tu16 phy_data);\n+\n+s32 ngbe_reset_phy_rtl(struct ngbe_hw *hw);\n+\n+#endif /* _NGBE_PHY_RTL_H_ */\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_yt.c b/drivers/net/ngbe/base/ngbe_phy_yt.c\nnew file mode 100644\nindex 0000000000..a5b032240c\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy_yt.c\n@@ -0,0 +1,112 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ */\n+\n+#include \"ngbe_phy_yt.h\"\n+\n+#define YT_PHY_RST_WAIT_PERIOD\t\t5\n+\n+s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 *phy_data)\n+{\n+\tmdi_reg_t reg;\n+\tmdi_reg_22_t reg22;\n+\n+\treg.device_type = device_type;\n+\treg.addr = reg_addr;\n+\n+\tngbe_mdi_map_register(&reg, &reg22);\n+\n+\t/* Read MII reg according to media type */\n+\tif (hw->phy.media_type == ngbe_media_type_fiber) {\n+\t\tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,\n+\t\t\t\t\treg22.device_type, YT_SMI_PHY_SDS);\n+\t\tngbe_read_phy_reg_mdi(hw, reg22.addr,\n+\t\t\t\t\treg22.device_type, phy_data);\n+\t\tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,\n+\t\t\t\t\treg22.device_type, 0);\n+\t} else {\n+\t\tngbe_read_phy_reg_mdi(hw, reg22.addr,\n+\t\t\t\t\treg22.device_type, phy_data);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_write_phy_reg_yt(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 phy_data)\n+{\n+\tmdi_reg_t reg;\n+\tmdi_reg_22_t reg22;\n+\n+\treg.device_type = device_type;\n+\treg.addr = reg_addr;\n+\n+\tngbe_mdi_map_register(&reg, &reg22);\n+\n+\t/* Write MII reg according to media type */\n+\tif (hw->phy.media_type == ngbe_media_type_fiber) {\n+\t\tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,\n+\t\t\t\t\treg22.device_type, YT_SMI_PHY_SDS);\n+\t\tngbe_write_phy_reg_mdi(hw, reg22.addr,\n+\t\t\t\t\treg22.device_type, phy_data);\n+\t\tngbe_write_phy_reg_ext_yt(hw, YT_SMI_PHY,\n+\t\t\t\t\treg22.device_type, 0);\n+\t} else {\n+\t\tngbe_write_phy_reg_mdi(hw, reg22.addr,\n+\t\t\t\t\treg22.device_type, phy_data);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_read_phy_reg_ext_yt(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 *phy_data)\n+{\n+\tngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);\n+\tngbe_read_phy_reg_mdi(hw, 0x1F, device_type, phy_data);\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_write_phy_reg_ext_yt(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 phy_data)\n+{\n+\tngbe_write_phy_reg_mdi(hw, 0x1E, device_type, reg_addr);\n+\tngbe_write_phy_reg_mdi(hw, 0x1F, device_type, phy_data);\n+\n+\treturn 0;\n+}\n+\n+s32 ngbe_reset_phy_yt(struct ngbe_hw *hw)\n+{\n+\tu32 i;\n+\tu16 ctrl = 0;\n+\ts32 status = 0;\n+\n+\tDEBUGFUNC(\"ngbe_reset_phy_yt\");\n+\n+\tif (hw->phy.type != ngbe_phy_yt8521s &&\n+\t\thw->phy.type != ngbe_phy_yt8521s_sfi)\n+\t\treturn NGBE_ERR_PHY_TYPE;\n+\n+\tstatus = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);\n+\t/* sds software reset */\n+\tctrl |= YT_BCR_RESET;\n+\tstatus = hw->phy.write_reg(hw, YT_BCR, 0, ctrl);\n+\n+\tfor (i = 0; i < YT_PHY_RST_WAIT_PERIOD; i++) {\n+\t\tstatus = hw->phy.read_reg(hw, YT_BCR, 0, &ctrl);\n+\t\tif (!(ctrl & YT_BCR_RESET))\n+\t\t\tbreak;\n+\t\tmsleep(1);\n+\t}\n+\n+\tif (i == YT_PHY_RST_WAIT_PERIOD) {\n+\t\tDEBUGOUT(\"PHY reset polling failed to complete.\\n\");\n+\t\treturn NGBE_ERR_RESET_FAILED;\n+\t}\n+\n+\treturn status;\n+}\n+\ndiff --git a/drivers/net/ngbe/base/ngbe_phy_yt.h b/drivers/net/ngbe/base/ngbe_phy_yt.h\nnew file mode 100644\nindex 0000000000..6d49464d6d\n--- /dev/null\n+++ b/drivers/net/ngbe/base/ngbe_phy_yt.h\n@@ -0,0 +1,67 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(c) 2018-2021 Beijing WangXun Technology Co., Ltd.\n+ */\n+\n+#include \"ngbe_phy.h\"\n+\n+#ifndef _NGBE_PHY_YT_H_\n+#define _NGBE_PHY_YT_H_\n+\n+#define NGBE_PHYID_YT\t\t\t0x00000110U\n+\n+/* Common EXT */\n+#define YT_SMI_PHY\t\t\t0xA000\n+#define   YT_SMI_PHY_SDS\t\tMS16(1, 0x1) /* 0 for UTP */\n+#define YT_CHIP\t\t\t\t0xA001\n+#define   YT_CHIP_SW_RST\t\tMS16(15, 0x1)\n+#define   YT_CHIP_SW_LDO_EN\t\tMS16(6, 0x1)\n+#define   YT_CHIP_MODE_SEL(v)\t\tLS16(v, 0, 0x7)\n+#define YT_RGMII_CONF1\t\t\t0xA003\n+#define   YT_RGMII_CONF1_RXDELAY\tMS16(10, 0xF)\n+#define   YT_RGMII_CONF1_TXDELAY_FE\tMS16(4, 0xF)\n+#define   YT_RGMII_CONF1_TXDELAY\tMS16(0, 0x1)\n+#define YT_MISC\t\t\t\t0xA006\n+#define   YT_MISC_FIBER_PRIO\t\tMS16(8, 0x1) /* 0 for UTP */\n+\n+/* MII common registers in UTP and SDS */\n+#define YT_BCR\t\t\t\t0x0\n+#define   YT_BCR_RESET\t\t\tMS16(15, 0x1)\n+#define   YT_BCR_PWDN\t\t\tMS16(11, 0x1)\n+#define YT_ANA\t\t\t\t0x4\n+/* copper */\n+#define   YT_ANA_100BASET_FULL\t\tMS16(8, 0x1)\n+#define   YT_ANA_10BASET_FULL\t\tMS16(6, 0x1)\n+/* fiber */\n+#define   YT_FANA_PAUSE_MASK\t\tMS16(7, 0x3)\n+\n+#define YT_LPAR\t\t\t\t0x5\n+#define   YT_CLPAR_ASM_PAUSE\t\tMS(11, 0x1)\n+#define   YT_CLPAR_PAUSE\t\tMS(10, 0x1)\n+#define   YT_FLPAR_PAUSE_MASK\t\tMS(7, 0x3)\n+\n+#define YT_MS_CTRL\t\t\t0x9\n+#define   YT_MS_1000BASET_FULL\t\tMS16(9, 0x1)\n+#define YT_SPST\t\t\t\t0x11\n+#define   YT_SPST_SPEED_MASK\t\tMS16(14, 0x3)\n+#define\t    YT_SPST_SPEED_1000M\t\tLS16(2, 14, 0x3)\n+#define\t    YT_SPST_SPEED_100M\t\tLS16(1, 14, 0x3)\n+#define\t    YT_SPST_SPEED_10M\t\tLS16(0, 14, 0x3)\n+#define   YT_SPST_LINK\t\t\tMS16(10, 0x1)\n+\n+/* UTP only */\n+#define YT_INTR\t\t\t\t0x12\n+#define   YT_INTR_ENA_MASK\t\tMS16(2, 0x3)\n+#define YT_INTR_STATUS\t\t\t0x13\n+\n+s32 ngbe_read_phy_reg_yt(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\tu16 *phy_data);\n+s32 ngbe_write_phy_reg_yt(struct ngbe_hw *hw, u32 reg_addr, u32 device_type,\n+\t\t\tu16 phy_data);\n+s32 ngbe_read_phy_reg_ext_yt(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 *phy_data);\n+s32 ngbe_write_phy_reg_ext_yt(struct ngbe_hw *hw,\n+\t\tu32 reg_addr, u32 device_type, u16 phy_data);\n+\n+s32 ngbe_reset_phy_yt(struct ngbe_hw *hw);\n+\n+#endif /* _NGBE_PHY_YT_H_ */\ndiff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h\nindex 9741cb7687..0eabc21b2b 100644\n--- a/drivers/net/ngbe/base/ngbe_type.h\n+++ b/drivers/net/ngbe/base/ngbe_type.h\n@@ -94,6 +94,7 @@ struct ngbe_mac_info {\n \n \t/* Manageability interface */\n \ts32 (*init_thermal_sensor_thresh)(struct ngbe_hw *hw);\n+\ts32 (*check_overtemp)(struct ngbe_hw *hw);\n \n \tenum ngbe_mac_type type;\n \tu32 max_tx_queues;\n@@ -103,8 +104,24 @@ struct ngbe_mac_info {\n };\n \n struct ngbe_phy_info {\n+\ts32 (*identify)(struct ngbe_hw *hw);\n+\ts32 (*reset_hw)(struct ngbe_hw *hw);\n+\ts32 (*read_reg)(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 *phy_data);\n+\ts32 (*write_reg)(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data);\n+\ts32 (*read_reg_unlocked)(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 *phy_data);\n+\ts32 (*write_reg_unlocked)(struct ngbe_hw *hw, u32 reg_addr,\n+\t\t\t\tu32 device_type, u16 phy_data);\n+\n \tenum ngbe_media_type media_type;\n \tenum ngbe_phy_type type;\n+\tu32 addr;\n+\tu32 id;\n+\tu32 revision;\n+\tu32 phy_semaphore_mask;\n+\tbool reset_disable;\n };\n \n struct ngbe_hw {\n",
    "prefixes": [
        "v7",
        "08/19"
    ]
}