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GET /api/patches/95359/?format=api
{ "id": 95359, "url": "http://patchwork.dpdk.org/api/patches/95359/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210706095545.10776-16-jiawenwu@trustnetic.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210706095545.10776-16-jiawenwu@trustnetic.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210706095545.10776-16-jiawenwu@trustnetic.com", "date": "2021-07-06T09:55:41", "name": "[v7,15/19] net/ngbe: add Tx queue start and stop", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "9622d6527edb1bef8ba5e24216cd9c0c05b94eaf", "submitter": { "id": 1932, "url": "http://patchwork.dpdk.org/api/people/1932/?format=api", "name": "Jiawen Wu", "email": "jiawenwu@trustnetic.com" }, "delegate": { "id": 3961, "url": "http://patchwork.dpdk.org/api/users/3961/?format=api", "username": "arybchenko", "first_name": "Andrew", "last_name": "Rybchenko", "email": "andrew.rybchenko@oktetlabs.ru" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210706095545.10776-16-jiawenwu@trustnetic.com/mbox/", "series": [ { "id": 17659, "url": "http://patchwork.dpdk.org/api/series/17659/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17659", "date": "2021-07-06T09:55:28", "name": "net: ngbe PMD", "version": 7, "mbox": "http://patchwork.dpdk.org/series/17659/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/95359/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/95359/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 520C3A0C47;\n\tTue, 6 Jul 2021 11:58:28 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 433E141340;\n\tTue, 6 Jul 2021 11:56:24 +0200 (CEST)", "from smtpbg506.qq.com (smtpbg506.qq.com [203.205.250.33])\n by mails.dpdk.org (Postfix) with ESMTP id F022E41365\n for <dev@dpdk.org>; Tue, 6 Jul 2021 11:56:21 +0200 (CEST)", "from jiawenwu.trustnetic.com (unknown [183.129.236.74])\n by esmtp6.qq.com (ESMTP) with\n id ; Tue, 06 Jul 2021 17:56:18 +0800 (CST)" ], "X-QQ-mid": "bizesmtp51t1625565378thkghfag", "X-QQ-SSF": "01400000002000D0E000B00A0000000", "X-QQ-FEAT": "b0oIbfUHMAjGGdOzQ+5j5l+QDcY029QKRYe68T7/mD/TPeUvIcie4pyAKSfoq\n k12fTD3Rw42E4y3sgRWiz/9o9u27L7kVR6ABaBcG6Mb7e55S9yoYK4bxsT+76f8FhaWPdqo\n 7JuoTb8PuiXhN+SHagxNQiihATKNeQGO6xSUS6AnVWuM7vAVDwULH2hJ5rZr61Zc48BhkHl\n G18TkZxSzUAwTrAMYgyipczvoE73QA+Twmd/YhoFlAY/SMsGfSL2h73eAGdZOnQMY+hvsem\n K7APiBEmwUWr4FdPUJ9uM2vbewSA01ki2BKn0wTBbIwXYFeutd9tgXAn1XmAlbg8En8GE5y\n dQyyy6IcdOrgWHlvnEbaf6DUTSbZFDz6raSajVT", "X-QQ-GoodBg": "2", "From": "Jiawen Wu <jiawenwu@trustnetic.com>", "To": "dev@dpdk.org", "Cc": "Jiawen Wu <jiawenwu@trustnetic.com>", "Date": "Tue, 6 Jul 2021 17:55:41 +0800", "Message-Id": "<20210706095545.10776-16-jiawenwu@trustnetic.com>", "X-Mailer": "git-send-email 2.21.0.windows.1", "In-Reply-To": "<20210706095545.10776-1-jiawenwu@trustnetic.com>", "References": "<20210706095545.10776-1-jiawenwu@trustnetic.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-QQ-SENDSIZE": "520", "Feedback-ID": "bizesmtp:trustnetic.com:qybgforeign:qybgforeign5", "X-QQ-Bgrelay": "1", "Subject": "[dpdk-dev] [PATCH v7 15/19] net/ngbe: add Tx queue start and stop", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Initializes transmit unit, support to start and stop transmit unit for\nspecified queues.\n\nSigned-off-by: Jiawen Wu <jiawenwu@trustnetic.com>\n---\n doc/guides/nics/features/ngbe.ini | 1 +\n drivers/net/ngbe/base/ngbe_type.h | 1 +\n drivers/net/ngbe/ngbe_ethdev.c | 3 +\n drivers/net/ngbe/ngbe_ethdev.h | 7 ++\n drivers/net/ngbe/ngbe_rxtx.c | 161 +++++++++++++++++++++++++++++-\n drivers/net/ngbe/ngbe_rxtx.h | 3 +\n 6 files changed, 174 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/nics/features/ngbe.ini b/doc/guides/nics/features/ngbe.ini\nindex 291a542a42..08d5f1b0dc 100644\n--- a/doc/guides/nics/features/ngbe.ini\n+++ b/doc/guides/nics/features/ngbe.ini\n@@ -7,6 +7,7 @@\n Speed capabilities = Y\n Link status = Y\n Link status event = Y\n+Queue start/stop = Y\n Multiprocess aware = Y\n Linux = Y\n ARMv8 = Y\ndiff --git a/drivers/net/ngbe/base/ngbe_type.h b/drivers/net/ngbe/base/ngbe_type.h\nindex 3f6698be15..2846a6a2b6 100644\n--- a/drivers/net/ngbe/base/ngbe_type.h\n+++ b/drivers/net/ngbe/base/ngbe_type.h\n@@ -190,6 +190,7 @@ struct ngbe_hw {\n \tu16 nb_rx_queues;\n \tu16 nb_tx_queues;\n \n+\tu32 q_tx_regs[8 * 4];\n \tbool is_pf;\n };\n \ndiff --git a/drivers/net/ngbe/ngbe_ethdev.c b/drivers/net/ngbe/ngbe_ethdev.c\nindex f88e71b855..f1911bdcbc 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.c\n+++ b/drivers/net/ngbe/ngbe_ethdev.c\n@@ -598,6 +598,7 @@ ngbe_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\t\t\tETH_LINK_SPEED_10M;\n \n \t/* Driver-preferred Rx/Tx parameters */\n+\tdev_info->default_txportconf.burst_size = 32;\n \tdev_info->default_rxportconf.nb_queues = 1;\n \tdev_info->default_txportconf.nb_queues = 1;\n \tdev_info->default_rxportconf.ring_size = 256;\n@@ -1089,6 +1090,8 @@ static const struct eth_dev_ops ngbe_eth_dev_ops = {\n \t.dev_start = ngbe_dev_start,\n \t.dev_stop = ngbe_dev_stop,\n \t.link_update = ngbe_dev_link_update,\n+\t.tx_queue_start\t = ngbe_dev_tx_queue_start,\n+\t.tx_queue_stop = ngbe_dev_tx_queue_stop,\n \t.rx_queue_setup = ngbe_dev_rx_queue_setup,\n \t.rx_queue_release = ngbe_dev_rx_queue_release,\n \t.tx_queue_setup = ngbe_dev_tx_queue_setup,\ndiff --git a/drivers/net/ngbe/ngbe_ethdev.h b/drivers/net/ngbe/ngbe_ethdev.h\nindex 55c8a3c022..f631d847ad 100644\n--- a/drivers/net/ngbe/ngbe_ethdev.h\n+++ b/drivers/net/ngbe/ngbe_ethdev.h\n@@ -86,6 +86,13 @@ void ngbe_dev_tx_init(struct rte_eth_dev *dev);\n \n int ngbe_dev_rxtx_start(struct rte_eth_dev *dev);\n \n+void ngbe_dev_save_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id);\n+void ngbe_dev_store_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id);\n+\n+int ngbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n+int ngbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id);\n+\n void ngbe_set_ivar_map(struct ngbe_hw *hw, int8_t direction,\n \t\t\t uint8_t queue, uint8_t msix_vector);\n \ndiff --git a/drivers/net/ngbe/ngbe_rxtx.c b/drivers/net/ngbe/ngbe_rxtx.c\nindex 84350075e8..54ae1802eb 100644\n--- a/drivers/net/ngbe/ngbe_rxtx.c\n+++ b/drivers/net/ngbe/ngbe_rxtx.c\n@@ -526,8 +526,32 @@ ngbe_dev_rx_init(struct rte_eth_dev *dev)\n void __rte_cold\n ngbe_dev_tx_init(struct rte_eth_dev *dev)\n {\n-\tRTE_SET_USED(dev);\n+\tstruct ngbe_hw *hw;\n+\tstruct ngbe_tx_queue *txq;\n+\tuint64_t bus_addr;\n+\tuint16_t i;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\thw = ngbe_dev_hw(dev);\n \n+\twr32m(hw, NGBE_SECTXCTL, NGBE_SECTXCTL_ODSA, NGBE_SECTXCTL_ODSA);\n+\twr32m(hw, NGBE_SECTXCTL, NGBE_SECTXCTL_XDSA, 0);\n+\n+\t/* Setup the Base and Length of the Tx Descriptor Rings */\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\n+\t\tbus_addr = txq->tx_ring_phys_addr;\n+\t\twr32(hw, NGBE_TXBAL(txq->reg_idx),\n+\t\t\t\t(uint32_t)(bus_addr & BIT_MASK32));\n+\t\twr32(hw, NGBE_TXBAH(txq->reg_idx),\n+\t\t\t\t(uint32_t)(bus_addr >> 32));\n+\t\twr32m(hw, NGBE_TXCFG(txq->reg_idx), NGBE_TXCFG_BUFLEN_MASK,\n+\t\t\tNGBE_TXCFG_BUFLEN(txq->nb_tx_desc));\n+\t\t/* Setup the HW Tx Head and TX Tail descriptor pointers */\n+\t\twr32(hw, NGBE_TXRP(txq->reg_idx), 0);\n+\t\twr32(hw, NGBE_TXWP(txq->reg_idx), 0);\n+\t}\n }\n \n /*\n@@ -536,8 +560,141 @@ ngbe_dev_tx_init(struct rte_eth_dev *dev)\n int __rte_cold\n ngbe_dev_rxtx_start(struct rte_eth_dev *dev)\n {\n-\tRTE_SET_USED(dev);\n+\tstruct ngbe_hw *hw;\n+\tstruct ngbe_tx_queue *txq;\n+\tuint32_t dmatxctl;\n+\tuint16_t i;\n+\tint ret = 0;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\thw = ngbe_dev_hw(dev);\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\t/* Setup Transmit Threshold Registers */\n+\t\twr32m(hw, NGBE_TXCFG(txq->reg_idx),\n+\t\t NGBE_TXCFG_HTHRESH_MASK |\n+\t\t NGBE_TXCFG_WTHRESH_MASK,\n+\t\t NGBE_TXCFG_HTHRESH(txq->hthresh) |\n+\t\t NGBE_TXCFG_WTHRESH(txq->wthresh));\n+\t}\n+\n+\tdmatxctl = rd32(hw, NGBE_DMATXCTRL);\n+\tdmatxctl |= NGBE_DMATXCTRL_ENA;\n+\twr32(hw, NGBE_DMATXCTRL, dmatxctl);\n+\n+\tfor (i = 0; i < dev->data->nb_tx_queues; i++) {\n+\t\ttxq = dev->data->tx_queues[i];\n+\t\tif (txq->tx_deferred_start == 0) {\n+\t\t\tret = ngbe_dev_tx_queue_start(dev, i);\n+\t\t\tif (ret < 0)\n+\t\t\t\treturn ret;\n+\t\t}\n+\t}\n \n \treturn -EINVAL;\n }\n \n+void\n+ngbe_dev_save_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id)\n+{\n+\tu32 *reg = &hw->q_tx_regs[tx_queue_id * 8];\n+\t*(reg++) = rd32(hw, NGBE_TXBAL(tx_queue_id));\n+\t*(reg++) = rd32(hw, NGBE_TXBAH(tx_queue_id));\n+\t*(reg++) = rd32(hw, NGBE_TXCFG(tx_queue_id));\n+}\n+\n+void\n+ngbe_dev_store_tx_queue(struct ngbe_hw *hw, uint16_t tx_queue_id)\n+{\n+\tu32 *reg = &hw->q_tx_regs[tx_queue_id * 8];\n+\twr32(hw, NGBE_TXBAL(tx_queue_id), *(reg++));\n+\twr32(hw, NGBE_TXBAH(tx_queue_id), *(reg++));\n+\twr32(hw, NGBE_TXCFG(tx_queue_id), *(reg++) & ~NGBE_TXCFG_ENA);\n+}\n+\n+/*\n+ * Start Transmit Units for specified queue.\n+ */\n+int __rte_cold\n+ngbe_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct ngbe_hw *hw = ngbe_dev_hw(dev);\n+\tstruct ngbe_tx_queue *txq;\n+\tuint32_t txdctl;\n+\tint poll_ms;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\twr32m(hw, NGBE_TXCFG(txq->reg_idx), NGBE_TXCFG_ENA, NGBE_TXCFG_ENA);\n+\n+\t/* Wait until Tx Enable ready */\n+\tpoll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n+\t\ttxdctl = rd32(hw, NGBE_TXCFG(txq->reg_idx));\n+\t} while (--poll_ms && !(txdctl & NGBE_TXCFG_ENA));\n+\tif (poll_ms == 0)\n+\t\tPMD_INIT_LOG(ERR, \"Could not enable Tx Queue %d\",\n+\t\t\t tx_queue_id);\n+\n+\trte_wmb();\n+\twr32(hw, NGBE_TXWP(txq->reg_idx), txq->tx_tail);\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * Stop Transmit Units for specified queue.\n+ */\n+int __rte_cold\n+ngbe_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n+{\n+\tstruct ngbe_hw *hw = ngbe_dev_hw(dev);\n+\tstruct ngbe_tx_queue *txq;\n+\tuint32_t txdctl;\n+\tuint32_t txtdh, txtdt;\n+\tint poll_ms;\n+\n+\tPMD_INIT_FUNC_TRACE();\n+\n+\ttxq = dev->data->tx_queues[tx_queue_id];\n+\n+\t/* Wait until Tx queue is empty */\n+\tpoll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_us(RTE_NGBE_WAIT_100_US);\n+\t\ttxtdh = rd32(hw, NGBE_TXRP(txq->reg_idx));\n+\t\ttxtdt = rd32(hw, NGBE_TXWP(txq->reg_idx));\n+\t} while (--poll_ms && (txtdh != txtdt));\n+\tif (poll_ms == 0)\n+\t\tPMD_INIT_LOG(ERR, \"Tx Queue %d is not empty when stopping.\",\n+\t\t\t tx_queue_id);\n+\n+\tngbe_dev_save_tx_queue(hw, txq->reg_idx);\n+\twr32m(hw, NGBE_TXCFG(txq->reg_idx), NGBE_TXCFG_ENA, 0);\n+\n+\t/* Wait until Tx Enable bit clear */\n+\tpoll_ms = RTE_NGBE_REGISTER_POLL_WAIT_10_MS;\n+\tdo {\n+\t\trte_delay_ms(1);\n+\t\ttxdctl = rd32(hw, NGBE_TXCFG(txq->reg_idx));\n+\t} while (--poll_ms && (txdctl & NGBE_TXCFG_ENA));\n+\tif (poll_ms == 0)\n+\t\tPMD_INIT_LOG(ERR, \"Could not disable Tx Queue %d\",\n+\t\t\t tx_queue_id);\n+\n+\trte_delay_us(RTE_NGBE_WAIT_100_US);\n+\tngbe_dev_store_tx_queue(hw, txq->reg_idx);\n+\n+\tif (txq->ops != NULL) {\n+\t\ttxq->ops->release_mbufs(txq);\n+\t\ttxq->ops->reset(txq);\n+\t}\n+\tdev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;\n+\n+\treturn 0;\n+}\n+\ndiff --git a/drivers/net/ngbe/ngbe_rxtx.h b/drivers/net/ngbe/ngbe_rxtx.h\nindex 3b567b767b..58487caa95 100644\n--- a/drivers/net/ngbe/ngbe_rxtx.h\n+++ b/drivers/net/ngbe/ngbe_rxtx.h\n@@ -73,6 +73,9 @@ struct ngbe_tx_desc {\n #define RX_RING_SZ ((NGBE_RING_DESC_MAX + RTE_PMD_NGBE_RX_MAX_BURST) * \\\n \t\t sizeof(struct ngbe_rx_desc))\n \n+#define RTE_NGBE_REGISTER_POLL_WAIT_10_MS 10\n+#define RTE_NGBE_WAIT_100_US 100\n+\n #define NGBE_TX_MAX_SEG 40\n \n #ifndef DEFAULT_TX_FREE_THRESH\n", "prefixes": [ "v7", "15/19" ] }