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GET /api/patches/96102/?format=api
{ "id": 96102, "url": "http://patchwork.dpdk.org/api/patches/96102/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-9-suanmingm@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210720130944.5407-9-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210720130944.5407-9-suanmingm@nvidia.com", "date": "2021-07-20T13:09:37", "name": "[v9,08/15] crypto/mlx5: add keytag devarg", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "43ce6e80f8b310089b1b221e777dea723e87e8cb", "submitter": { "id": 1887, "url": "http://patchwork.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 6690, "url": "http://patchwork.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210720130944.5407-9-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17912, "url": "http://patchwork.dpdk.org/api/series/17912/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=17912", "date": "2021-07-20T13:09:29", "name": "drivers: introduce mlx5 crypto PMD", "version": 9, "mbox": "http://patchwork.dpdk.org/series/17912/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96102/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96102/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 02BD9A0C48;\n\tTue, 20 Jul 2021 15:11:10 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 11BA84115F;\n\tTue, 20 Jul 2021 15:10:23 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2073.outbound.protection.outlook.com [40.107.236.73])\n by mails.dpdk.org (Postfix) with ESMTP id 3CE6941141\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<shirik@nvidia.com>, <gakhil@marvell.com>", "CC": "<matan@nvidia.com>, <david.marchand@redhat.com>, <dev@dpdk.org>", "Date": "Tue, 20 Jul 2021 16:09:37 +0300", "Message-ID": "<20210720130944.5407-9-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210720130944.5407-1-suanmingm@nvidia.com>", "References": "<20210408204849.9543-1-shirik@nvidia.com>\n <20210720130944.5407-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "3ae6f90e-8223-46eb-4ed0-08d94b7fb900", "X-MS-TrafficTypeDiagnostic": "CH2PR12MB3654:", "X-Microsoft-Antispam-PRVS": "\n <CH2PR12MB36546BAF21D55EF141CBEE7CC1E29@CH2PR12MB3654.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:139;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n z0R7DyK9KsUCqZaq4ek+F+ofgoPCMKYL7nSM0TR73zwly8T6fhe/ZqxxASyZFyHqyRHWa1+o6ERSKOh+V9Y2aAQFKCW31JwUC8ew7JCeKO589v3+3+d39ECah04vKdtUoy2psfEburZay8bTnQLZz++y7p4l+TbGeJLlRwMqnXP0bZRauJjg71QLCEoW62vCswd7OXSwi+CprUwDe/dyYI1P55bsYWxV6/oNy01hzJLPcuK4r1t+17Ma/hS7uiXrka9npeaiwfuG6MFLx/X5NOekgKhGOENghDpwrGFeeIdmSPyUH0RPmU0GR/z3OySAoF0jPWTgD5sAlTLBZJFYe4FqwxmdWyJ5oE5nQESHRvJrG+xfOz0+WnFKlST81hhpOXUdX36jrJUNxcYF73MQHHF147SzXo5jROWHhQ7m1nG9tiNND/bzywOINzUpg4MiCUM9j1lMKAcwjqXAxftemr0q47mRTq8FBgVOQqcKYqB+lZFj9I4C77WQzVnQyHFLLPcEe7n0RswIlK73Asgc1wVqAWZwd9X7kH2C1OWY0Xk4ZfGzeB9dyBTWMfXeFM2G17nrgam15x4wycDopF0Oq1W4qP9quACstg/nNAEEGvEEAztSMBkOM1RZ7lcAyv2/YzhGiMeIBhqoTb9LVAKVIFjeI7syeoUGzfxk3MYOujcmlqYkP5hrzDI+L50G30ybb58E3HRZMtTAKAYDJaGcpA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(136003)(396003)(376002)(39860400002)(346002)(36840700001)(46966006)(356005)(426003)(1076003)(7636003)(36860700001)(2906002)(8936002)(55016002)(6666004)(478600001)(70586007)(336012)(82740400003)(8676002)(4326008)(36906005)(83380400001)(110136005)(47076005)(16526019)(86362001)(316002)(82310400003)(70206006)(186003)(36756003)(2616005)(7696005)(5660300002)(26005)(6286002)(54906003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "20 Jul 2021 13:10:18.5381 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 3ae6f90e-8223-46eb-4ed0-08d94b7fb900", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "CH2PR12MB3654", "Subject": "[dpdk-dev] [PATCH v9 08/15] crypto/mlx5: add keytag devarg", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "A keytag is a piece of data encrypted together with a DEK.\n\nWhen a DEK is referenced by an MKEY.bsf through its index, the keytag is\nalso supplied in the BSF as plaintext. The HW will decrypt the DEK (and\nthe attached keytag) and will fail the operation if the keytags don't\nmatch.\n\nThis commit adds the configuration of the keytag with devargs.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nSigned-off-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/cryptodevs/mlx5.rst | 7 +++++\n drivers/crypto/mlx5/mlx5_crypto.c | 50 +++++++++++++++++--------------\n drivers/crypto/mlx5/mlx5_crypto.h | 3 +-\n 3 files changed, 37 insertions(+), 23 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nindex c316bfdc58..5b874824db 100644\n--- a/doc/guides/cryptodevs/mlx5.rst\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -52,6 +52,9 @@ wrapping.\n The credential and the AES-XTS keys should be provided to the hardware, as ciphertext\n encrypted by the KEK.\n \n+A keytag (64 bits) should be appended to the AES-XTS keys (before wrapping),\n+and will be validated when the hardware attempts to access it.\n+\n When crypto engines are defined to work in wrapped import method, they come out\n of the factory in Commissioning mode, and thus, cannot be used for crypto operations\n yet. A dedicated tool is used for changing the mode from Commissioning to\n@@ -113,6 +116,10 @@ Driver options\n The identifier of the credential, default value is 0 represents the operational\n register credential.\n \n+- ``keytag`` parameter [int]\n+\n+ The plaintext of the keytag appanded to the AES-XTS keys, default value is 0.\n+\n \n Supported NICs\n --------------\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex a16578b3af..b24e68532c 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -498,56 +498,52 @@ mlx5_crypto_args_check_handler(const char *key, const char *val, void *opaque)\n \t\tattr->session_import_kek_ptr = (uint32_t)tmp;\n \telse if (strcmp(key, \"credential_id\") == 0)\n \t\tattr->credential_pointer = (uint32_t)tmp;\n+\telse if (strcmp(key, \"keytag\") == 0)\n+\t\tdevarg_prms->keytag = tmp;\n \telse\n \t\tDRV_LOG(WARNING, \"Invalid key %s.\", key);\n \treturn 0;\n }\n \n-static struct mlx5_devx_obj *\n-mlx5_crypto_config_login(struct rte_devargs *devargs,\n-\t\t\t struct ibv_context *ctx)\n+static int\n+mlx5_crypto_parse_devargs(struct rte_devargs *devargs,\n+\t\t\t struct mlx5_crypto_devarg_params *devarg_prms)\n {\n-\t/*\n-\t * Set credential pointer and session import KEK pointer to a default\n-\t * value of 0.\n-\t */\n-\tstruct mlx5_crypto_devarg_params login = {\n-\t\t\t.login_devarg = false,\n-\t\t\t.login_attr = {\n-\t\t\t\t\t.credential_pointer = 0,\n-\t\t\t\t\t.session_import_kek_ptr = 0,\n-\t\t\t}\n-\t};\n+\tstruct mlx5_devx_crypto_login_attr *attr = &devarg_prms->login_attr;\n \tstruct rte_kvargs *kvlist;\n \n+\t/* Default values. */\n+\tattr->credential_pointer = 0;\n+\tattr->session_import_kek_ptr = 0;\n+\tdevarg_prms->keytag = 0;\n \tif (devargs == NULL) {\n \t\tDRV_LOG(ERR,\n \t\"No login devargs in order to enable crypto operations in the device.\");\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n \tkvlist = rte_kvargs_parse(devargs->args, NULL);\n \tif (kvlist == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to parse devargs.\");\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n \tif (rte_kvargs_process(kvlist, NULL, mlx5_crypto_args_check_handler,\n-\t\t\t &login) != 0) {\n+\t\t\t devarg_prms) != 0) {\n \t\tDRV_LOG(ERR, \"Devargs handler function Failed.\");\n \t\trte_kvargs_free(kvlist);\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n \trte_kvargs_free(kvlist);\n-\tif (login.login_devarg == false) {\n+\tif (devarg_prms->login_devarg == false) {\n \t\tDRV_LOG(ERR,\n \t\"No login credential devarg in order to enable crypto operations \"\n \t\"in the device.\");\n \t\trte_errno = EINVAL;\n-\t\treturn NULL;\n+\t\treturn -1;\n \t}\n-\treturn mlx5_devx_cmd_create_crypto_login_obj(ctx, &login.login_attr);\n+\treturn 0;\n }\n \n /**\n@@ -607,6 +603,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \tstruct ibv_context *ctx;\n \tstruct mlx5_devx_obj *login;\n \tstruct mlx5_crypto_priv *priv;\n+\tstruct mlx5_crypto_devarg_params devarg_prms = { 0 };\n \tstruct mlx5_hca_attr attr = { 0 };\n \tstruct rte_cryptodev_pmd_init_params init_params = {\n \t\t.name = \"\",\n@@ -615,6 +612,8 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\t.max_nb_queue_pairs =\n \t\t\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,\n \t};\n+\tint ret;\n+\n \tRTE_SET_USED(pci_drv);\n \tif (rte_eal_process_type() != RTE_PROC_PRIMARY) {\n \t\tDRV_LOG(ERR, \"Non-primary process type is not supported.\");\n@@ -644,7 +643,13 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\trte_errno = ENOTSUP;\n \t\treturn -ENOTSUP;\n \t}\n-\tlogin = mlx5_crypto_config_login(pci_dev->device.devargs, ctx);\n+\tret = mlx5_crypto_parse_devargs(pci_dev->device.devargs, &devarg_prms);\n+\tif (ret) {\n+\t\tDRV_LOG(ERR, \"Failed to parse devargs.\");\n+\t\treturn -rte_errno;\n+\t}\n+\tlogin = mlx5_devx_cmd_create_crypto_login_obj(ctx,\n+\t\t\t\t\t\t &devarg_prms.login_attr);\n \tif (login == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to configure login.\");\n \t\treturn -rte_errno;\n@@ -684,6 +689,7 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t}\n \tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n \tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n+\tpriv->keytag = rte_cpu_to_be_64(devarg_prms.keytag);\n \t/* Register callback function for global shared MR cache management. */\n \tif (TAILQ_EMPTY(&mlx5_crypto_priv_list))\n \t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 9df982b23e..a513e9ee36 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -30,6 +30,7 @@ struct mlx5_crypto_priv {\n \tstruct rte_cryptodev_config dev_config;\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n \tstruct mlx5_devx_obj *login_obj;\n+\tuint64_t keytag;\n };\n \n struct mlx5_crypto_qp {\n@@ -49,10 +50,10 @@ struct mlx5_crypto_dek {\n \tbool size_is_48; /* Whether the key\\data size is 48 bytes or not. */\n } __rte_cache_aligned;\n \n-\n struct mlx5_crypto_devarg_params {\n \tbool login_devarg;\n \tstruct mlx5_devx_crypto_login_attr login_attr;\n+\tuint64_t keytag;\n };\n \n int\n", "prefixes": [ "v9", "08/15" ] }