Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/96413/?format=api
{ "id": 96413, "url": "http://patchwork.dpdk.org/api/patches/96413/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210729140020.1077946-2-dkozlyuk@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210729140020.1077946-2-dkozlyuk@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210729140020.1077946-2-dkozlyuk@nvidia.com", "date": "2021-07-29T14:00:18", "name": "[v2,1/3] net/mlx5: discover max flow priority using DevX", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "61478a482d5787905ce704db97fa228d22917ac3", "submitter": { "id": 2248, "url": "http://patchwork.dpdk.org/api/people/2248/?format=api", "name": "Dmitry Kozlyuk", "email": "dkozlyuk@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210729140020.1077946-2-dkozlyuk@nvidia.com/mbox/", "series": [ { "id": 18065, "url": "http://patchwork.dpdk.org/api/series/18065/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18065", "date": "2021-07-29T14:00:17", "name": "net/mlx5: keep indirect actions across port restart", "version": 2, "mbox": "http://patchwork.dpdk.org/series/18065/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96413/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96413/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3338CA034F;\n\tThu, 29 Jul 2021 16:00:46 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 167E9410F0;\n\tThu, 29 Jul 2021 16:00:43 +0200 (CEST)", "from NAM10-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam10on2053.outbound.protection.outlook.com [40.107.94.53])\n by mails.dpdk.org (Postfix) with ESMTP id BEB71410F0;\n Thu, 29 Jul 2021 16:00:41 +0200 (CEST)", "from DM6PR02CA0069.namprd02.prod.outlook.com (2603:10b6:5:177::46)\n by MN2PR12MB3520.namprd12.prod.outlook.com (2603:10b6:208:100::28) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.20; Thu, 29 Jul\n 2021 14:00:39 +0000", "from DM6NAM11FT056.eop-nam11.prod.protection.outlook.com\n (2603:10b6:5:177:cafe::df) by DM6PR02CA0069.outlook.office365.com\n (2603:10b6:5:177::46) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4373.18 via Frontend\n Transport; Thu, 29 Jul 2021 14:00:39 +0000", "from mail.nvidia.com (216.228.112.34) by\n DM6NAM11FT056.mail.protection.outlook.com (10.13.173.99) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4373.18 via Frontend Transport; Thu, 29 Jul 2021 14:00:38 +0000", "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 29 Jul\n 2021 14:00:35 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=DQShoTXNLf/28yekoX3F+k9m27lMr7XVdeyVndbHbu7Fs4LhFUo4T/zf7T46ljSqj+pcZY7Ym/Ve1UnDryvMyszNXszeAsYcNc04cKnB2fRYO2iqZ9GsfVi/FgkBNDKuFxVX39nFGPBO3xRaRvWcXARHIexIoldYGpA1asUec89wuQofNjbN2K7hlIi0MToAuwSf2Uue+8SK1vg9wJ/6RKEsCpBcM+piwrkMKHr7bFnYXOdUwsAbtuD4T5MrYUo/uUM4LOORJj18lx5o6spXCdWtgB+CbxSNGeps5zkuqhsIwFMnvk/8h/eSQ0iHrGHjy+LoRRgM/wocMhW0Q8EwHw==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=G/P4iMfgLoJcEn5eXVMArk/dGucRgUDt978ZOlzUrvU=;\n b=Or27jIXqplY8dWrJCBNEm59UFnMvref92qHudABnjDUxJU7To7VG9waXzqf8sN9GPnlmMBUTJ1i6HE84wAf5MDeiBNK+kZxmxSk4SlZB0rtVu6THQ2gBNujsgxWI9D1RO24JoEOqSPkjg4wQge/9TIswTkQMOArI8PpfGWL7ZW9XGjrmae4V1ZMK4DLS5PDrmlNFsuGgOMdLCtRSOgj2HG1WNtSaE1axlfgr4plFfx0N6nrDC/d1G1057gD/0zOr0EwW8Z5tmrqSpnrOy791X0Adcl7BM3oMG4KtKsrvk1F+cRsQB1VfF0AqLF4x0VE2eSOqwKwEEgW6UwsRSrBCLg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=oktetlabs.ru smtp.mailfrom=nvidia.com;\n dmarc=pass (p=quarantine sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=G/P4iMfgLoJcEn5eXVMArk/dGucRgUDt978ZOlzUrvU=;\n b=Cj3i4Fwu1PK7ZVSiqFihBeCuZ+cjhKHUCCm7CzSsHY+Kamfi8/5ubkW6ceQEHI5ds3mXNnLMTz3SCoa1KvpmxPqmuHfZ4FricaqmkV0pVPEsS62t/SRLdwcUkbxPV8bH4dSetoeG4ths4diYuqzuP9KNRmmyeMZ5LqsGikrsG0TJK36KCKk4pJHyl9nms57t1KTbl1ehiVjrgcoWe4P/stdQ4n76t2rgXtUVk3wTWtv8L0g7tUEm9dMKuXOPxKaw9Q3oxf9jlVW7/tUQwfrIm525YDUWNqaOYim9Lkd8fJCzzFR65btYO6XEN1rrhBLqPfAJqjHARkjti3cTlbOwTg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; oktetlabs.ru; dkim=none (message not signed)\n header.d=none;oktetlabs.ru; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Dmitry Kozlyuk <dkozlyuk@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "David Marchand <david.marchand@redhat.com>, Andrew Rybchenko\n <andrew.rybchenko@oktetlabs.ru>, Ori Kam <orika@nvidia.com>,\n <stable@dpdk.org>, Matan Azrad <matan@nvidia.com>, Shahaf Shuler\n <shahafs@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "Date": "Thu, 29 Jul 2021 17:00:18 +0300", "Message-ID": "<20210729140020.1077946-2-dkozlyuk@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210729140020.1077946-1-dkozlyuk@nvidia.com>", "References": "<20210727073121.895620-1-dkozlyuk@nvidia.com>\n <20210729140020.1077946-1-dkozlyuk@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "a3f718f3-9b75-4162-dcab-08d952993f17", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB3520:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB3520B204662E05897BE0DF25B9EB9@MN2PR12MB3520.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:1751;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n HybUi9QN2BQG45vlSvcM4WfKYiouEJzvnXdTbbqWR3HWeZDqHxUvvoJJx2KPkKbyQ4YkbokA0vlqFlznpowx6rv7MTfP92tcBw9QU4wg1UyZ9cCIEHqtr9kpKbzD3lxn84J10TtK19oy69DU827KDsE8K7MUHJYb22zGj2StrQqc9wZMpRomN++b4XVmVsnqPkqLhrhCdvpxAzdUJhDceNV4boZ9nKDfHLTS8w+Hdv7hWboBd2+sp7ape5cnyZYnCUQRehTtjG8DOVIo22lXQA2VzD+ZMwP19Acb+IzGPFk2hJF9funZifjKtVy7Jb5A0x/TR03+ogusnHMmAiCuWSdnFKcHYCSBGCHR+kRmhmE+dUKDwWrf0wKhBkkttWmyLFowGumkCsTvWNpEi66cIjGsozSklYl7p178ryMQxH9rKdnzGsURDEvLUTa/7/tp+rfzs3pzJyKH0VZoYUs3RMUnGf88xjVj6CA8pX/hXBGmI+gzMt8gBQovOGzOzmNmy7neEDJef+r8jxjtPuVMVTC7Em1Tb20pqi6C4PpgpS7qE6zQqZE4nxUz73EFeVwfFqauLbDOo12rBa5bc9AtbnBH9nJ3SQra2fw/6gMPmuvVZ/d/7DNwUuUp9Kcy13G7Ufyu9cSz435SMB3SoS8ChYXYe9/m8ZMqhzFrm5nI7atVG+iDsos9EU90J5o8vN0GMdaQySOp2F5mJkoAoO+QIQ==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(346002)(136003)(376002)(39860400002)(36840700001)(46966006)(336012)(86362001)(36860700001)(70586007)(70206006)(7696005)(1076003)(107886003)(36756003)(82310400003)(6916009)(83380400001)(16526019)(316002)(47076005)(8676002)(8936002)(2616005)(82740400003)(2906002)(6286002)(186003)(26005)(478600001)(356005)(36906005)(54906003)(5660300002)(4326008)(426003)(55016002)(7636003)(30864003)(6666004);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "29 Jul 2021 14:00:38.9129 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a3f718f3-9b75-4162-dcab-08d952993f17", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n DM6NAM11FT056.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB3520", "Subject": "[dpdk-dev] [PATCH v2 1/3] net/mlx5: discover max flow priority\n using DevX", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Maximum available flow priority was discovered using Verbs API\nregardless of the selected flow engine. This required some Verbs\nobjects to be initialized in order to use DevX engine. Make priority\ndiscovery an engine method and implement it for DevX using its API.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Dmitry Kozlyuk <dkozlyuk@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/linux/mlx5_os.c | 1 -\n drivers/net/mlx5/mlx5_flow.c | 98 +++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow.h | 4 ++\n drivers/net/mlx5/mlx5_flow_dv.c | 103 +++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_flow_verbs.c | 77 +++------------------\n 5 files changed, 215 insertions(+), 68 deletions(-)", "diff": "diff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 4712bd6f9b..671dfface9 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -1781,7 +1781,6 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tpriv->drop_queue.hrxq = mlx5_drop_action_create(eth_dev);\n \tif (!priv->drop_queue.hrxq)\n \t\tgoto error;\n-\t/* Supported Verbs flow priority number detection. */\n \terr = mlx5_flow_discover_priorities(eth_dev);\n \tif (err < 0) {\n \t\terr = -err;\ndiff --git a/drivers/net/mlx5/mlx5_flow.c b/drivers/net/mlx5/mlx5_flow.c\nindex a3fdce685e..e8d2678877 100644\n--- a/drivers/net/mlx5/mlx5_flow.c\n+++ b/drivers/net/mlx5/mlx5_flow.c\n@@ -9362,3 +9362,101 @@ mlx5_dbg__print_pattern(const struct rte_flow_item *item)\n \t}\n \tprintf(\"END\\n\");\n }\n+\n+/* Map of Verbs to Flow priority with 8 Verbs priorities. */\n+static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = {\n+\t{ 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 },\n+};\n+\n+/* Map of Verbs to Flow priority with 16 Verbs priorities. */\n+static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = {\n+\t{ 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 },\n+\t{ 9, 10, 11 }, { 12, 13, 14 },\n+};\n+\n+/**\n+ * Discover the number of available flow priorities.\n+ *\n+ * @param dev\n+ * Ethernet device.\n+ *\n+ * @return\n+ * On success, number of available flow priorities.\n+ * On failure, a negative errno-style code and rte_errno is set.\n+ */\n+int\n+mlx5_flow_discover_priorities(struct rte_eth_dev *dev)\n+{\n+\tstatic const uint16_t vprio[] = {8, 16};\n+\tconst struct mlx5_priv *priv = dev->data->dev_private;\n+\tconst struct mlx5_flow_driver_ops *fops;\n+\tenum mlx5_flow_drv_type type;\n+\tint ret;\n+\n+\ttype = mlx5_flow_os_get_type();\n+\tif (type == MLX5_FLOW_TYPE_MAX) {\n+\t\ttype = MLX5_FLOW_TYPE_VERBS;\n+\t\tif (priv->config.devx && priv->config.dv_flow_en)\n+\t\t\ttype = MLX5_FLOW_TYPE_DV;\n+\t}\n+\tfops = flow_get_drv_ops(type);\n+\tif (fops->discover_priorities == NULL) {\n+\t\tDRV_LOG(ERR, \"Priority discovery not supported\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -rte_errno;\n+\t}\n+\tret = fops->discover_priorities(dev, vprio, RTE_DIM(vprio));\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tswitch (ret) {\n+\tcase 8:\n+\t\tret = RTE_DIM(priority_map_3);\n+\t\tbreak;\n+\tcase 16:\n+\t\tret = RTE_DIM(priority_map_5);\n+\t\tbreak;\n+\tdefault:\n+\t\trte_errno = ENOTSUP;\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"port %u maximum priority: %d expected 8/16\",\n+\t\t\tdev->data->port_id, ret);\n+\t\treturn -rte_errno;\n+\t}\n+\tDRV_LOG(INFO, \"port %u supported flow priorities:\"\n+\t\t\" 0-%d for ingress or egress root table,\"\n+\t\t\" 0-%d for non-root table or transfer root table.\",\n+\t\tdev->data->port_id, ret - 2,\n+\t\tMLX5_NON_ROOT_FLOW_MAX_PRIO - 1);\n+\treturn ret;\n+}\n+\n+/**\n+ * Adjust flow priority based on the highest layer and the request priority.\n+ *\n+ * @param[in] dev\n+ * Pointer to the Ethernet device structure.\n+ * @param[in] priority\n+ * The rule base priority.\n+ * @param[in] subpriority\n+ * The priority based on the items.\n+ *\n+ * @return\n+ * The new priority.\n+ */\n+uint32_t\n+mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n+\t\t\t uint32_t subpriority)\n+{\n+\tuint32_t res = 0;\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\n+\tswitch (priv->config.flow_prio) {\n+\tcase RTE_DIM(priority_map_3):\n+\t\tres = priority_map_3[priority][subpriority];\n+\t\tbreak;\n+\tcase RTE_DIM(priority_map_5):\n+\t\tres = priority_map_5[priority][subpriority];\n+\t\tbreak;\n+\t}\n+\treturn res;\n+}\ndiff --git a/drivers/net/mlx5/mlx5_flow.h b/drivers/net/mlx5/mlx5_flow.h\nindex 3724293d26..da39eeb596 100644\n--- a/drivers/net/mlx5/mlx5_flow.h\n+++ b/drivers/net/mlx5/mlx5_flow.h\n@@ -1229,6 +1229,9 @@ typedef int (*mlx5_flow_create_def_policy_t)\n \t\t\t(struct rte_eth_dev *dev);\n typedef void (*mlx5_flow_destroy_def_policy_t)\n \t\t\t(struct rte_eth_dev *dev);\n+typedef int (*mlx5_flow_discover_priorities_t)\n+\t\t\t(struct rte_eth_dev *dev,\n+\t\t\t const uint16_t *vprio, int vprio_n);\n \n struct mlx5_flow_driver_ops {\n \tmlx5_flow_validate_t validate;\n@@ -1263,6 +1266,7 @@ struct mlx5_flow_driver_ops {\n \tmlx5_flow_action_update_t action_update;\n \tmlx5_flow_action_query_t action_query;\n \tmlx5_flow_sync_domain_t sync_domain;\n+\tmlx5_flow_discover_priorities_t discover_priorities;\n };\n \n /* mlx5_flow.c */\ndiff --git a/drivers/net/mlx5/mlx5_flow_dv.c b/drivers/net/mlx5/mlx5_flow_dv.c\nindex 736227bc0c..b31445b51e 100644\n--- a/drivers/net/mlx5/mlx5_flow_dv.c\n+++ b/drivers/net/mlx5/mlx5_flow_dv.c\n@@ -17828,6 +17828,108 @@ flow_dv_sync_domain(struct rte_eth_dev *dev, uint32_t domains, uint32_t flags)\n \treturn 0;\n }\n \n+/**\n+ * Discover the number of available flow priorities\n+ * by trying to create a flow with the highest priority value\n+ * for each possible number.\n+ *\n+ * @param[in] dev\n+ * Ethernet device.\n+ * @param[in] vprio\n+ * List of possible number of available priorities.\n+ * @param[in] vprio_n\n+ * Size of @p vprio array.\n+ * @return\n+ * On success, number of available flow priorities.\n+ * On failure, a negative errno-style code and rte_errno is set.\n+ */\n+static int\n+flow_dv_discover_priorities(struct rte_eth_dev *dev,\n+\t\t\t const uint16_t *vprio, int vprio_n)\n+{\n+\tstruct mlx5_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_indexed_pool *pool = priv->sh->ipool[MLX5_IPOOL_MLX5_FLOW];\n+\tstruct rte_flow_item_eth eth;\n+\tstruct rte_flow_item item = {\n+\t\t.type = RTE_FLOW_ITEM_TYPE_ETH,\n+\t\t.spec = ð,\n+\t\t.mask = ð,\n+\t};\n+\tstruct mlx5_flow_dv_matcher matcher = {\n+\t\t.mask = {\n+\t\t\t.size = sizeof(matcher.mask.buf),\n+\t\t},\n+\t};\n+\tunion mlx5_flow_tbl_key tbl_key;\n+\tstruct mlx5_flow flow;\n+\tvoid *action;\n+\tstruct rte_flow_error error;\n+\tuint8_t misc_mask;\n+\tint i, err, ret = -ENOTSUP;\n+\n+\t/*\n+\t * Prepare a flow with a catch-all pattern and a drop action.\n+\t * Use drop queue, because shared drop action may be unavailable.\n+\t */\n+\taction = priv->drop_queue.hrxq->action;\n+\tif (action == NULL) {\n+\t\tDRV_LOG(ERR, \"Priority discovery requires a drop action\");\n+\t\trte_errno = ENOTSUP;\n+\t\treturn -rte_errno;\n+\t}\n+\tmemset(&flow, 0, sizeof(flow));\n+\tflow.handle = mlx5_ipool_zmalloc(pool, &flow.handle_idx);\n+\tif (flow.handle == NULL) {\n+\t\tDRV_LOG(ERR, \"Cannot create flow handle\");\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tflow.ingress = true;\n+\tflow.dv.value.size = MLX5_ST_SZ_BYTES(fte_match_param);\n+\tflow.dv.actions[0] = action;\n+\tflow.dv.actions_n = 1;\n+\tmemset(ð, 0, sizeof(eth));\n+\tflow_dv_translate_item_eth(matcher.mask.buf, flow.dv.value.buf,\n+\t\t\t\t &item, /* inner */ false, /* group */ 0);\n+\tmatcher.crc = rte_raw_cksum(matcher.mask.buf, matcher.mask.size);\n+\tfor (i = 0; i < vprio_n; i++) {\n+\t\t/* Configure the next proposed maximum priority. */\n+\t\tmatcher.priority = vprio[i] - 1;\n+\t\tmemset(&tbl_key, 0, sizeof(tbl_key));\n+\t\terr = flow_dv_matcher_register(dev, &matcher, &tbl_key, &flow,\n+\t\t\t\t\t /* tunnel */ NULL,\n+\t\t\t\t\t /* group */ 0,\n+\t\t\t\t\t &error);\n+\t\tif (err != 0) {\n+\t\t\t/* This action is pure SW and must always succeed. */\n+\t\t\tDRV_LOG(ERR, \"Cannot register matcher\");\n+\t\t\tret = -rte_errno;\n+\t\t\tbreak;\n+\t\t}\n+\t\t/* Try to apply the flow to HW. */\n+\t\tmisc_mask = flow_dv_matcher_enable(flow.dv.value.buf);\n+\t\t__flow_dv_adjust_buf_size(&flow.dv.value.size, misc_mask);\n+\t\terr = mlx5_flow_os_create_flow\n+\t\t\t\t(flow.handle->dvh.matcher->matcher_object,\n+\t\t\t\t (void *)&flow.dv.value, flow.dv.actions_n,\n+\t\t\t\t flow.dv.actions, &flow.handle->drv_flow);\n+\t\tif (err == 0) {\n+\t\t\tclaim_zero(mlx5_flow_os_destroy_flow\n+\t\t\t\t\t\t(flow.handle->drv_flow));\n+\t\t\tflow.handle->drv_flow = NULL;\n+\t\t}\n+\t\tclaim_zero(flow_dv_matcher_release(dev, flow.handle));\n+\t\tif (err != 0)\n+\t\t\tbreak;\n+\t\tret = vprio[i];\n+\t}\n+\tmlx5_ipool_free(pool, flow.handle_idx);\n+\t/* Set rte_errno if no expected priority value matched. */\n+\tif (ret < 0)\n+\t\trte_errno = -ret;\n+\treturn ret;\n+}\n+\n const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {\n \t.validate = flow_dv_validate,\n \t.prepare = flow_dv_prepare,\n@@ -17861,6 +17963,7 @@ const struct mlx5_flow_driver_ops mlx5_flow_dv_drv_ops = {\n \t.action_update = flow_dv_action_update,\n \t.action_query = flow_dv_action_query,\n \t.sync_domain = flow_dv_sync_domain,\n+\t.discover_priorities = flow_dv_discover_priorities,\n };\n \n #endif /* HAVE_IBV_FLOW_DV_SUPPORT */\ndiff --git a/drivers/net/mlx5/mlx5_flow_verbs.c b/drivers/net/mlx5/mlx5_flow_verbs.c\nindex 7b3d0b320d..c87b257b37 100644\n--- a/drivers/net/mlx5/mlx5_flow_verbs.c\n+++ b/drivers/net/mlx5/mlx5_flow_verbs.c\n@@ -28,17 +28,6 @@\n #define VERBS_SPEC_INNER(item_flags) \\\n \t(!!((item_flags) & MLX5_FLOW_LAYER_TUNNEL) ? IBV_FLOW_SPEC_INNER : 0)\n \n-/* Map of Verbs to Flow priority with 8 Verbs priorities. */\n-static const uint32_t priority_map_3[][MLX5_PRIORITY_MAP_MAX] = {\n-\t{ 0, 1, 2 }, { 2, 3, 4 }, { 5, 6, 7 },\n-};\n-\n-/* Map of Verbs to Flow priority with 16 Verbs priorities. */\n-static const uint32_t priority_map_5[][MLX5_PRIORITY_MAP_MAX] = {\n-\t{ 0, 1, 2 }, { 3, 4, 5 }, { 6, 7, 8 },\n-\t{ 9, 10, 11 }, { 12, 13, 14 },\n-};\n-\n /* Verbs specification header. */\n struct ibv_spec_header {\n \tenum ibv_flow_spec_type type;\n@@ -50,13 +39,17 @@ struct ibv_spec_header {\n *\n * @param[in] dev\n * Pointer to the Ethernet device structure.\n- *\n+ * @param[in] vprio\n+ * Expected result variants.\n+ * @param[in] vprio_n\n+ * Number of entries in @p vprio array.\n * @return\n- * number of supported flow priority on success, a negative errno\n+ * Number of supported flow priority on success, a negative errno\n * value otherwise and rte_errno is set.\n */\n-int\n-mlx5_flow_discover_priorities(struct rte_eth_dev *dev)\n+static int\n+flow_verbs_discover_priorities(struct rte_eth_dev *dev,\n+\t\t\t const uint16_t *vprio, int vprio_n)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n \tstruct {\n@@ -79,7 +72,6 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev)\n \t};\n \tstruct ibv_flow *flow;\n \tstruct mlx5_hrxq *drop = priv->drop_queue.hrxq;\n-\tuint16_t vprio[] = { 8, 16 };\n \tint i;\n \tint priority = 0;\n \n@@ -87,7 +79,7 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev)\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\tfor (i = 0; i != RTE_DIM(vprio); i++) {\n+\tfor (i = 0; i != vprio_n; i++) {\n \t\tflow_attr.attr.priority = vprio[i] - 1;\n \t\tflow = mlx5_glue->create_flow(drop->qp, &flow_attr.attr);\n \t\tif (!flow)\n@@ -95,59 +87,9 @@ mlx5_flow_discover_priorities(struct rte_eth_dev *dev)\n \t\tclaim_zero(mlx5_glue->destroy_flow(flow));\n \t\tpriority = vprio[i];\n \t}\n-\tswitch (priority) {\n-\tcase 8:\n-\t\tpriority = RTE_DIM(priority_map_3);\n-\t\tbreak;\n-\tcase 16:\n-\t\tpriority = RTE_DIM(priority_map_5);\n-\t\tbreak;\n-\tdefault:\n-\t\trte_errno = ENOTSUP;\n-\t\tDRV_LOG(ERR,\n-\t\t\t\"port %u verbs maximum priority: %d expected 8/16\",\n-\t\t\tdev->data->port_id, priority);\n-\t\treturn -rte_errno;\n-\t}\n-\tDRV_LOG(INFO, \"port %u supported flow priorities:\"\n-\t\t\" 0-%d for ingress or egress root table,\"\n-\t\t\" 0-%d for non-root table or transfer root table.\",\n-\t\tdev->data->port_id, priority - 2,\n-\t\tMLX5_NON_ROOT_FLOW_MAX_PRIO - 1);\n \treturn priority;\n }\n \n-/**\n- * Adjust flow priority based on the highest layer and the request priority.\n- *\n- * @param[in] dev\n- * Pointer to the Ethernet device structure.\n- * @param[in] priority\n- * The rule base priority.\n- * @param[in] subpriority\n- * The priority based on the items.\n- *\n- * @return\n- * The new priority.\n- */\n-uint32_t\n-mlx5_flow_adjust_priority(struct rte_eth_dev *dev, int32_t priority,\n-\t\t\t\t uint32_t subpriority)\n-{\n-\tuint32_t res = 0;\n-\tstruct mlx5_priv *priv = dev->data->dev_private;\n-\n-\tswitch (priv->config.flow_prio) {\n-\tcase RTE_DIM(priority_map_3):\n-\t\tres = priority_map_3[priority][subpriority];\n-\t\tbreak;\n-\tcase RTE_DIM(priority_map_5):\n-\t\tres = priority_map_5[priority][subpriority];\n-\t\tbreak;\n-\t}\n-\treturn res;\n-}\n-\n /**\n * Get Verbs flow counter by index.\n *\n@@ -2093,4 +2035,5 @@ const struct mlx5_flow_driver_ops mlx5_flow_verbs_drv_ops = {\n \t.destroy = flow_verbs_destroy,\n \t.query = flow_verbs_query,\n \t.sync_domain = flow_verbs_sync_domain,\n+\t.discover_priorities = flow_verbs_discover_priorities,\n };\n", "prefixes": [ "v2", "1/3" ] }