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Update a patch.
GET /api/patches/96581/?format=api
{ "id": 96581, "url": "http://patchwork.dpdk.org/api/patches/96581/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210803083817.1243796-3-wenjun1.wu@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210803083817.1243796-3-wenjun1.wu@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210803083817.1243796-3-wenjun1.wu@intel.com", "date": "2021-08-03T08:37:57", "name": "[02/22] net/ice/base: align add VSI and update VSI AQ command buffer", "commit_ref": null, "pull_url": null, "state": "not-applicable", "archived": true, "hash": "3244c0248f949722e788f36d4d912ae6bd624889", "submitter": { "id": 2083, "url": "http://patchwork.dpdk.org/api/people/2083/?format=api", "name": "Wenjun Wu", "email": "wenjun1.wu@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210803083817.1243796-3-wenjun1.wu@intel.com/mbox/", "series": [ { "id": 18158, "url": "http://patchwork.dpdk.org/api/series/18158/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18158", "date": "2021-08-03T08:37:55", "name": "backport feature support to DPDK 20.11", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18158/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96581/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/96581/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 1A939A0C41;\n\tTue, 3 Aug 2021 10:57:23 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id CF0AE411C5;\n\tTue, 3 Aug 2021 10:57:14 +0200 (CEST)", "from mga04.intel.com (mga04.intel.com [192.55.52.120])\n by mails.dpdk.org (Postfix) with ESMTP id 5441D40E32\n for <dev@dpdk.org>; Tue, 3 Aug 2021 10:57:11 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 03 Aug 2021 01:56:49 -0700", "from wuwenjun.sh.intel.com ([10.67.110.197])\n by fmsmga008.fm.intel.com with ESMTP; 03 Aug 2021 01:56:48 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10064\"; a=\"211764357\"", "E=Sophos;i=\"5.84,291,1620716400\"; d=\"scan'208\";a=\"211764357\"", "E=Sophos;i=\"5.84,291,1620716400\"; d=\"scan'208\";a=\"479396565\"" ], "X-ExtLoop1": "1", "From": "Wenjun Wu <wenjun1.wu@intel.com>", "To": "dev@dpdk.org", "Date": "Tue, 3 Aug 2021 16:37:57 +0800", "Message-Id": "<20210803083817.1243796-3-wenjun1.wu@intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210803083817.1243796-1-wenjun1.wu@intel.com>", "References": "<20210803083817.1243796-1-wenjun1.wu@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 02/22] net/ice/base: align add VSI and update VSI\n AQ command buffer", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Qi Zhang <qi.z.zhang@intel.com>\n\n[ upstream commit 9ea028123a0bef9f6bbf5dd1a5250b9bfa63c1ea ]\n\nAligned the buffer the following admin commands to their new\ndefinitions:\n* 0x210 = add_vsi\n* 0x211 = update_vsi\n\nSigned-off-by: Shay Amir <shay.amir@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_adminq_cmd.h | 209 +++++++++++++-------------\n drivers/net/ice/ice_ethdev.c | 88 +++++------\n 2 files changed, 152 insertions(+), 145 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_adminq_cmd.h b/drivers/net/ice/base/ice_adminq_cmd.h\nindex f715fb0910..91d360be62 100644\n--- a/drivers/net/ice/base/ice_adminq_cmd.h\n+++ b/drivers/net/ice/base/ice_adminq_cmd.h\n@@ -411,144 +411,151 @@ struct ice_aqc_vsi_props {\n #define ICE_AQ_VSI_SW_FLAG_SRC_PRUNE\t\tBIT(7)\n \tu8 sw_flags2;\n #define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S\t0\n-#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M\t\\\n-\t\t\t\t(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)\n+#define ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_M\t(0xF << ICE_AQ_VSI_SW_FLAG_RX_PRUNE_EN_S)\n #define ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA\tBIT(0)\n #define ICE_AQ_VSI_SW_FLAG_LAN_ENA\t\tBIT(4)\n \tu8 veb_stat_id;\n #define ICE_AQ_VSI_SW_VEB_STAT_ID_S\t\t0\n-#define ICE_AQ_VSI_SW_VEB_STAT_ID_M\t(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)\n+#define ICE_AQ_VSI_SW_VEB_STAT_ID_M\t\t(0x1F << ICE_AQ_VSI_SW_VEB_STAT_ID_S)\n #define ICE_AQ_VSI_SW_VEB_STAT_ID_VALID\t\tBIT(5)\n \t/* security section */\n \tu8 sec_flags;\n #define ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD\tBIT(0)\n #define ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF\tBIT(2)\n-#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S\t4\n-#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M\t(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)\n+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S\t\t4\n+#define ICE_AQ_VSI_SEC_TX_PRUNE_ENA_M\t\t(0xF << ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S)\n #define ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA\tBIT(0)\n \tu8 sec_reserved;\n \t/* VLAN section */\n-\t__le16 pvid; /* VLANS include priority bits */\n-\tu8 pvlan_reserved[2];\n-\tu8 vlan_flags;\n-#define ICE_AQ_VSI_VLAN_MODE_S\t0\n-#define ICE_AQ_VSI_VLAN_MODE_M\t(0x3 << ICE_AQ_VSI_VLAN_MODE_S)\n-#define ICE_AQ_VSI_VLAN_MODE_UNTAGGED\t0x1\n-#define ICE_AQ_VSI_VLAN_MODE_TAGGED\t0x2\n-#define ICE_AQ_VSI_VLAN_MODE_ALL\t0x3\n-#define ICE_AQ_VSI_PVLAN_INSERT_PVID\tBIT(2)\n-#define ICE_AQ_VSI_VLAN_EMOD_S\t\t3\n-#define ICE_AQ_VSI_VLAN_EMOD_M\t\t(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)\n-#define ICE_AQ_VSI_VLAN_EMOD_STR_BOTH\t(0x0 << ICE_AQ_VSI_VLAN_EMOD_S)\n-#define ICE_AQ_VSI_VLAN_EMOD_STR_UP\t(0x1 << ICE_AQ_VSI_VLAN_EMOD_S)\n-#define ICE_AQ_VSI_VLAN_EMOD_STR\t(0x2 << ICE_AQ_VSI_VLAN_EMOD_S)\n-#define ICE_AQ_VSI_VLAN_EMOD_NOTHING\t(0x3 << ICE_AQ_VSI_VLAN_EMOD_S)\n-\tu8 pvlan_reserved2[3];\n+\t__le16 port_based_inner_vlan; /* VLANS include priority bits */\n+\tu8 inner_vlan_reserved[2];\n+\tu8 inner_vlan_flags;\n+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_S\t\t0\n+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_M\t\t(0x3 << ICE_AQ_VSI_INNER_VLAN_TX_MODE_S)\n+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED\t0x1\n+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED\t0x2\n+#define ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL\t0x3\n+#define ICE_AQ_VSI_INNER_VLAN_INSERT_PVID\tBIT(2)\n+#define ICE_AQ_VSI_INNER_VLAN_EMODE_S\t\t3\n+#define ICE_AQ_VSI_INNER_VLAN_EMODE_M\t\t(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)\n+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH\t(0x0 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)\n+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR_UP\t(0x1 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)\n+#define ICE_AQ_VSI_INNER_VLAN_EMODE_STR\t\t(0x2 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)\n+#define ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING\t(0x3 << ICE_AQ_VSI_INNER_VLAN_EMODE_S)\n+#define ICE_AQ_VSI_INNER_VLAN_BLOCK_TX_DESC\tBIT(5)\n+\tu8 inner_vlan_reserved2[3];\n \t/* ingress egress up sections */\n \t__le32 ingress_table; /* bitmap, 3 bits per up */\n-#define ICE_AQ_VSI_UP_TABLE_UP0_S\t0\n-#define ICE_AQ_VSI_UP_TABLE_UP0_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)\n-#define ICE_AQ_VSI_UP_TABLE_UP1_S\t3\n-#define ICE_AQ_VSI_UP_TABLE_UP1_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)\n-#define ICE_AQ_VSI_UP_TABLE_UP2_S\t6\n-#define ICE_AQ_VSI_UP_TABLE_UP2_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)\n-#define ICE_AQ_VSI_UP_TABLE_UP3_S\t9\n-#define ICE_AQ_VSI_UP_TABLE_UP3_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)\n-#define ICE_AQ_VSI_UP_TABLE_UP4_S\t12\n-#define ICE_AQ_VSI_UP_TABLE_UP4_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)\n-#define ICE_AQ_VSI_UP_TABLE_UP5_S\t15\n-#define ICE_AQ_VSI_UP_TABLE_UP5_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)\n-#define ICE_AQ_VSI_UP_TABLE_UP6_S\t18\n-#define ICE_AQ_VSI_UP_TABLE_UP6_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)\n-#define ICE_AQ_VSI_UP_TABLE_UP7_S\t21\n-#define ICE_AQ_VSI_UP_TABLE_UP7_M\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP0_S\t\t0\n+#define ICE_AQ_VSI_UP_TABLE_UP0_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP0_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP1_S\t\t3\n+#define ICE_AQ_VSI_UP_TABLE_UP1_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP1_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP2_S\t\t6\n+#define ICE_AQ_VSI_UP_TABLE_UP2_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP2_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP3_S\t\t9\n+#define ICE_AQ_VSI_UP_TABLE_UP3_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP3_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP4_S\t\t12\n+#define ICE_AQ_VSI_UP_TABLE_UP4_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP4_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP5_S\t\t15\n+#define ICE_AQ_VSI_UP_TABLE_UP5_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP5_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP6_S\t\t18\n+#define ICE_AQ_VSI_UP_TABLE_UP6_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP6_S)\n+#define ICE_AQ_VSI_UP_TABLE_UP7_S\t\t21\n+#define ICE_AQ_VSI_UP_TABLE_UP7_M\t\t(0x7 << ICE_AQ_VSI_UP_TABLE_UP7_S)\n \t__le32 egress_table; /* same defines as for ingress table */\n \t/* outer tags section */\n-\t__le16 outer_tag;\n-\tu8 outer_tag_flags;\n-#define ICE_AQ_VSI_OUTER_TAG_MODE_S\t0\n-#define ICE_AQ_VSI_OUTER_TAG_MODE_M\t(0x3 << ICE_AQ_VSI_OUTER_TAG_MODE_S)\n-#define ICE_AQ_VSI_OUTER_TAG_NOTHING\t0x0\n-#define ICE_AQ_VSI_OUTER_TAG_REMOVE\t0x1\n-#define ICE_AQ_VSI_OUTER_TAG_COPY\t0x2\n-#define ICE_AQ_VSI_OUTER_TAG_TYPE_S\t2\n-#define ICE_AQ_VSI_OUTER_TAG_TYPE_M\t(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)\n-#define ICE_AQ_VSI_OUTER_TAG_NONE\t0x0\n-#define ICE_AQ_VSI_OUTER_TAG_STAG\t0x1\n-#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100\t0x2\n-#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100\t0x3\n-#define ICE_AQ_VSI_OUTER_TAG_INSERT\tBIT(4)\n-#define ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST BIT(6)\n-\tu8 outer_tag_reserved;\n+\t__le16 port_based_outer_vlan;\n+\tu8 outer_vlan_flags;\n+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_S\t\t0\n+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_M\t\t(0x3 << ICE_AQ_VSI_OUTER_VLAN_EMODE_S)\n+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH\t0x0\n+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_UP\t0x1\n+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW\t0x2\n+#define ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING\t0x3\n+#define ICE_AQ_VSI_OUTER_TAG_TYPE_S\t\t2\n+#define ICE_AQ_VSI_OUTER_TAG_TYPE_M\t\t(0x3 << ICE_AQ_VSI_OUTER_TAG_TYPE_S)\n+#define ICE_AQ_VSI_OUTER_TAG_NONE\t\t0x0\n+#define ICE_AQ_VSI_OUTER_TAG_STAG\t\t0x1\n+#define ICE_AQ_VSI_OUTER_TAG_VLAN_8100\t\t0x2\n+#define ICE_AQ_VSI_OUTER_TAG_VLAN_9100\t\t0x3\n+#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT\t\tBIT(4)\n+#define ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST\t\tBIT(4)\n+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S\t\t\t5\n+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M\t\t\t(0x3 << ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S)\n+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTUNTAGGED\t0x1\n+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ACCEPTTAGGED\t0x2\n+#define ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL\t\t0x3\n+#define ICE_AQ_VSI_OUTER_VLAN_BLOCK_TX_DESC\t\tBIT(7)\n+\tu8 outer_vlan_reserved;\n \t/* queue mapping section */\n \t__le16 mapping_flags;\n-#define ICE_AQ_VSI_Q_MAP_CONTIG\t0x0\n-#define ICE_AQ_VSI_Q_MAP_NONCONTIG\tBIT(0)\n+#define ICE_AQ_VSI_Q_MAP_CONTIG\t\t\t0x0\n+#define ICE_AQ_VSI_Q_MAP_NONCONTIG\t\tBIT(0)\n \t__le16 q_mapping[16];\n-#define ICE_AQ_VSI_Q_S\t\t0\n-#define ICE_AQ_VSI_Q_M\t\t(0x7FF << ICE_AQ_VSI_Q_S)\n+#define ICE_AQ_VSI_Q_S\t\t\t\t0\n+#define ICE_AQ_VSI_Q_M\t\t\t\t(0x7FF << ICE_AQ_VSI_Q_S)\n \t__le16 tc_mapping[8];\n-#define ICE_AQ_VSI_TC_Q_OFFSET_S\t0\n-#define ICE_AQ_VSI_TC_Q_OFFSET_M\t(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)\n-#define ICE_AQ_VSI_TC_Q_NUM_S\t\t11\n-#define ICE_AQ_VSI_TC_Q_NUM_M\t\t(0xF << ICE_AQ_VSI_TC_Q_NUM_S)\n+#define ICE_AQ_VSI_TC_Q_OFFSET_S\t\t0\n+#define ICE_AQ_VSI_TC_Q_OFFSET_M\t\t(0x7FF << ICE_AQ_VSI_TC_Q_OFFSET_S)\n+#define ICE_AQ_VSI_TC_Q_NUM_S\t\t\t11\n+#define ICE_AQ_VSI_TC_Q_NUM_M\t\t\t(0xF << ICE_AQ_VSI_TC_Q_NUM_S)\n \t/* queueing option section */\n \tu8 q_opt_rss;\n-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S\t0\n-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)\n-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI\t0x0\n-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF\t0x2\n-#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL\t0x3\n-#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S\t2\n-#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M\t(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)\n-#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S\t6\n-#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n-#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ\t(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n-#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ\t(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n-#define ICE_AQ_VSI_Q_OPT_RSS_XOR\t(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n-#define ICE_AQ_VSI_Q_OPT_RSS_JHASH\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_S\t\t0\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_M\t\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_LUT_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI\t\t0x0\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_PF\t\t0x2\n+#define ICE_AQ_VSI_Q_OPT_RSS_LUT_GBL\t\t0x3\n+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S\t\t2\n+#define ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_M\t\t(0xF << ICE_AQ_VSI_Q_OPT_RSS_GBL_LUT_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_S\t\t6\n+#define ICE_AQ_VSI_Q_OPT_RSS_HASH_M\t\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_TPLZ\t\t(0x0 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_SYM_TPLZ\t\t(0x1 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_XOR\t\t(0x2 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n+#define ICE_AQ_VSI_Q_OPT_RSS_JHASH\t\t(0x3 << ICE_AQ_VSI_Q_OPT_RSS_HASH_S)\n \tu8 q_opt_tc;\n-#define ICE_AQ_VSI_Q_OPT_TC_OVR_S\t0\n-#define ICE_AQ_VSI_Q_OPT_TC_OVR_M\t(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)\n-#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR\tBIT(7)\n+#define ICE_AQ_VSI_Q_OPT_TC_OVR_S\t\t0\n+#define ICE_AQ_VSI_Q_OPT_TC_OVR_M\t\t(0x1F << ICE_AQ_VSI_Q_OPT_TC_OVR_S)\n+#define ICE_AQ_VSI_Q_OPT_PROF_TC_OVR\t\tBIT(7)\n \tu8 q_opt_flags;\n-#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN\tBIT(0)\n+#define ICE_AQ_VSI_Q_OPT_PE_FLTR_EN\t\tBIT(0)\n \tu8 q_opt_reserved[3];\n \t/* outer up section */\n \t__le32 outer_up_table; /* same structure and defines as ingress tbl */\n \t/* ACL section */\n \t__le16 acl_def_act;\n-#define ICE_AQ_VSI_ACL_DEF_RX_PROF_S\t0\n-#define ICE_AQ_VSI_ACL_DEF_RX_PROF_M\t(0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)\n-#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S\t4\n-#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M\t(0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)\n-#define ICE_AQ_VSI_ACL_DEF_TX_PROF_S\t8\n-#define ICE_AQ_VSI_ACL_DEF_TX_PROF_M\t(0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)\n-#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S\t12\n-#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M\t(0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)\n+#define ICE_AQ_VSI_ACL_DEF_RX_PROF_S\t\t0\n+#define ICE_AQ_VSI_ACL_DEF_RX_PROF_M\t\t(0xF << ICE_AQ_VSI_ACL_DEF_RX_PROF_S)\n+#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_S\t\t4\n+#define ICE_AQ_VSI_ACL_DEF_RX_TABLE_M\t\t(0xF << ICE_AQ_VSI_ACL_DEF_RX_TABLE_S)\n+#define ICE_AQ_VSI_ACL_DEF_TX_PROF_S\t\t8\n+#define ICE_AQ_VSI_ACL_DEF_TX_PROF_M\t\t(0xF << ICE_AQ_VSI_ACL_DEF_TX_PROF_S)\n+#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_S\t\t12\n+#define ICE_AQ_VSI_ACL_DEF_TX_TABLE_M\t\t(0xF << ICE_AQ_VSI_ACL_DEF_TX_TABLE_S)\n \t/* flow director section */\n \t__le16 fd_options;\n-#define ICE_AQ_VSI_FD_ENABLE\t\tBIT(0)\n-#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE\tBIT(1)\n-#define ICE_AQ_VSI_FD_PROG_ENABLE\tBIT(3)\n+#define ICE_AQ_VSI_FD_ENABLE\t\t\tBIT(0)\n+#define ICE_AQ_VSI_FD_TX_AUTO_ENABLE\t\tBIT(1)\n+#define ICE_AQ_VSI_FD_PROG_ENABLE\t\tBIT(3)\n \t__le16 max_fd_fltr_dedicated;\n \t__le16 max_fd_fltr_shared;\n \t__le16 fd_def_q;\n-#define ICE_AQ_VSI_FD_DEF_Q_S\t\t0\n-#define ICE_AQ_VSI_FD_DEF_Q_M\t\t(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)\n-#define ICE_AQ_VSI_FD_DEF_GRP_S\t12\n-#define ICE_AQ_VSI_FD_DEF_GRP_M\t(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)\n+#define ICE_AQ_VSI_FD_DEF_Q_S\t\t\t0\n+#define ICE_AQ_VSI_FD_DEF_Q_M\t\t\t(0x7FF << ICE_AQ_VSI_FD_DEF_Q_S)\n+#define ICE_AQ_VSI_FD_DEF_GRP_S\t\t\t12\n+#define ICE_AQ_VSI_FD_DEF_GRP_M\t\t\t(0x7 << ICE_AQ_VSI_FD_DEF_GRP_S)\n \t__le16 fd_report_opt;\n-#define ICE_AQ_VSI_FD_REPORT_Q_S\t0\n-#define ICE_AQ_VSI_FD_REPORT_Q_M\t(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)\n-#define ICE_AQ_VSI_FD_DEF_PRIORITY_S\t12\n-#define ICE_AQ_VSI_FD_DEF_PRIORITY_M\t(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)\n-#define ICE_AQ_VSI_FD_DEF_DROP\t\tBIT(15)\n+#define ICE_AQ_VSI_FD_REPORT_Q_S\t\t0\n+#define ICE_AQ_VSI_FD_REPORT_Q_M\t\t(0x7FF << ICE_AQ_VSI_FD_REPORT_Q_S)\n+#define ICE_AQ_VSI_FD_DEF_PRIORITY_S\t\t12\n+#define ICE_AQ_VSI_FD_DEF_PRIORITY_M\t\t(0x7 << ICE_AQ_VSI_FD_DEF_PRIORITY_S)\n+#define ICE_AQ_VSI_FD_DEF_DROP\t\t\tBIT(15)\n \t/* PASID section */\n \t__le32 pasid_id;\n-#define ICE_AQ_VSI_PASID_ID_S\t\t0\n-#define ICE_AQ_VSI_PASID_ID_M\t\t(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)\n-#define ICE_AQ_VSI_PASID_ID_VALID\tBIT(31)\n+#define ICE_AQ_VSI_PASID_ID_S\t\t\t0\n+#define ICE_AQ_VSI_PASID_ID_M\t\t\t(0xFFFFF << ICE_AQ_VSI_PASID_ID_S)\n+#define ICE_AQ_VSI_PASID_ID_VALID\t\tBIT(31)\n \tu8 reserved[24];\n };\n \ndiff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex c153c7ca78..9ce0280726 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -1131,28 +1131,28 @@ ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)\n \tif (vsi->info.valid_sections &\n \t\trte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {\n \t\tif (on) {\n-\t\t\tif ((vsi->info.outer_tag_flags &\n-\t\t\t ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==\n-\t\t\t ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)\n+\t\t\tif ((vsi->info.outer_vlan_flags &\n+\t\t\t ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST) ==\n+\t\t\t ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST)\n \t\t\t\treturn 0; /* already on */\n \t\t} else {\n-\t\t\tif (!(vsi->info.outer_tag_flags &\n-\t\t\t ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))\n+\t\t\tif (!(vsi->info.outer_vlan_flags &\n+\t\t\t ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST))\n \t\t\t\treturn 0; /* already off */\n \t\t}\n \t}\n \n \tif (on)\n-\t\tqinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;\n+\t\tqinq_flags = ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST;\n \telse\n \t\tqinq_flags = 0;\n \t/* clear global insertion and use per packet insertion */\n-\tvsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);\n-\tvsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);\n-\tvsi->info.outer_tag_flags |= qinq_flags;\n+\tvsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_INSERT);\n+\tvsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_PORT_BASED_ACCEPT_HOST);\n+\tvsi->info.outer_vlan_flags |= qinq_flags;\n \t/* use default vlan type 0x8100 */\n-\tvsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);\n-\tvsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<\n+\tvsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);\n+\tvsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<\n \t\t\t\t ICE_AQ_VSI_OUTER_TAG_TYPE_S;\n \t(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));\n \tctxt.info.valid_sections =\n@@ -1184,27 +1184,27 @@ ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)\n \tif (vsi->info.valid_sections &\n \t\trte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {\n \t\tif (on) {\n-\t\t\tif ((vsi->info.outer_tag_flags &\n-\t\t\t ICE_AQ_VSI_OUTER_TAG_MODE_M) ==\n-\t\t\t ICE_AQ_VSI_OUTER_TAG_COPY)\n+\t\t\tif ((vsi->info.outer_vlan_flags &\n+\t\t\t ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==\n+\t\t\t ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW)\n \t\t\t\treturn 0; /* already on */\n \t\t} else {\n-\t\t\tif ((vsi->info.outer_tag_flags &\n-\t\t\t ICE_AQ_VSI_OUTER_TAG_MODE_M) ==\n-\t\t\t ICE_AQ_VSI_OUTER_TAG_NOTHING)\n+\t\t\tif ((vsi->info.outer_vlan_flags &\n+\t\t\t ICE_AQ_VSI_OUTER_VLAN_EMODE_M) ==\n+\t\t\t ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH)\n \t\t\t\treturn 0; /* already off */\n \t\t}\n \t}\n \n \tif (on)\n-\t\tqinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;\n+\t\tqinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW;\n \telse\n-\t\tqinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;\n-\tvsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);\n-\tvsi->info.outer_tag_flags |= qinq_flags;\n+\t\tqinq_flags = ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH;\n+\tvsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M);\n+\tvsi->info.outer_vlan_flags |= qinq_flags;\n \t/* use default vlan type 0x8100 */\n-\tvsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);\n-\tvsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<\n+\tvsi->info.outer_vlan_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);\n+\tvsi->info.outer_vlan_flags |= ICE_DFLT_OUTER_TAG_TYPE <<\n \t\t\t\t ICE_AQ_VSI_OUTER_TAG_TYPE_S;\n \t(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));\n \tctxt.info.valid_sections =\n@@ -1582,8 +1582,8 @@ ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)\n \t\tvsi_ctx.info.sw_id = hw->port_info->sw_id;\n \t\tvsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;\n \t\t/* Allow all untagged or tagged packets */\n-\t\tvsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;\n-\t\tvsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;\n+\t\tvsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;\n+\t\tvsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;\n \t\tvsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |\n \t\t\t\t\t ICE_AQ_VSI_Q_OPT_RSS_TPLZ;\n \n@@ -4124,24 +4124,24 @@ ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)\n \tif (vsi->info.valid_sections &\n \t\trte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {\n \t\tif (on) {\n-\t\t\tif ((vsi->info.vlan_flags &\n-\t\t\t ICE_AQ_VSI_VLAN_EMOD_M) ==\n-\t\t\t ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)\n+\t\t\tif ((vsi->info.inner_vlan_flags &\n+\t\t\t ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==\n+\t\t\t ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH)\n \t\t\t\treturn 0; /* already on */\n \t\t} else {\n-\t\t\tif ((vsi->info.vlan_flags &\n-\t\t\t ICE_AQ_VSI_VLAN_EMOD_M) ==\n-\t\t\t ICE_AQ_VSI_VLAN_EMOD_NOTHING)\n+\t\t\tif ((vsi->info.inner_vlan_flags &\n+\t\t\t ICE_AQ_VSI_INNER_VLAN_EMODE_M) ==\n+\t\t\t ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING)\n \t\t\t\treturn 0; /* already off */\n \t\t}\n \t}\n \n \tif (on)\n-\t\tvlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;\n+\t\tvlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;\n \telse\n-\t\tvlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;\n-\tvsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);\n-\tvsi->info.vlan_flags |= vlan_flags;\n+\t\tvlan_flags = ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;\n+\tvsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_EMODE_M);\n+\tvsi->info.inner_vlan_flags |= vlan_flags;\n \t(void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));\n \tctxt.info.valid_sections =\n \t\trte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);\n@@ -4627,24 +4627,24 @@ ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)\n \t}\n \n \tif (info->on) {\n-\t\tvsi->info.pvid = info->config.pvid;\n+\t\tvsi->info.port_based_inner_vlan = info->config.pvid;\n \t\t/**\n \t\t * If insert pvid is enabled, only tagged pkts are\n \t\t * allowed to be sent out.\n \t\t */\n-\t\tvlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |\n-\t\t\t ICE_AQ_VSI_VLAN_MODE_UNTAGGED;\n+\t\tvlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |\n+\t\t\t ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;\n \t} else {\n-\t\tvsi->info.pvid = 0;\n+\t\tvsi->info.port_based_inner_vlan = 0;\n \t\tif (info->config.reject.tagged == 0)\n-\t\t\tvlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;\n+\t\t\tvlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;\n \n \t\tif (info->config.reject.untagged == 0)\n-\t\t\tvlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;\n+\t\t\tvlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;\n \t}\n-\tvsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |\n-\t\t\t\t ICE_AQ_VSI_VLAN_MODE_M);\n-\tvsi->info.vlan_flags |= vlan_flags;\n+\tvsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |\n+\t\t\t\t ICE_AQ_VSI_INNER_VLAN_EMODE_M);\n+\tvsi->info.inner_vlan_flags |= vlan_flags;\n \tmemset(&ctxt, 0, sizeof(ctxt));\n \trte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));\n \tctxt.info.valid_sections =\n", "prefixes": [ "02/22" ] }