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GET /api/patches/96693/?format=api
{ "id": 96693, "url": "http://patchwork.dpdk.org/api/patches/96693/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210806013424.186010-5-simei.su@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210806013424.186010-5-simei.su@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210806013424.186010-5-simei.su@intel.com", "date": "2021-08-06T01:34:24", "name": "[4/4] net/ice: support IEEE 1588 PTP", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "afd14f4325658443eec7b099c4412cb9fb72f299", "submitter": { "id": 1298, "url": "http://patchwork.dpdk.org/api/people/1298/?format=api", "name": "Simei Su", "email": "simei.su@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210806013424.186010-5-simei.su@intel.com/mbox/", "series": [ { "id": 18208, "url": "http://patchwork.dpdk.org/api/series/18208/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18208", "date": "2021-08-06T01:34:20", "name": "net/ice: support IEEE 1588", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18208/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96693/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/96693/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id ED180A0C41;\n\tFri, 6 Aug 2021 03:46:57 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 9DAB241298;\n\tFri, 6 Aug 2021 03:46:42 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id C88EE412A7\n for <dev@dpdk.org>; Fri, 6 Aug 2021 03:46:40 +0200 (CEST)", "from fmsmga002.fm.intel.com ([10.253.24.26])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 05 Aug 2021 18:46:40 -0700", "from unknown (HELO npg-dpdk-cvl-simeisu-118d193.sh.intel.com)\n ([10.67.119.195])\n by fmsmga002.fm.intel.com with ESMTP; 05 Aug 2021 18:46:37 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10067\"; a=\"193883172\"", "E=Sophos;i=\"5.84,299,1620716400\"; d=\"scan'208\";a=\"193883172\"", "E=Sophos;i=\"5.84,299,1620716400\"; d=\"scan'208\";a=\"523228544\"" ], "X-ExtLoop1": "1", "From": "Simei Su <simei.su@intel.com>", "To": "qi.z.zhang@intel.com", "Cc": "dev@dpdk.org,\n\thaiyue.wang@intel.com,\n\tSimei Su <simei.su@intel.com>", "Date": "Fri, 6 Aug 2021 09:34:24 +0800", "Message-Id": "<20210806013424.186010-5-simei.su@intel.com>", "X-Mailer": "git-send-email 2.9.5", "In-Reply-To": "<20210806013424.186010-1-simei.su@intel.com>", "References": "<20210806013424.186010-1-simei.su@intel.com>", "Subject": "[dpdk-dev] [PATCH 4/4] net/ice: support IEEE 1588 PTP", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add ice support for new ethdev APIs to enable and read IEEE1588\nPTP timstamps. Currently, only normal path supports 1588 PTP,\nvector path doesn't.\n\nThe example command for running ptpclinet is as below:\n./build/examples/dpdk-ptpclient -c 1 -n 3 --force-max-simd-bitwidth=64 --\n-T 0 -p 0x1\n\nSigned-off-by: Simei Su <simei.su@intel.com>\n---\n drivers/net/ice/ice_ethdev.c | 226 ++++++++++++++++++++++++++++++++++++++++++-\n drivers/net/ice/ice_ethdev.h | 5 +\n drivers/net/ice/ice_rxtx.c | 42 +++++++-\n drivers/net/ice/ice_rxtx.h | 1 +\n 4 files changed, 272 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c\nindex 5fd5f99..1e76628 100644\n--- a/drivers/net/ice/ice_ethdev.c\n+++ b/drivers/net/ice/ice_ethdev.c\n@@ -16,6 +16,7 @@\n #include \"base/ice_flow.h\"\n #include \"base/ice_dcb.h\"\n #include \"base/ice_common.h\"\n+#include \"base/ice_ptp_hw.h\"\n \n #include \"rte_pmd_ice.h\"\n #include \"ice_ethdev.h\"\n@@ -27,6 +28,8 @@\n #define ICE_PIPELINE_MODE_SUPPORT_ARG \"pipeline-mode-support\"\n #define ICE_PROTO_XTR_ARG \"proto_xtr\"\n \n+#define ICE_CYCLECOUNTER_MASK 0xffffffffffffffffULL\n+\n static const char * const ice_valid_args[] = {\n \tICE_SAFE_MODE_SUPPORT_ARG,\n \tICE_PIPELINE_MODE_SUPPORT_ARG,\n@@ -137,6 +140,18 @@ static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,\n \t\t\tstruct rte_eth_udp_tunnel *udp_tunnel);\n static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,\n \t\t\tstruct rte_eth_udp_tunnel *udp_tunnel);\n+static int ice_timesync_enable(struct rte_eth_dev *dev);\n+static int ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\t\t struct timespec *timestamp,\n+\t\t\t\t\t uint32_t flags);\n+static int ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t\t\t struct timespec *timestamp);\n+static int ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);\n+static int ice_timesync_read_time(struct rte_eth_dev *dev,\n+\t\t\t\t struct timespec *timestamp);\n+static int ice_timesync_write_time(struct rte_eth_dev *dev,\n+\t\t\t\t const struct timespec *timestamp);\n+static int ice_timesync_disable(struct rte_eth_dev *dev);\n \n static const struct rte_pci_id pci_id_ice_map[] = {\n \t{ RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },\n@@ -220,6 +235,13 @@ static const struct eth_dev_ops ice_eth_dev_ops = {\n \t.udp_tunnel_port_del = ice_dev_udp_tunnel_port_del,\n \t.tx_done_cleanup = ice_tx_done_cleanup,\n \t.get_monitor_addr = ice_get_monitor_addr,\n+\t.timesync_enable = ice_timesync_enable,\n+\t.timesync_read_rx_timestamp = ice_timesync_read_rx_timestamp,\n+\t.timesync_read_tx_timestamp = ice_timesync_read_tx_timestamp,\n+\t.timesync_adjust_time = ice_timesync_adjust_time,\n+\t.timesync_read_time = ice_timesync_read_time,\n+\t.timesync_write_time = ice_timesync_write_time,\n+\t.timesync_disable = ice_timesync_disable,\n };\n \n /* store statistics names and its offset in stats structure */\n@@ -3442,7 +3464,8 @@ ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)\n \t\t\tDEV_RX_OFFLOAD_QINQ_STRIP |\n \t\t\tDEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |\n \t\t\tDEV_RX_OFFLOAD_VLAN_EXTEND |\n-\t\t\tDEV_RX_OFFLOAD_RSS_HASH;\n+\t\t\tDEV_RX_OFFLOAD_RSS_HASH |\n+\t\t\tDEV_RX_OFFLOAD_TIMESTAMP;\n \t\tdev_info->tx_offload_capa |=\n \t\t\tDEV_TX_OFFLOAD_QINQ_INSERT |\n \t\t\tDEV_TX_OFFLOAD_IPV4_CKSUM |\n@@ -5254,6 +5277,207 @@ ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,\n }\n \n static int\n+ice_timesync_enable(struct rte_eth_dev *dev)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_adapter *ad =\n+\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tint ret;\n+\n+\tif (hw->func_caps.ts_func_info.src_tmr_owned) {\n+\t\tret = ice_ptp_init_phc(hw);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(ERR, \"Failed to initialize PHC\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\n+\t\tret = ice_ptp_write_incval(hw, ICE_PTP_NOMINAL_INCVAL_E810);\n+\t\tif (ret) {\n+\t\t\tPMD_DRV_LOG(ERR,\n+\t\t\t\t \"Failed to write PHC increment time value\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\t/* Initialize cycle counters for system time/RX/TX timestamp */\n+\tmemset(&ad->systime_tc, 0, sizeof(struct rte_timecounter));\n+\tmemset(&ad->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n+\tmemset(&ad->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));\n+\n+\tad->systime_tc.cc_mask = ICE_CYCLECOUNTER_MASK;\n+\tad->systime_tc.cc_shift = 0;\n+\tad->systime_tc.nsec_mask = 0;\n+\n+\tad->rx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;\n+\tad->rx_tstamp_tc.cc_shift = 0;\n+\tad->rx_tstamp_tc.nsec_mask = 0;\n+\n+\tad->tx_tstamp_tc.cc_mask = ICE_CYCLECOUNTER_MASK;\n+\tad->tx_tstamp_tc.cc_shift = 0;\n+\tad->tx_tstamp_tc.nsec_mask = 0;\n+\n+\treturn 0;\n+}\n+\n+static uint64_t\n+ice_read_time(struct ice_hw *hw)\n+{\n+\tuint32_t hi, lo, lo2;\n+\tuint64_t time;\n+\n+\tlo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));\n+\thi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));\n+\tlo2 = ICE_READ_REG(hw, GLTSYN_TIME_L(0));\n+\n+\tif (lo2 < lo) {\n+\t\tlo = ICE_READ_REG(hw, GLTSYN_TIME_L(0));\n+\t\thi = ICE_READ_REG(hw, GLTSYN_TIME_H(0));\n+\t}\n+\n+\ttime = ((uint64_t)hi << 32) | lo;\n+\n+\treturn time;\n+}\n+\n+static uint64_t\n+ice_tstamp_convert_32b_64b(uint64_t time, uint64_t timestamp)\n+{\n+\tconst uint64_t mask = 0xFFFFFFFF;\n+\tuint32_t delta;\n+\tuint64_t ns;\n+\n+\tdelta = (timestamp - (uint32_t)(time & mask));\n+\n+\tif (delta > (mask / 2)) {\n+\t\tdelta = ((uint32_t)(time & mask) - timestamp);\n+\t\tns = time - delta;\n+\t} else {\n+\t\tns = time + delta;\n+\t}\n+\n+\treturn ns;\n+}\n+\n+static int\n+ice_timesync_read_rx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t struct timespec *timestamp, uint32_t flags)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_adapter *ad =\n+\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tstruct ice_rx_queue *rxq;\n+\tuint32_t ts_high;\n+\tuint64_t time, ts_ns, ns;\n+\n+\trxq = dev->data->rx_queues[flags];\n+\n+\ttime = ice_read_time(hw);\n+\n+\tts_high = rxq->time_high;\n+\tts_ns = ice_tstamp_convert_32b_64b(time, ts_high);\n+\tns = rte_timecounter_update(&ad->rx_tstamp_tc, ts_ns);\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_timesync_read_tx_timestamp(struct rte_eth_dev *dev,\n+\t\t\t struct timespec *timestamp)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_adapter *ad =\n+\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tuint8_t lport;\n+\tuint64_t time, ts_ns, ns, tstamp;\n+\tconst uint64_t mask = 0xFFFFFFFF;\n+\tint ret;\n+\n+\tlport = hw->port_info->lport;\n+\n+\tret = ice_read_phy_tstamp(hw, lport, 0, &tstamp);\n+\tif (ret) {\n+\t\tPMD_DRV_LOG(ERR, \"Failed to read phy timestamp\\n\");\n+\t\treturn -1;\n+\t}\n+\n+\ttime = ice_read_time(hw);\n+\n+\tts_ns = ice_tstamp_convert_32b_64b(time, (tstamp >> 8) & mask);\n+\tns = rte_timecounter_update(&ad->tx_tstamp_tc, ts_ns);\n+\t*timestamp = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)\n+{\n+\tstruct ice_adapter *ad =\n+\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\n+\tad->systime_tc.nsec += delta;\n+\tad->rx_tstamp_tc.nsec += delta;\n+\tad->tx_tstamp_tc.nsec += delta;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)\n+{\n+\tstruct ice_adapter *ad =\n+\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tuint64_t ns;\n+\n+\tns = rte_timespec_to_ns(ts);\n+\n+\tad->systime_tc.nsec = ns;\n+\tad->rx_tstamp_tc.nsec = ns;\n+\tad->tx_tstamp_tc.nsec = ns;\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tstruct ice_adapter *ad =\n+\t\t\tICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);\n+\tuint64_t time, ns;\n+\n+\ttime = ice_read_time(hw);\n+\tns = rte_timecounter_update(&ad->systime_tc, time);\n+\t*ts = rte_ns_to_timespec(ns);\n+\n+\treturn 0;\n+}\n+\n+static int\n+ice_timesync_disable(struct rte_eth_dev *dev)\n+{\n+\tstruct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);\n+\tuint64_t val;\n+\tuint8_t lport;\n+\n+\tlport = hw->port_info->lport;\n+\n+\tdev->data->dev_conf.rxmode.offloads &= ~DEV_RX_OFFLOAD_TIMESTAMP;\n+\n+\tice_clear_phy_tstamp(hw, lport, 0);\n+\n+\tval = ICE_READ_REG(hw, GLTSYN_ENA(0));\n+\tval &= ~GLTSYN_ENA_TSYN_ENA_M;\n+\tICE_WRITE_REG(hw, GLTSYN_ENA(0), val);\n+\n+\tICE_WRITE_REG(hw, GLTSYN_INCVAL_L(0), 0);\n+\tICE_WRITE_REG(hw, GLTSYN_INCVAL_H(0), 0);\n+\n+\treturn 0;\n+}\n+\n+static int\n ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t struct rte_pci_device *pci_dev)\n {\ndiff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h\nindex 2a8a816..f71af40 100644\n--- a/drivers/net/ice/ice_ethdev.h\n+++ b/drivers/net/ice/ice_ethdev.h\n@@ -6,6 +6,7 @@\n #define _ICE_ETHDEV_H_\n \n #include <rte_kvargs.h>\n+#include <rte_time.h>\n \n #include <ethdev_driver.h>\n \n@@ -487,6 +488,10 @@ struct ice_adapter {\n \tstruct ice_devargs devargs;\n \tenum ice_pkg_type active_pkg_type; /* loaded ddp package type */\n \tuint16_t fdir_ref_cnt;\n+\t/* For PTP */\n+\tstruct rte_timecounter systime_tc;\n+\tstruct rte_timecounter rx_tstamp_tc;\n+\tstruct rte_timecounter tx_tstamp_tc;\n };\n \n struct ice_vsi_vlan_pvid_info {\ndiff --git a/drivers/net/ice/ice_rxtx.c b/drivers/net/ice/ice_rxtx.c\nindex 49abcb2..606a4e2 100644\n--- a/drivers/net/ice/ice_rxtx.c\n+++ b/drivers/net/ice/ice_rxtx.c\n@@ -346,6 +346,11 @@ ice_program_hw_rx_queue(struct ice_rx_queue *rxq)\n \tregval |= (0x03 << QRXFLXP_CNTXT_RXDID_PRIO_S) &\n \t\tQRXFLXP_CNTXT_RXDID_PRIO_M;\n \n+\t/* Enable timestamp bit in the queue context */\n+\tif (rxmode->offloads & DEV_RX_OFFLOAD_TIMESTAMP)\n+\t\tregval |= (0x1 << QRXFLXP_CNTXT_TS_S) &\n+\t\t\tQRXFLXP_CNTXT_TS_M;\n+\n \tICE_WRITE_REG(hw, QRXFLXP_CNTXT(rxq->reg_idx), regval);\n \n \terr = ice_clear_rxq_ctx(hw, rxq->reg_idx);\n@@ -681,6 +686,7 @@ ice_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)\n \ttx_ctx.tso_ena = 1; /* tso enable */\n \ttx_ctx.tso_qnum = txq->reg_idx; /* index for tso state structure */\n \ttx_ctx.legacy_int = 1; /* Legacy or Advanced Host Interface */\n+\ttx_ctx.tsyn_ena = 1;\n \n \tice_set_ctx(hw, (uint8_t *)&tx_ctx, txq_elem->txqs[0].txq_ctx,\n \t\t ice_tlan_ctx_info);\n@@ -1530,6 +1536,7 @@ static inline int\n ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)\n {\n \tvolatile union ice_rx_flex_desc *rxdp;\n+\tstruct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;\n \tstruct ice_rx_entry *rxep;\n \tstruct rte_mbuf *mb;\n \tuint16_t stat_err0;\n@@ -1581,6 +1588,14 @@ ice_rx_scan_hw_ring(struct ice_rx_queue *rxq)\n \t\t\tice_rxd_to_vlan_tci(mb, &rxdp[j]);\n \t\t\trxq->rxd_to_pkt_fields(rxq, mb, &rxdp[j]);\n \n+\t\t\tif (dev_data->dev_conf.rxmode.offloads &\n+\t\t\t DEV_RX_OFFLOAD_TIMESTAMP) {\n+\t\t\t\trxq->time_high = rte_le_to_cpu_32(\n+\t\t\t\t\t\trxdp[j].wb.flex_ts.ts_high);\n+\t\t\t\tmb->timesync = rxq->queue_id;\n+\t\t\t\tpkt_flags |= PKT_RX_IEEE1588_PTP;\n+\t\t\t}\n+\n \t\t\tmb->ol_flags |= pkt_flags;\n \t\t}\n \n@@ -1749,6 +1764,7 @@ ice_recv_scattered_pkts(void *rx_queue,\n \t\t\tuint16_t nb_pkts)\n {\n \tstruct ice_rx_queue *rxq = rx_queue;\n+\tstruct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;\n \tvolatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;\n \tvolatile union ice_rx_flex_desc *rxdp;\n \tunion ice_rx_flex_desc rxd;\n@@ -1878,6 +1894,14 @@ ice_recv_scattered_pkts(void *rx_queue,\n \t\tice_rxd_to_vlan_tci(first_seg, &rxd);\n \t\trxq->rxd_to_pkt_fields(rxq, first_seg, &rxd);\n \t\tpkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);\n+\n+\t\tif (dev_data->dev_conf.rxmode.offloads &\n+\t\t DEV_RX_OFFLOAD_TIMESTAMP) {\n+\t\t\trxq->time_high = rxd.wb.flex_ts.ts_high;\n+\t\t\tfirst_seg->timesync = rxq->queue_id;\n+\t\t\tpkt_flags |= PKT_RX_IEEE1588_PTP;\n+\t\t}\n+\n \t\tfirst_seg->ol_flags |= pkt_flags;\n \t\t/* Prefetch data of first segment, if configured to do so. */\n \t\trte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,\n@@ -2216,6 +2240,7 @@ ice_recv_pkts(void *rx_queue,\n \t uint16_t nb_pkts)\n {\n \tstruct ice_rx_queue *rxq = rx_queue;\n+\tstruct rte_eth_dev_data *dev_data = rxq->vsi->adapter->pf.dev_data;\n \tvolatile union ice_rx_flex_desc *rx_ring = rxq->rx_ring;\n \tvolatile union ice_rx_flex_desc *rxdp;\n \tunion ice_rx_flex_desc rxd;\n@@ -2284,6 +2309,14 @@ ice_recv_pkts(void *rx_queue,\n \t\tice_rxd_to_vlan_tci(rxm, &rxd);\n \t\trxq->rxd_to_pkt_fields(rxq, rxm, &rxd);\n \t\tpkt_flags = ice_rxd_error_to_pkt_flags(rx_stat_err0);\n+\n+\t\tif (dev_data->dev_conf.rxmode.offloads &\n+\t\t DEV_RX_OFFLOAD_TIMESTAMP) {\n+\t\t\trxq->time_high = rxd.wb.flex_ts.ts_high;\n+\t\t\trxm->timesync = rxq->queue_id;\n+\t\t\tpkt_flags |= PKT_RX_IEEE1588_PTP;\n+\t\t}\n+\n \t\trxm->ol_flags |= pkt_flags;\n \t\t/* copy old mbuf to rx_pkts */\n \t\trx_pkts[nb_rx++] = rxm;\n@@ -2495,7 +2528,8 @@ ice_calc_context_desc(uint64_t flags)\n \tstatic uint64_t mask = PKT_TX_TCP_SEG |\n \t\tPKT_TX_QINQ |\n \t\tPKT_TX_OUTER_IP_CKSUM |\n-\t\tPKT_TX_TUNNEL_MASK;\n+\t\tPKT_TX_TUNNEL_MASK |\n+\t\tPKT_TX_IEEE1588_TMST;\n \n \treturn (flags & mask) ? 1 : 0;\n }\n@@ -2663,6 +2697,12 @@ ice_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)\n \t\t\tif (ol_flags & PKT_TX_TCP_SEG)\n \t\t\t\tcd_type_cmd_tso_mss |=\n \t\t\t\t\tice_set_tso_ctx(tx_pkt, tx_offload);\n+\t\t\telse {\n+\t\t\t\tif (ol_flags & PKT_TX_IEEE1588_TMST)\n+\t\t\t\t\tcd_type_cmd_tso_mss |=\n+\t\t\t\t\t ((uint64_t)ICE_TX_CTX_DESC_TSYN <<\n+\t\t\t\t\t ICE_TXD_CTX_QW1_CMD_S);\n+\t\t\t}\n \n \t\t\tctx_txd->tunneling_params =\n \t\t\t\trte_cpu_to_le_32(cd_tunneling_params);\ndiff --git a/drivers/net/ice/ice_rxtx.h b/drivers/net/ice/ice_rxtx.h\nindex b29387c..b544eb2 100644\n--- a/drivers/net/ice/ice_rxtx.h\n+++ b/drivers/net/ice/ice_rxtx.h\n@@ -89,6 +89,7 @@ struct ice_rx_queue {\n \tice_rxd_to_pkt_fields_t rxd_to_pkt_fields; /* handle FlexiMD by RXDID */\n \tice_rx_release_mbufs_t rx_rel_mbufs;\n \tuint64_t offloads;\n+\tuint32_t time_high; /* High value of the timestamp */\n };\n \n struct ice_tx_entry {\n", "prefixes": [ "4/4" ] }