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GET /api/patches/96747/?format=api
{ "id": 96747, "url": "http://patchwork.dpdk.org/api/patches/96747/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-9-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210810025140.1698163-9-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210810025140.1698163-9-qi.z.zhang@intel.com", "date": "2021-08-10T02:51:20", "name": "[08/28] net/ice/base: print human-friendly PHY types", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "d54476479de3934cd6acbbade57cc257640eb8e5", "submitter": { "id": 504, "url": "http://patchwork.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "http://patchwork.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210810025140.1698163-9-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18242, "url": "http://patchwork.dpdk.org/api/series/18242/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18242", "date": "2021-08-10T02:51:12", "name": "ice: base code update", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18242/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96747/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96747/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id C9E9FA0C54;\n\tTue, 10 Aug 2021 04:49:29 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 30B49411AA;\n\tTue, 10 Aug 2021 04:48:54 +0200 (CEST)", "from mga09.intel.com (mga09.intel.com [134.134.136.24])\n by mails.dpdk.org (Postfix) with ESMTP id 67451410FF\n for <dev@dpdk.org>; Tue, 10 Aug 2021 04:48:52 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 09 Aug 2021 19:48:52 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 09 Aug 2021 19:48:50 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10070\"; a=\"214808429\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"214808429\"", "E=Sophos;i=\"5.84,309,1620716400\"; d=\"scan'208\";a=\"483823593\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>", "Date": "Tue, 10 Aug 2021 10:51:20 +0800", "Message-Id": "<20210810025140.1698163-9-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "References": "<20210810025140.1698163-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 08/28] net/ice/base: print human-friendly PHY\n types", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add functions to print PHY types in human-friendly form\n\nSigned-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_common.c | 164 ++++++++++++++++++++++++++----\n 1 file changed, 146 insertions(+), 18 deletions(-)", "diff": "diff --git a/drivers/net/ice/base/ice_common.c b/drivers/net/ice/base/ice_common.c\nindex e8d66aad6b..2447d15b87 100644\n--- a/drivers/net/ice/base/ice_common.c\n+++ b/drivers/net/ice/base/ice_common.c\n@@ -11,6 +11,120 @@\n \n #define ICE_PF_RESET_WAIT_COUNT\t300\n \n+/**\n+ * dump_phy_type - helper function that prints PHY type strings\n+ * @hw: pointer to the HW structure\n+ * @phy: 64 bit PHY type to decipher\n+ * @i: bit index within phy\n+ * @phy_string: string corresponding to bit i in phy\n+ * @prefix: prefix string to differentiate multiple dumps\n+ */\n+static void\n+dump_phy_type(struct ice_hw *hw, u64 phy, u8 i, const char *phy_string,\n+\t const char *prefix)\n+{\n+\tif (phy & BIT_ULL(i))\n+\t\tice_debug(hw, ICE_DBG_PHY, \"%s: bit(%d): %s\\n\", prefix, i,\n+\t\t\t phy_string);\n+}\n+\n+/**\n+ * ice_dump_phy_type_low - helper function to dump phy_type_low\n+ * @hw: pointer to the HW structure\n+ * @low: 64 bit value for phy_type_low\n+ * @prefix: prefix string to differentiate multiple dumps\n+ */\n+static void\n+ice_dump_phy_type_low(struct ice_hw *hw, u64 low, const char *prefix)\n+{\n+\tice_debug(hw, ICE_DBG_PHY, \"%s: phy_type_low: 0x%016llx\\n\", prefix,\n+\t\t (unsigned long long)low);\n+\n+\tdump_phy_type(hw, low, 0, \"100BASE_TX\", prefix);\n+\tdump_phy_type(hw, low, 1, \"100M_SGMII\", prefix);\n+\tdump_phy_type(hw, low, 2, \"1000BASE_T\", prefix);\n+\tdump_phy_type(hw, low, 3, \"1000BASE_SX\", prefix);\n+\tdump_phy_type(hw, low, 4, \"1000BASE_LX\", prefix);\n+\tdump_phy_type(hw, low, 5, \"1000BASE_KX\", prefix);\n+\tdump_phy_type(hw, low, 6, \"1G_SGMII\", prefix);\n+\tdump_phy_type(hw, low, 7, \"2500BASE_T\", prefix);\n+\tdump_phy_type(hw, low, 8, \"2500BASE_X\", prefix);\n+\tdump_phy_type(hw, low, 9, \"2500BASE_KX\", prefix);\n+\tdump_phy_type(hw, low, 10, \"5GBASE_T\", prefix);\n+\tdump_phy_type(hw, low, 11, \"5GBASE_KR\", prefix);\n+\tdump_phy_type(hw, low, 12, \"10GBASE_T\", prefix);\n+\tdump_phy_type(hw, low, 13, \"10G_SFI_DA\", prefix);\n+\tdump_phy_type(hw, low, 14, \"10GBASE_SR\", prefix);\n+\tdump_phy_type(hw, low, 15, \"10GBASE_LR\", prefix);\n+\tdump_phy_type(hw, low, 16, \"10GBASE_KR_CR1\", prefix);\n+\tdump_phy_type(hw, low, 17, \"10G_SFI_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 18, \"10G_SFI_C2C\", prefix);\n+\tdump_phy_type(hw, low, 19, \"25GBASE_T\", prefix);\n+\tdump_phy_type(hw, low, 20, \"25GBASE_CR\", prefix);\n+\tdump_phy_type(hw, low, 21, \"25GBASE_CR_S\", prefix);\n+\tdump_phy_type(hw, low, 22, \"25GBASE_CR1\", prefix);\n+\tdump_phy_type(hw, low, 23, \"25GBASE_SR\", prefix);\n+\tdump_phy_type(hw, low, 24, \"25GBASE_LR\", prefix);\n+\tdump_phy_type(hw, low, 25, \"25GBASE_KR\", prefix);\n+\tdump_phy_type(hw, low, 26, \"25GBASE_KR_S\", prefix);\n+\tdump_phy_type(hw, low, 27, \"25GBASE_KR1\", prefix);\n+\tdump_phy_type(hw, low, 28, \"25G_AUI_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 29, \"25G_AUI_C2C\", prefix);\n+\tdump_phy_type(hw, low, 30, \"40GBASE_CR4\", prefix);\n+\tdump_phy_type(hw, low, 31, \"40GBASE_SR4\", prefix);\n+\tdump_phy_type(hw, low, 32, \"40GBASE_LR4\", prefix);\n+\tdump_phy_type(hw, low, 33, \"40GBASE_KR4\", prefix);\n+\tdump_phy_type(hw, low, 34, \"40G_XLAUI_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 35, \"40G_XLAUI\", prefix);\n+\tdump_phy_type(hw, low, 36, \"50GBASE_CR2\", prefix);\n+\tdump_phy_type(hw, low, 37, \"50GBASE_SR2\", prefix);\n+\tdump_phy_type(hw, low, 38, \"50GBASE_LR2\", prefix);\n+\tdump_phy_type(hw, low, 39, \"50GBASE_KR2\", prefix);\n+\tdump_phy_type(hw, low, 40, \"50G_LAUI2_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 41, \"50G_LAUI2\", prefix);\n+\tdump_phy_type(hw, low, 42, \"50G_AUI2_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 43, \"50G_AUI2\", prefix);\n+\tdump_phy_type(hw, low, 44, \"50GBASE_CP\", prefix);\n+\tdump_phy_type(hw, low, 45, \"50GBASE_SR\", prefix);\n+\tdump_phy_type(hw, low, 46, \"50GBASE_FR\", prefix);\n+\tdump_phy_type(hw, low, 47, \"50GBASE_LR\", prefix);\n+\tdump_phy_type(hw, low, 48, \"50GBASE_KR_PAM4\", prefix);\n+\tdump_phy_type(hw, low, 49, \"50G_AUI1_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 50, \"50G_AUI1\", prefix);\n+\tdump_phy_type(hw, low, 51, \"100GBASE_CR4\", prefix);\n+\tdump_phy_type(hw, low, 52, \"100GBASE_SR4\", prefix);\n+\tdump_phy_type(hw, low, 53, \"100GBASE_LR4\", prefix);\n+\tdump_phy_type(hw, low, 54, \"100GBASE_KR4\", prefix);\n+\tdump_phy_type(hw, low, 55, \"100G_CAUI4_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 56, \"100G_CAUI4\", prefix);\n+\tdump_phy_type(hw, low, 57, \"100G_AUI4_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, low, 58, \"100G_AUI4\", prefix);\n+\tdump_phy_type(hw, low, 59, \"100GBASE_CR_PAM4\", prefix);\n+\tdump_phy_type(hw, low, 60, \"100GBASE_KR_PAM4\", prefix);\n+\tdump_phy_type(hw, low, 61, \"100GBASE_CP2\", prefix);\n+\tdump_phy_type(hw, low, 62, \"100GBASE_SR2\", prefix);\n+\tdump_phy_type(hw, low, 63, \"100GBASE_DR\", prefix);\n+}\n+\n+/**\n+ * ice_dump_phy_type_high - helper function to dump phy_type_high\n+ * @hw: pointer to the HW structure\n+ * @high: 64 bit value for phy_type_high\n+ * @prefix: prefix string to differentiate multiple dumps\n+ */\n+static void\n+ice_dump_phy_type_high(struct ice_hw *hw, u64 high, const char *prefix)\n+{\n+\tice_debug(hw, ICE_DBG_PHY, \"%s: phy_type_high: 0x%016llx\\n\", prefix,\n+\t\t (unsigned long long)high);\n+\n+\tdump_phy_type(hw, high, 0, \"100GBASE_KR2_PAM4\", prefix);\n+\tdump_phy_type(hw, high, 1, \"100G_CAUI2_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, high, 2, \"100G_CAUI2\", prefix);\n+\tdump_phy_type(hw, high, 3, \"100G_AUI2_AOC_ACC\", prefix);\n+\tdump_phy_type(hw, high, 4, \"100G_AUI2\", prefix);\n+}\n+\n /**\n * ice_set_mac_type - Sets MAC type\n * @hw: pointer to the HW structure\n@@ -180,6 +294,7 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n \tu16 pcaps_size = sizeof(*pcaps);\n \tstruct ice_aq_desc desc;\n \tenum ice_status status;\n+\tconst char *prefix;\n \tstruct ice_hw *hw;\n \n \tcmd = &desc.params.get_phy;\n@@ -200,29 +315,42 @@ ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,\n \tcmd->param0 |= CPU_TO_LE16(report_mode);\n \tstatus = ice_aq_send_cmd(hw, &desc, pcaps, pcaps_size, cd);\n \n-\tice_debug(hw, ICE_DBG_LINK, \"get phy caps - report_mode = 0x%x\\n\",\n-\t\t report_mode);\n-\tice_debug(hw, ICE_DBG_LINK, \"\tphy_type_low = 0x%llx\\n\",\n-\t\t (unsigned long long)LE64_TO_CPU(pcaps->phy_type_low));\n-\tice_debug(hw, ICE_DBG_LINK, \"\tphy_type_high = 0x%llx\\n\",\n-\t\t (unsigned long long)LE64_TO_CPU(pcaps->phy_type_high));\n-\tice_debug(hw, ICE_DBG_LINK, \"\tcaps = 0x%x\\n\", pcaps->caps);\n-\tice_debug(hw, ICE_DBG_LINK, \"\tlow_power_ctrl_an = 0x%x\\n\",\n+\tice_debug(hw, ICE_DBG_LINK, \"get phy caps dump\\n\");\n+\n+\tif (report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA)\n+\t\tprefix = \"phy_caps_media\";\n+\telse if (report_mode == ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA)\n+\t\tprefix = \"phy_caps_no_media\";\n+\telse if (report_mode == ICE_AQC_REPORT_ACTIVE_CFG)\n+\t\tprefix = \"phy_caps_active\";\n+\telse if (report_mode == ICE_AQC_REPORT_DFLT_CFG)\n+\t\tprefix = \"phy_caps_default\";\n+\telse\n+\t\tprefix = \"phy_caps_invalid\";\n+\n+\tice_dump_phy_type_low(hw, LE64_TO_CPU(pcaps->phy_type_low), prefix);\n+\tice_dump_phy_type_high(hw, LE64_TO_CPU(pcaps->phy_type_high), prefix);\n+\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: report_mode = 0x%x\\n\",\n+\t\t prefix, report_mode);\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: caps = 0x%x\\n\", prefix, pcaps->caps);\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: low_power_ctrl_an = 0x%x\\n\", prefix,\n \t\t pcaps->low_power_ctrl_an);\n-\tice_debug(hw, ICE_DBG_LINK, \"\teee_cap = 0x%x\\n\", pcaps->eee_cap);\n-\tice_debug(hw, ICE_DBG_LINK, \"\teeer_value = 0x%x\\n\",\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: eee_cap = 0x%x\\n\", prefix,\n+\t\t pcaps->eee_cap);\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: eeer_value = 0x%x\\n\", prefix,\n \t\t pcaps->eeer_value);\n-\tice_debug(hw, ICE_DBG_LINK, \"\tlink_fec_options = 0x%x\\n\",\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: link_fec_options = 0x%x\\n\", prefix,\n \t\t pcaps->link_fec_options);\n-\tice_debug(hw, ICE_DBG_LINK, \"\tmodule_compliance_enforcement = 0x%x\\n\",\n-\t\t pcaps->module_compliance_enforcement);\n-\tice_debug(hw, ICE_DBG_LINK, \" extended_compliance_code = 0x%x\\n\",\n-\t\t pcaps->extended_compliance_code);\n-\tice_debug(hw, ICE_DBG_LINK, \" module_type[0] = 0x%x\\n\",\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: module_compliance_enforcement = 0x%x\\n\",\n+\t\t prefix, pcaps->module_compliance_enforcement);\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: extended_compliance_code = 0x%x\\n\",\n+\t\t prefix, pcaps->extended_compliance_code);\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: module_type[0] = 0x%x\\n\", prefix,\n \t\t pcaps->module_type[0]);\n-\tice_debug(hw, ICE_DBG_LINK, \" module_type[1] = 0x%x\\n\",\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: module_type[1] = 0x%x\\n\", prefix,\n \t\t pcaps->module_type[1]);\n-\tice_debug(hw, ICE_DBG_LINK, \" module_type[2] = 0x%x\\n\",\n+\tice_debug(hw, ICE_DBG_LINK, \"%s: module_type[2] = 0x%x\\n\", prefix,\n \t\t pcaps->module_type[2]);\n \n \tif (status == ICE_SUCCESS && report_mode == ICE_AQC_REPORT_TOPO_CAP_MEDIA) {\n", "prefixes": [ "08/28" ] }