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GET /api/patches/96996/?format=api
{ "id": 96996, "url": "http://patchwork.dpdk.org/api/patches/96996/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-6-michaelba@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210817134441.1966618-6-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210817134441.1966618-6-michaelba@nvidia.com", "date": "2021-08-17T13:44:25", "name": "[RFC,05/21] crypto/mlx5: use context device structure", "commit_ref": null, "pull_url": null, "state": "rfc", "archived": true, "hash": "d58ef0e97dae812549167709b96b5218b9d27c97", "submitter": { "id": 1949, "url": "http://patchwork.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 3268, "url": "http://patchwork.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210817134441.1966618-6-michaelba@nvidia.com/mbox/", "series": [ { "id": 18314, "url": "http://patchwork.dpdk.org/api/series/18314/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18314", "date": "2021-08-17T13:44:20", "name": "mlx5: sharing global MR cache between drivers", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18314/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/96996/comments/", "check": "success", "checks": "http://patchwork.dpdk.org/api/patches/96996/checks/", "tags": {}, "related": [], "headers": { "Return-Path": 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"Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MWHPR12MB1248", "Subject": "[dpdk-dev] [RFC 05/21] crypto/mlx5: use context device structure", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Use common context device structure as a priv field.\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/crypto/mlx5/mlx5_crypto.c | 114 ++++++++++----------------\n drivers/crypto/mlx5/mlx5_crypto.h | 4 +-\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 5 +-\n 3 files changed, 49 insertions(+), 74 deletions(-)", "diff": "diff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex b3d5200ca3..7cb5bb5445 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -347,7 +347,8 @@ mlx5_crypto_addr2mr(struct mlx5_crypto_priv *priv, uintptr_t addr,\n \tif (likely(lkey != UINT32_MAX))\n \t\treturn lkey;\n \t/* Take slower bottom-half on miss. */\n-\treturn mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,\n+\treturn mlx5_mr_addr2mr_bh(priv->dev_ctx->pd, 0, &priv->mr_scache,\n+\t\t\t\t mr_ctrl, addr,\n \t\t\t\t !!(ol_flags & EXT_ATTACHED_MBUF));\n }\n \n@@ -621,7 +622,7 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n \tstruct mlx5_umr_wqe *umr;\n \tuint32_t i;\n \tstruct mlx5_devx_mkey_attr attr = {\n-\t\t.pd = priv->pdn,\n+\t\t.pd = priv->dev_ctx->pdn,\n \t\t.umr_en = 1,\n \t\t.crypto_en = 1,\n \t\t.set_remote_rw = 1,\n@@ -631,7 +632,8 @@ mlx5_crypto_indirect_mkeys_prepare(struct mlx5_crypto_priv *priv,\n \tfor (umr = (struct mlx5_umr_wqe *)qp->umem_buf, i = 0;\n \t i < qp->entries_n; i++, umr = RTE_PTR_ADD(umr, priv->wqe_set_size)) {\n \t\tattr.klm_array = (struct mlx5_klm *)&umr->kseg[0];\n-\t\tqp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->ctx, &attr);\n+\t\tqp->mkey[i] = mlx5_devx_cmd_mkey_create(priv->dev_ctx->ctx,\n+\t\t\t\t\t\t\t&attr);\n \t\tif (!qp->mkey[i]) {\n \t\t\tDRV_LOG(ERR, \"Failed to allocate indirect mkey.\");\n \t\t\treturn -1;\n@@ -670,7 +672,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n-\tif (mlx5_devx_cq_create(priv->ctx, &qp->cq_obj, log_nb_desc,\n+\tif (mlx5_devx_cq_create(priv->dev_ctx->ctx, &qp->cq_obj, log_nb_desc,\n \t\t\t\t&cq_attr, socket_id) != 0) {\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto error;\n@@ -681,7 +683,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\trte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n-\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->ctx,\n+\tqp->umem_obj = mlx5_glue->devx_umem_reg(priv->dev_ctx->ctx,\n \t\t\t\t\t (void *)(uintptr_t)qp->umem_buf,\n \t\t\t\t\t umem_size,\n \t\t\t\t\t IBV_ACCESS_LOCAL_WRITE);\n@@ -697,7 +699,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tgoto error;\n \t}\n \tqp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;\n-\tattr.pd = priv->pdn;\n+\tattr.pd = priv->dev_ctx->pdn;\n \tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n \tattr.cqn = qp->cq_obj.cq->id;\n \tattr.log_page_size = rte_log2_u32(sysconf(_SC_PAGESIZE));\n@@ -708,7 +710,7 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \tattr.wq_umem_offset = 0;\n \tattr.dbr_umem_id = qp->umem_obj->umem_id;\n \tattr.dbr_address = RTE_BIT64(log_nb_desc) * priv->wqe_set_size;\n-\tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->ctx, &attr);\n+\tqp->qp_obj = mlx5_devx_cmd_create_qp(priv->dev_ctx->ctx, &attr);\n \tif (qp->qp_obj == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to create QP(%u).\", rte_errno);\n \t\tgoto error;\n@@ -782,58 +784,20 @@ static struct rte_cryptodev_ops mlx5_crypto_ops = {\n static void\n mlx5_crypto_hw_global_release(struct mlx5_crypto_priv *priv)\n {\n-\tif (priv->pd != NULL) {\n-\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n-\t\tpriv->pd = NULL;\n-\t}\n \tif (priv->uar != NULL) {\n \t\tmlx5_glue->devx_free_uar(priv->uar);\n \t\tpriv->uar = NULL;\n \t}\n }\n \n-static int\n-mlx5_crypto_pd_create(struct mlx5_crypto_priv *priv)\n-{\n-#ifdef HAVE_IBV_FLOW_DV_SUPPORT\n-\tstruct mlx5dv_obj obj;\n-\tstruct mlx5dv_pd pd_info;\n-\tint ret;\n-\n-\tpriv->pd = mlx5_glue->alloc_pd(priv->ctx);\n-\tif (priv->pd == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to allocate PD.\");\n-\t\treturn errno ? -errno : -ENOMEM;\n-\t}\n-\tobj.pd.in = priv->pd;\n-\tobj.pd.out = &pd_info;\n-\tret = mlx5_glue->dv_init_obj(&obj, MLX5DV_OBJ_PD);\n-\tif (ret != 0) {\n-\t\tDRV_LOG(ERR, \"Fail to get PD object info.\");\n-\t\tmlx5_glue->dealloc_pd(priv->pd);\n-\t\tpriv->pd = NULL;\n-\t\treturn -errno;\n-\t}\n-\tpriv->pdn = pd_info.pdn;\n-\treturn 0;\n-#else\n-\t(void)priv;\n-\tDRV_LOG(ERR, \"Cannot get pdn - no DV support.\");\n-\treturn -ENOTSUP;\n-#endif /* HAVE_IBV_FLOW_DV_SUPPORT */\n-}\n-\n static int\n mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)\n {\n-\tif (mlx5_crypto_pd_create(priv) != 0)\n-\t\treturn -1;\n-\tpriv->uar = mlx5_devx_alloc_uar(priv->ctx, -1);\n+\tpriv->uar = mlx5_devx_alloc_uar(priv->dev_ctx->ctx, -1);\n \tif (priv->uar)\n \t\tpriv->uar_addr = mlx5_os_get_devx_uar_reg_addr(priv->uar);\n \tif (priv->uar == NULL || priv->uar_addr == NULL) {\n \t\trte_errno = errno;\n-\t\tclaim_zero(mlx5_glue->dealloc_pd(priv->pd));\n \t\tDRV_LOG(ERR, \"Failed to allocate UAR.\");\n \t\treturn -1;\n \t}\n@@ -966,7 +930,8 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n \t\t/* Iterate all the existing mlx5 devices. */\n \t\tTAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)\n \t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n-\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t mlx5_os_get_ctx_device_name\n+\t\t\t\t\t\t\t (priv->dev_ctx->ctx),\n \t\t\t\t\t addr, len);\n \t\tpthread_mutex_unlock(&priv_list_lock);\n \t\tbreak;\n@@ -979,9 +944,8 @@ mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n static int\n mlx5_crypto_dev_probe(struct rte_device *dev)\n {\n-\tstruct ibv_device *ibv;\n \tstruct rte_cryptodev *crypto_dev;\n-\tstruct ibv_context *ctx;\n+\tstruct mlx5_dev_ctx *dev_ctx;\n \tstruct mlx5_devx_obj *login;\n \tstruct mlx5_crypto_priv *priv;\n \tstruct mlx5_crypto_devarg_params devarg_prms = { 0 };\n@@ -993,6 +957,7 @@ mlx5_crypto_dev_probe(struct rte_device *dev)\n \t\t.max_nb_queue_pairs =\n \t\t\t\tRTE_CRYPTODEV_PMD_DEFAULT_MAX_NB_QUEUE_PAIRS,\n \t};\n+\tconst char *ibdev_name;\n \tuint16_t rdmw_wqe_size;\n \tint ret;\n \n@@ -1001,57 +966,66 @@ mlx5_crypto_dev_probe(struct rte_device *dev)\n \t\trte_errno = ENOTSUP;\n \t\treturn -rte_errno;\n \t}\n-\tibv = mlx5_os_get_ibv_dev(dev);\n-\tif (ibv == NULL)\n+\tdev_ctx = mlx5_malloc(MLX5_MEM_ZERO, sizeof(struct mlx5_dev_ctx),\n+\t\t\t RTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n+\tif (dev_ctx == NULL) {\n+\t\tDRV_LOG(ERR, \"Device context allocation failure.\");\n+\t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n-\tctx = mlx5_glue->dv_open_device(ibv);\n-\tif (ctx == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to open IB device \\\"%s\\\".\", ibv->name);\n+\t}\n+\tret = mlx5_dev_ctx_prepare(dev_ctx, dev, MLX5_CLASS_CRYPTO);\n+\tif (ret < 0) {\n+\t\tDRV_LOG(ERR, \"Failed to create device context.\");\n+\t\tmlx5_free(dev_ctx);\n \t\trte_errno = ENODEV;\n \t\treturn -rte_errno;\n \t}\n-\tif (mlx5_devx_cmd_query_hca_attr(ctx, &attr) != 0 ||\n+\tibdev_name = mlx5_os_get_ctx_device_name(dev_ctx->ctx);\n+\tif (mlx5_devx_cmd_query_hca_attr(dev_ctx->ctx, &attr) != 0 ||\n \t attr.crypto == 0 || attr.aes_xts == 0) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support crypto \"\n \t\t\t\"operations, maybe old FW/OFED version?\");\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\tmlx5_dev_ctx_release(dev_ctx);\n+\t\tmlx5_free(dev_ctx);\n \t\trte_errno = ENOTSUP;\n \t\treturn -ENOTSUP;\n \t}\n \tret = mlx5_crypto_parse_devargs(dev->devargs, &devarg_prms);\n \tif (ret) {\n \t\tDRV_LOG(ERR, \"Failed to parse devargs.\");\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\tmlx5_dev_ctx_release(dev_ctx);\n+\t\tmlx5_free(dev_ctx);\n \t\treturn -rte_errno;\n \t}\n-\tlogin = mlx5_devx_cmd_create_crypto_login_obj(ctx,\n+\tlogin = mlx5_devx_cmd_create_crypto_login_obj(dev_ctx->ctx,\n \t\t\t\t\t\t &devarg_prms.login_attr);\n \tif (login == NULL) {\n \t\tDRV_LOG(ERR, \"Failed to configure login.\");\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\tmlx5_dev_ctx_release(dev_ctx);\n+\t\tmlx5_free(dev_ctx);\n \t\treturn -rte_errno;\n \t}\n-\tcrypto_dev = rte_cryptodev_pmd_create(ibv->name, dev,\n-\t\t\t\t\t&init_params);\n+\tcrypto_dev = rte_cryptodev_pmd_create(ibdev_name, dev, &init_params);\n \tif (crypto_dev == NULL) {\n-\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibv->name);\n-\t\tclaim_zero(mlx5_glue->close_device(ctx));\n+\t\tDRV_LOG(ERR, \"Failed to create device \\\"%s\\\".\", ibdev_name);\n+\t\tmlx5_dev_ctx_release(dev_ctx);\n+\t\tmlx5_free(dev_ctx);\n \t\treturn -ENODEV;\n \t}\n-\tDRV_LOG(INFO,\n-\t\t\"Crypto device %s was created successfully.\", ibv->name);\n+\tDRV_LOG(INFO, \"Crypto device %s was created successfully.\", ibdev_name);\n \tcrypto_dev->dev_ops = &mlx5_crypto_ops;\n \tcrypto_dev->dequeue_burst = mlx5_crypto_dequeue_burst;\n \tcrypto_dev->enqueue_burst = mlx5_crypto_enqueue_burst;\n \tcrypto_dev->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n \tcrypto_dev->driver_id = mlx5_crypto_driver_id;\n \tpriv = crypto_dev->data->dev_private;\n-\tpriv->ctx = ctx;\n+\tpriv->dev_ctx = dev_ctx;\n \tpriv->login_obj = login;\n \tpriv->crypto_dev = crypto_dev;\n \tif (mlx5_crypto_hw_global_prepare(priv) != 0) {\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\tmlx5_dev_ctx_release(priv->dev_ctx);\n+\t\tmlx5_free(priv->dev_ctx);\n \t\treturn -1;\n \t}\n \tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n@@ -1059,7 +1033,8 @@ mlx5_crypto_dev_probe(struct rte_device *dev)\n \t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n \t\tmlx5_crypto_hw_global_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\tmlx5_dev_ctx_release(priv->dev_ctx);\n+\t\tmlx5_free(priv->dev_ctx);\n \t\trte_errno = ENOMEM;\n \t\treturn -rte_errno;\n \t}\n@@ -1109,7 +1084,8 @@ mlx5_crypto_dev_remove(struct rte_device *dev)\n \t\tmlx5_crypto_hw_global_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\tclaim_zero(mlx5_devx_cmd_destroy(priv->login_obj));\n-\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\tmlx5_dev_ctx_release(priv->dev_ctx);\n+\t\tmlx5_free(priv->dev_ctx);\n \t}\n \treturn 0;\n }\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex d49b0001f0..7ae05f0b00 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -19,13 +19,11 @@\n \n struct mlx5_crypto_priv {\n \tTAILQ_ENTRY(mlx5_crypto_priv) next;\n-\tstruct ibv_context *ctx; /* Device context. */\n+\tstruct mlx5_dev_ctx *dev_ctx; /* Device context. */\n \tstruct rte_cryptodev *crypto_dev;\n \tvoid *uar; /* User Access Region. */\n \tvolatile uint64_t *uar_addr;\n-\tuint32_t pdn; /* Protection Domain number. */\n \tuint32_t max_segs_num; /* Maximum supported data segs. */\n-\tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tstruct rte_cryptodev_config dev_config;\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c\nindex 67b1fa3819..91c06fffbb 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto_dek.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c\n@@ -94,7 +94,7 @@ mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n \tstruct mlx5_crypto_dek *dek = rte_zmalloc(__func__, sizeof(*dek),\n \t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n \tstruct mlx5_devx_dek_attr dek_attr = {\n-\t\t.pd = ctx->priv->pdn,\n+\t\t.pd = ctx->priv->dev_ctx->pdn,\n \t\t.key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS,\n \t\t.has_keytag = 1,\n \t};\n@@ -117,7 +117,8 @@ mlx5_crypto_dek_create_cb(void *tool_ctx __rte_unused, void *cb_ctx)\n \t\treturn NULL;\n \t}\n \tmemcpy(&dek_attr.key, cipher_ctx->key.data, cipher_ctx->key.length);\n-\tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->ctx, &dek_attr);\n+\tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->dev_ctx->ctx,\n+\t\t\t\t\t\t&dek_attr);\n \tif (dek->obj == NULL) {\n \t\trte_free(dek);\n \t\treturn NULL;\n", "prefixes": [ "RFC", "05/21" ] }