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GET /api/patches/97061/?format=api
{ "id": 97061, "url": "http://patchwork.dpdk.org/api/patches/97061/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/patch/20210818151441.12400-3-rzidane@nvidia.com/", "project": { "id": 1, "url": "http://patchwork.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210818151441.12400-3-rzidane@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210818151441.12400-3-rzidane@nvidia.com", "date": "2021-08-18T15:14:40", "name": "[RFC,2/3] compress/mlx5: refactor queue creation in mlx5 add support to compress and regex drivers in BlueField3", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "1ff21c443929c57ee8b224ed757b1b0fb07347ed", "submitter": { "id": 2300, "url": "http://patchwork.dpdk.org/api/people/2300/?format=api", "name": "Raja Zidane", "email": "rzidane@nvidia.com" }, "delegate": { "id": 1, "url": "http://patchwork.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "http://patchwork.dpdk.org/project/dpdk/patch/20210818151441.12400-3-rzidane@nvidia.com/mbox/", "series": [ { "id": 18334, "url": "http://patchwork.dpdk.org/api/series/18334/?format=api", "web_url": "http://patchwork.dpdk.org/project/dpdk/list/?series=18334", "date": "2021-08-18T15:14:38", "name": "mlx5: replaced hardware queue object", "version": 1, "mbox": "http://patchwork.dpdk.org/series/18334/mbox/" } ], "comments": "http://patchwork.dpdk.org/api/patches/97061/comments/", "check": "warning", "checks": "http://patchwork.dpdk.org/api/patches/97061/checks/", "tags": {}, "related": [], "headers": { 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SFS:(4636009)(39860400002)(396003)(136003)(346002)(376002)(46966006)(36840700001)(6916009)(55016002)(36756003)(16526019)(4326008)(2906002)(86362001)(7696005)(426003)(336012)(186003)(107886003)(26005)(478600001)(2616005)(6666004)(82310400003)(30864003)(36860700001)(8936002)(70206006)(47076005)(5660300002)(8676002)(6286002)(356005)(70586007)(1076003)(316002)(83380400001)(54906003)(7636003)(82740400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "18 Aug 2021 15:15:11.2173 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 20d8e88b-d3cb-416e-21f3-08d9625af904", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.36];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT036.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BYAPR12MB3574", "Subject": "[dpdk-dev] [RFC 2/3] compress/mlx5: refactor queue creation in mlx5\n add support to compress and regex drivers in BlueField3", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Signed-off-by: Raja Zidane <rzidane@nvidia.com>\n---\n drivers/common/mlx5/mlx5_devx_cmds.c | 14 ++++-\n drivers/common/mlx5/mlx5_devx_cmds.h | 10 ++-\n drivers/common/mlx5/mlx5_prm.h | 42 +++++++++++--\n drivers/compress/mlx5/mlx5_compress.c | 91 ++++++++++++++++++---------\n 4 files changed, 116 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c\nindex 56407cc332..347ae75d37 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.c\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.c\n@@ -858,9 +858,12 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,\n \tattr->log_max_srq_sz = MLX5_GET(cmd_hca_cap, hcattr, log_max_srq_sz);\n \tattr->reg_c_preserve =\n \t\tMLX5_GET(cmd_hca_cap, hcattr, reg_c_preserve);\n-\tattr->mmo_dma_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo);\n-\tattr->mmo_compress_en = MLX5_GET(cmd_hca_cap, hcattr, compress);\n-\tattr->mmo_decompress_en = MLX5_GET(cmd_hca_cap, hcattr, decompress);\n+\tattr->mmo_dma_sq_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_sq);\n+\tattr->mmo_compress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, compress_mmo_sq);\n+\tattr->mmo_decompress_sq_en = MLX5_GET(cmd_hca_cap, hcattr, decompress_mmo_sq);\n+\tattr->mmo_dma_qp_en = MLX5_GET(cmd_hca_cap, hcattr, dma_mmo_qp);\n+\tattr->mmo_compress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, compress_mmo_qp);\n+\tattr->mmo_decompress_qp_en = MLX5_GET(cmd_hca_cap, hcattr, decompress_mmo_qp);\n \tattr->compress_min_block_size = MLX5_GET(cmd_hca_cap, hcattr,\n \t\t\t\t\t\t compress_min_block_size);\n \tattr->log_max_mmo_dma = MLX5_GET(cmd_hca_cap, hcattr, log_dma_mmo_size);\n@@ -2022,6 +2025,11 @@ mlx5_devx_cmd_create_qp(void *ctx,\n \tMLX5_SET(qpc, qpc, pd, attr->pd);\n \tMLX5_SET(qpc, qpc, ts_format, attr->ts_format);\n \tif (attr->uar_index) {\n+\t\tif(attr->mmo) {\n+\t\t\tvoid *qpc_ext_and_pas_list = MLX5_ADDR_OF(create_qp_in, in, qpc_extension_and_pas_list);\n+\t\t\tvoid* qpc_ext = MLX5_ADDR_OF(qpc_extension_and_pas_list, qpc_ext_and_pas_list, qpc_data_extension);\n+\t\t\tMLX5_SET(qpc_extension, qpc_ext, mmo, 1);\n+\t\t}\n \t\tMLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);\n \t\tMLX5_SET(qpc, qpc, uar_page, attr->uar_index);\n \t\tif (attr->log_page_size > MLX5_ADAPTER_PAGE_SHIFT)\ndiff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h\nindex e576e30f24..f993b511dc 100644\n--- a/drivers/common/mlx5/mlx5_devx_cmds.h\n+++ b/drivers/common/mlx5/mlx5_devx_cmds.h\n@@ -173,9 +173,12 @@ struct mlx5_hca_attr {\n \tuint32_t log_max_srq;\n \tuint32_t log_max_srq_sz;\n \tuint32_t rss_ind_tbl_cap;\n-\tuint32_t mmo_dma_en:1;\n-\tuint32_t mmo_compress_en:1;\n-\tuint32_t mmo_decompress_en:1;\n+\tuint32_t mmo_dma_sq_en:1;\n+\tuint32_t mmo_compress_sq_en:1;\n+\tuint32_t mmo_decompress_sq_en:1;\n+\tuint32_t mmo_dma_qp_en:1;\n+\tuint32_t mmo_compress_qp_en:1;\n+\tuint32_t mmo_decompress_qp_en:1;\n \tuint32_t compress_min_block_size:4;\n \tuint32_t log_max_mmo_dma:5;\n \tuint32_t log_max_mmo_compress:5;\n@@ -397,6 +400,7 @@ struct mlx5_devx_qp_attr {\n \tuint64_t dbr_address;\n \tuint32_t wq_umem_id;\n \tuint64_t wq_umem_offset;\n+\tuint32_t mmo;\n };\n \n struct mlx5_devx_virtio_q_couners_attr {\ndiff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h\nindex fdb20f5d49..d0c75b97df 100644\n--- a/drivers/common/mlx5/mlx5_prm.h\n+++ b/drivers/common/mlx5/mlx5_prm.h\n@@ -1385,10 +1385,10 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 rtr2rts_qp_counters_set_id[0x1];\n \tu8 rts2rts_udp_sport[0x1];\n \tu8 rts2rts_lag_tx_port_affinity[0x1];\n-\tu8 dma_mmo[0x1];\n+\tu8 dma_mmo_sq[0x1];\n \tu8 compress_min_block_size[0x4];\n-\tu8 compress[0x1];\n-\tu8 decompress[0x1];\n+\tu8 compress_mmo_sq[0x1];\n+\tu8 decompress_mmo_sq[0x1];\n \tu8 log_max_ra_res_qp[0x6];\n \tu8 end_pad[0x1];\n \tu8 cc_query_allowed[0x1];\n@@ -1631,7 +1631,12 @@ struct mlx5_ifc_cmd_hca_cap_bits {\n \tu8 num_vhca_ports[0x8];\n \tu8 reserved_at_618[0x6];\n \tu8 sw_owner_id[0x1];\n-\tu8 reserved_at_61f[0x1e1];\n+\tu8 reserved_at_61f[0x109];\n+\tu8 dma_mmo_qp[0x1];\n+\tu8 reserved_at_621[0x1];\n+\tu8 compress_mmo_qp[0x1];\n+\tu8 decompress_mmo_qp[0x1];\n+\tu8 reserved_at_624[0xd4];\n };\n \n struct mlx5_ifc_qos_cap_bits {\n@@ -3235,6 +3240,27 @@ struct mlx5_ifc_create_qp_out_bits {\n \tu8 reserved_at_60[0x20];\n };\n \n+struct mlx5_ifc_qpc_extension_bits {\n+\tu8 reserved_at_0[0x2];\n+\tu8 mmo[0x1];\n+\tu8 reserved_at_3[0x5fd];\n+};\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+struct mlx5_ifc_qpc_pas_list_bits {\n+\tu8 pas[0][0x40];\n+};\n+\n+#ifdef PEDANTIC\n+#pragma GCC diagnostic ignored \"-Wpedantic\"\n+#endif\n+struct mlx5_ifc_qpc_extension_and_pas_list_bits {\n+\tstruct mlx5_ifc_qpc_extension_bits qpc_data_extension;\n+\tu8 pas[0][0x40];\n+};\n+\n #ifdef PEDANTIC\n #pragma GCC diagnostic ignored \"-Wpedantic\"\n #endif\n@@ -3243,7 +3269,8 @@ struct mlx5_ifc_create_qp_in_bits {\n \tu8 uid[0x10];\n \tu8 reserved_at_20[0x10];\n \tu8 op_mod[0x10];\n-\tu8 reserved_at_40[0x40];\n+\tu8 qpc_ext[0x1];\n+\tu8 reserved_at_41[0x3f];\n \tu8 opt_param_mask[0x20];\n \tu8 reserved_at_a0[0x20];\n \tstruct mlx5_ifc_qpc_bits qpc;\n@@ -3251,7 +3278,10 @@ struct mlx5_ifc_create_qp_in_bits {\n \tu8 wq_umem_id[0x20];\n \tu8 wq_umem_valid[0x1];\n \tu8 reserved_at_861[0x1f];\n-\tu8 pas[0][0x40];\n+\tunion {\n+\t\tstruct mlx5_ifc_qpc_pas_list_bits qpc_pas_list;\n+\t\tstruct mlx5_ifc_qpc_extension_and_pas_list_bits qpc_extension_and_pas_list;\n+\t};\n };\n #ifdef PEDANTIC\n #pragma GCC diagnostic error \"-Wpedantic\"\ndiff --git a/drivers/compress/mlx5/mlx5_compress.c b/drivers/compress/mlx5/mlx5_compress.c\nindex 883e720ec1..05e75adb1c 100644\n--- a/drivers/compress/mlx5/mlx5_compress.c\n+++ b/drivers/compress/mlx5/mlx5_compress.c\n@@ -48,6 +48,7 @@ struct mlx5_compress_priv {\n \trte_spinlock_t xform_sl;\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n \tvolatile uint64_t *uar_addr;\n+\tuint8_t mmo_caps; /* bitmap 0->5: decomp_sq, decomp_qp, comp_sq, comp_qp, dma_sq, dma_qp */\n #ifndef RTE_ARCH_64\n \trte_spinlock_t uar32_sl;\n #endif /* RTE_ARCH_64 */\n@@ -61,7 +62,7 @@ struct mlx5_compress_qp {\n \tstruct mlx5_mr_ctrl mr_ctrl;\n \tint socket_id;\n \tstruct mlx5_devx_cq cq;\n-\tstruct mlx5_devx_sq sq;\n+\tstruct mlx5_devx_qp qp;\n \tstruct mlx5_pmd_mr opaque_mr;\n \tstruct rte_comp_op **ops;\n \tstruct mlx5_compress_priv *priv;\n@@ -134,8 +135,8 @@ mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)\n {\n \tstruct mlx5_compress_qp *qp = dev->data->queue_pairs[qp_id];\n \n-\tif (qp->sq.sq != NULL)\n-\t\tmlx5_devx_sq_destroy(&qp->sq);\n+\tif (qp->qp.qp != NULL)\n+\t\tmlx5_devx_qp_destroy(&qp->qp);\n \tif (qp->cq.cq != NULL)\n \t\tmlx5_devx_cq_destroy(&qp->cq);\n \tif (qp->opaque_mr.obj != NULL) {\n@@ -152,12 +153,12 @@ mlx5_compress_qp_release(struct rte_compressdev *dev, uint16_t qp_id)\n }\n \n static void\n-mlx5_compress_init_sq(struct mlx5_compress_qp *qp)\n+mlx5_compress_init_qp(struct mlx5_compress_qp *qp)\n {\n \tvolatile struct mlx5_gga_wqe *restrict wqe =\n-\t\t\t\t (volatile struct mlx5_gga_wqe *)qp->sq.wqes;\n+\t\t\t\t (volatile struct mlx5_gga_wqe *)qp->qp.wqes;\n \tvolatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n-\tconst uint32_t sq_ds = rte_cpu_to_be_32((qp->sq.sq->id << 8) | 4u);\n+\tconst uint32_t sq_ds = rte_cpu_to_be_32((qp->qp.qp->id << 8) | 4u);\n \tconst uint32_t flags = RTE_BE32(MLX5_COMP_ALWAYS <<\n \t\t\t\t\tMLX5_COMP_MODE_OFFSET);\n \tconst uint32_t opaq_lkey = rte_cpu_to_be_32(qp->opaque_mr.lkey);\n@@ -173,6 +174,35 @@ mlx5_compress_init_sq(struct mlx5_compress_qp *qp)\n \t}\n }\n \n+static int\n+mlx5_compress_qp2rts(struct mlx5_compress_qp *qp)\n+{\n+\t/*\n+\t * In Order to configure self loopback, when calling these functions the\n+\t * remote QP id that is used is the id of the same QP.\n+\t */\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_RST2INIT_QP,\n+\t\t\t\t\t qp->qp.qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to INIT state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_INIT2RTR_QP,\n+\t\t\t\t\t qp->qp.qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to RTR state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\tif (mlx5_devx_cmd_modify_qp_state(qp->qp.qp, MLX5_CMD_OP_RTR2RTS_QP,\n+\t\t\t\t\t qp->qp.qp->id)) {\n+\t\tDRV_LOG(ERR, \"Failed to modify QP to RTS state(%u).\",\n+\t\t\trte_errno);\n+\t\treturn -1;\n+\t}\n+\treturn 0;\n+}\n+\n+\n static int\n mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\t uint32_t max_inflight_ops, int socket_id)\n@@ -182,15 +212,9 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \tstruct mlx5_devx_cq_attr cq_attr = {\n \t\t.uar_page_id = mlx5_os_get_devx_uar_page_id(priv->uar),\n \t};\n-\tstruct mlx5_devx_create_sq_attr sq_attr = {\n-\t\t.user_index = qp_id,\n-\t\t.wq_attr = (struct mlx5_devx_wq_attr){\n-\t\t\t.pd = priv->pdn,\n-\t\t\t.uar_page = mlx5_os_get_devx_uar_page_id(priv->uar),\n-\t\t},\n-\t};\n-\tstruct mlx5_devx_modify_sq_attr modify_attr = {\n-\t\t.state = MLX5_SQC_STATE_RDY,\n+\tstruct mlx5_devx_qp_attr qp_attr = {\n+\t\t.pd = priv->pdn,\n+\t\t.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar),\n \t};\n \tuint32_t log_ops_n = rte_log2_u32(max_inflight_ops);\n \tuint32_t alloc_size = sizeof(*qp);\n@@ -242,24 +266,26 @@ mlx5_compress_qp_setup(struct rte_compressdev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Failed to create CQ.\");\n \t\tgoto err;\n \t}\n-\tsq_attr.cqn = qp->cq.cq->id;\n-\tsq_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);\n-\tret = mlx5_devx_sq_create(priv->ctx, &qp->sq, log_ops_n, &sq_attr,\n+\tqp_attr.cqn = qp->cq.cq->id;\n+\tqp_attr.ts_format = mlx5_ts_format_conv(priv->sq_ts_format);\n+\tqp_attr.rq_size = 0;\n+\tqp_attr.sq_size = 1 << log_ops_n;\n+\tqp_attr.mmo = (priv->mmo_caps & (1<<1)) && (priv->mmo_caps & (1<<3)) && (priv->mmo_caps & (1<<5));\n+\tret = mlx5_devx_qp_create(priv->ctx, &qp->qp, log_ops_n, &qp_attr,\n \t\t\t\t socket_id);\n \tif (ret != 0) {\n-\t\tDRV_LOG(ERR, \"Failed to create SQ.\");\n+\t\tDRV_LOG(ERR, \"Failed to create QP.\");\n \t\tgoto err;\n \t}\n-\tmlx5_compress_init_sq(qp);\n-\tret = mlx5_devx_cmd_modify_sq(qp->sq.sq, &modify_attr);\n-\tif (ret != 0) {\n-\t\tDRV_LOG(ERR, \"Can't change SQ state to ready.\");\n+\tret = mlx5_compress_qp2rts(qp);\n+\tif(ret) {\n \t\tgoto err;\n \t}\n+\tmlx5_compress_init_qp(qp);\n \t/* Save pointer of global generation number to check memory event. */\n \tqp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;\n \tDRV_LOG(INFO, \"QP %u: SQN=0x%X CQN=0x%X entries num = %u\",\n-\t\t(uint32_t)qp_id, qp->sq.sq->id, qp->cq.cq->id, qp->entries_n);\n+\t\t(uint32_t)qp_id, qp->qp.qp->id, qp->cq.cq->id, qp->entries_n);\n \treturn 0;\n err:\n \tmlx5_compress_qp_release(dev, qp_id);\n@@ -508,7 +534,7 @@ mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,\n {\n \tstruct mlx5_compress_qp *qp = queue_pair;\n \tvolatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)\n-\t\t\t\t\t\t\t qp->sq.wqes, *wqe;\n+\t\t\t\t\t\t\t qp->qp.wqes, *wqe;\n \tstruct mlx5_compress_xform *xform;\n \tstruct rte_comp_op *op;\n \tuint16_t mask = qp->entries_n - 1;\n@@ -563,7 +589,7 @@ mlx5_compress_enqueue_burst(void *queue_pair, struct rte_comp_op **ops,\n \t} while (--remain);\n \tqp->stats.enqueued_count += nb_ops;\n \trte_io_wmb();\n-\tqp->sq.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);\n+\tqp->qp.db_rec[MLX5_SND_DBR] = rte_cpu_to_be_32(qp->pi);\n \trte_wmb();\n \tmlx5_compress_uar_write(*(volatile uint64_t *)wqe, qp->priv);\n \trte_wmb();\n@@ -598,7 +624,7 @@ mlx5_compress_cqe_err_handle(struct mlx5_compress_qp *qp,\n \tvolatile struct mlx5_err_cqe *cqe = (volatile struct mlx5_err_cqe *)\n \t\t\t\t\t\t\t &qp->cq.cqes[idx];\n \tvolatile struct mlx5_gga_wqe *wqes = (volatile struct mlx5_gga_wqe *)\n-\t\t\t\t\t\t\t\t qp->sq.wqes;\n+\t\t\t\t\t\t\t\t qp->qp.wqes;\n \tvolatile struct mlx5_gga_compress_opaque *opaq = qp->opaque_mr.addr;\n \n \top->status = RTE_COMP_OP_STATUS_ERROR;\n@@ -813,8 +839,9 @@ mlx5_compress_dev_probe(struct rte_device *dev)\n \t\treturn -rte_errno;\n \t}\n \tif (mlx5_devx_cmd_query_hca_attr(ctx, &att) != 0 ||\n-\t att.mmo_compress_en == 0 || att.mmo_decompress_en == 0 ||\n-\t att.mmo_dma_en == 0) {\n+\t ((att.mmo_compress_sq_en == 0 || att.mmo_decompress_sq_en == 0 ||\n+\t \tatt.mmo_dma_sq_en == 0) && (att.mmo_compress_qp_en == 0 || \n+\t\t\t\tatt.mmo_decompress_qp_en == 0 || att.mmo_dma_qp_en == 0))) {\n \t\tDRV_LOG(ERR, \"Not enough capabilities to support compress \"\n \t\t\t\"operations, maybe old FW/OFED version?\");\n \t\tclaim_zero(mlx5_glue->close_device(ctx));\n@@ -835,6 +862,12 @@ mlx5_compress_dev_probe(struct rte_device *dev)\n \tcdev->enqueue_burst = mlx5_compress_enqueue_burst;\n \tcdev->feature_flags = RTE_COMPDEV_FF_HW_ACCELERATED;\n \tpriv = cdev->data->dev_private;\n+\tpriv->mmo_caps = 0 | att.mmo_decompress_sq_en;\n+\tpriv->mmo_caps |= att.mmo_decompress_qp_en << 1;\n+\tpriv->mmo_caps |= att.mmo_compress_sq_en << 2;\n+\tpriv->mmo_caps |= att.mmo_compress_qp_en << 3;\n+\tpriv->mmo_caps |= att.mmo_dma_sq_en << 4;\n+\tpriv->mmo_caps |= att.mmo_dma_qp_en << 5;\n \tpriv->ctx = ctx;\n \tpriv->cdev = cdev;\n \tpriv->min_block_size = att.compress_min_block_size;\n", "prefixes": [ "RFC", "2/3" ] }